1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32K344_SXOSC.h 10 * @version 1.9 11 * @date 2021-10-27 12 * @brief Peripheral Access Layer for S32K344_SXOSC 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32K344_SXOSC_H_) /* Check if memory map has not been already included */ 58 #define S32K344_SXOSC_H_ 59 60 #include "S32K344_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- SXOSC Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup SXOSC_Peripheral_Access_Layer SXOSC Peripheral Access Layer 68 * @{ 69 */ 70 71 /** SXOSC - Register Layout Typedef */ 72 typedef struct { 73 __IO uint32_t SXOSC_CTRL; /**< Oscillator Control, offset: 0x0 */ 74 __I uint32_t SXOSC_STAT; /**< Oscillator Status, offset: 0x4 */ 75 } SXOSC_Type, *SXOSC_MemMapPtr; 76 77 /** Number of instances of the SXOSC module. */ 78 #define SXOSC_INSTANCE_COUNT (1u) 79 80 /* SXOSC - Peripheral instance base addresses */ 81 /** Peripheral SXOSC base address */ 82 #define IP_SXOSC_BASE (0x402CC000u) 83 /** Peripheral SXOSC base pointer */ 84 #define IP_SXOSC ((SXOSC_Type *)IP_SXOSC_BASE) 85 /** Array initializer of SXOSC peripheral base addresses */ 86 #define IP_SXOSC_BASE_ADDRS { IP_SXOSC_BASE } 87 /** Array initializer of SXOSC peripheral base pointers */ 88 #define IP_SXOSC_BASE_PTRS { IP_SXOSC } 89 90 /* ---------------------------------------------------------------------------- 91 -- SXOSC Register Masks 92 ---------------------------------------------------------------------------- */ 93 94 /*! 95 * @addtogroup SXOSC_Register_Masks SXOSC Register Masks 96 * @{ 97 */ 98 99 /*! @name SXOSC_CTRL - Oscillator Control */ 100 /*! @{ */ 101 102 #define SXOSC_SXOSC_CTRL_OSCON_MASK (0x1U) 103 #define SXOSC_SXOSC_CTRL_OSCON_SHIFT (0U) 104 #define SXOSC_SXOSC_CTRL_OSCON_WIDTH (1U) 105 #define SXOSC_SXOSC_CTRL_OSCON(x) (((uint32_t)(((uint32_t)(x)) << SXOSC_SXOSC_CTRL_OSCON_SHIFT)) & SXOSC_SXOSC_CTRL_OSCON_MASK) 106 107 #define SXOSC_SXOSC_CTRL_EOCV_MASK (0xFF0000U) 108 #define SXOSC_SXOSC_CTRL_EOCV_SHIFT (16U) 109 #define SXOSC_SXOSC_CTRL_EOCV_WIDTH (8U) 110 #define SXOSC_SXOSC_CTRL_EOCV(x) (((uint32_t)(((uint32_t)(x)) << SXOSC_SXOSC_CTRL_EOCV_SHIFT)) & SXOSC_SXOSC_CTRL_EOCV_MASK) 111 /*! @} */ 112 113 /*! @name SXOSC_STAT - Oscillator Status */ 114 /*! @{ */ 115 116 #define SXOSC_SXOSC_STAT_OSC_STAT_MASK (0x80000000U) 117 #define SXOSC_SXOSC_STAT_OSC_STAT_SHIFT (31U) 118 #define SXOSC_SXOSC_STAT_OSC_STAT_WIDTH (1U) 119 #define SXOSC_SXOSC_STAT_OSC_STAT(x) (((uint32_t)(((uint32_t)(x)) << SXOSC_SXOSC_STAT_OSC_STAT_SHIFT)) & SXOSC_SXOSC_STAT_OSC_STAT_MASK) 120 /*! @} */ 121 122 /*! 123 * @} 124 */ /* end of group SXOSC_Register_Masks */ 125 126 /*! 127 * @} 128 */ /* end of group SXOSC_Peripheral_Access_Layer */ 129 130 #endif /* #if !defined(S32K344_SXOSC_H_) */ 131
