1 /** 2 ****************************************************************************** 3 * @file stts22h_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * stts22h_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STTS22H_REGS_H 23 #define STTS22H_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup STTS22H 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *, uint8_t, const uint8_t *, uint16_t); 113 typedef int32_t (*stmdev_read_ptr)(void *, uint8_t, uint8_t *, uint16_t); 114 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 115 116 typedef struct 117 { 118 /** Component mandatory fields **/ 119 stmdev_write_ptr write_reg; 120 stmdev_read_ptr read_reg; 121 /** Component optional fields **/ 122 stmdev_mdelay_ptr mdelay; 123 /** Customizable optional pointer **/ 124 void *handle; 125 } stmdev_ctx_t; 126 127 /** 128 * @} 129 * 130 */ 131 132 #endif /* MEMS_SHARED_TYPES */ 133 134 #ifndef MEMS_UCF_SHARED_TYPES 135 #define MEMS_UCF_SHARED_TYPES 136 137 /** @defgroup Generic address-data structure definition 138 * @brief This structure is useful to load a predefined configuration 139 * of a sensor. 140 * You can create a sensor configuration by your own or using 141 * Unico / Unicleo tools available on STMicroelectronics 142 * web site. 143 * 144 * @{ 145 * 146 */ 147 148 typedef struct 149 { 150 uint8_t address; 151 uint8_t data; 152 } ucf_line_t; 153 154 /** 155 * @} 156 * 157 */ 158 159 #endif /* MEMS_UCF_SHARED_TYPES */ 160 161 /** 162 * @} 163 * 164 */ 165 166 /** @defgroup STTS22H_Infos 167 * @{ 168 * 169 */ 170 171 /** I2C Device Address 8 bit format **/ 172 #define STTS22H_I2C_ADD_H 0x71U 173 #define STTS22H_I2C_ADD_L 0x7FU 174 175 /** Device Identification (Who am I) **/ 176 #define STTS22H_ID 0xA0U 177 178 /** 179 * @} 180 * 181 */ 182 183 #define STTS22H_WHOAMI 0x01U 184 #define STTS22H_TEMP_H_LIMIT 0x02U 185 typedef struct 186 { 187 uint8_t thl : 8; 188 } stts22h_temp_h_limit_t; 189 190 #define STTS22H_TEMP_L_LIMIT 0x03U 191 typedef struct 192 { 193 uint8_t tll : 8; 194 } stts22h_temp_l_limit_t; 195 196 #define STTS22H_CTRL 0x04U 197 typedef struct 198 { 199 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 200 uint8_t one_shot : 1; 201 uint8_t time_out_dis : 1; 202 uint8_t freerun : 1; 203 uint8_t if_add_inc : 1; 204 uint8_t avg : 2; 205 uint8_t bdu : 1; 206 uint8_t low_odr_start : 1; 207 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 208 uint8_t low_odr_start : 1; 209 uint8_t bdu : 1; 210 uint8_t avg : 2; 211 uint8_t if_add_inc : 1; 212 uint8_t freerun : 1; 213 uint8_t time_out_dis : 1; 214 uint8_t one_shot : 1; 215 #endif /* DRV_BYTE_ORDER */ 216 } stts22h_ctrl_t; 217 218 #define STTS22H_STATUS 0x05U 219 typedef struct 220 { 221 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 222 uint8_t busy : 1; 223 uint8_t over_thh : 1; 224 uint8_t under_thl : 1; 225 uint8_t not_used_01 : 5; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t not_used_01 : 5; 228 uint8_t under_thl : 1; 229 uint8_t over_thh : 1; 230 uint8_t busy : 1; 231 #endif /* DRV_BYTE_ORDER */ 232 } stts22h_status_t; 233 234 #define STTS22H_TEMP_L_OUT 0x06U 235 #define STTS22H_TEMP_H_OUT 0x07U 236 237 /** 238 * @defgroup STTS22H_Register_Union 239 * @brief This union group all the registers having a bit-field 240 * description. 241 * This union is useful but it's not needed by the driver. 242 * 243 * REMOVING this union you are compliant with: 244 * MISRA-C 2012 [Rule 19.2] -> " Union are not allowed " 245 * 246 * @{ 247 * 248 */ 249 typedef union 250 { 251 stts22h_temp_h_limit_t temp_h_limit; 252 stts22h_temp_l_limit_t temp_l_limit; 253 stts22h_ctrl_t ctrl; 254 stts22h_status_t status; 255 bitwise_t bitwise; 256 uint8_t byte; 257 } stts22h_reg_t; 258 259 /** 260 * @} 261 * 262 */ 263 264 #ifndef __weak 265 #define __weak __attribute__((weak)) 266 #endif /* __weak */ 267 268 /* 269 * These are the basic platform dependent I/O routines to read 270 * and write device registers connected on a standard bus. 271 * The driver keeps offering a default implementation based on function 272 * pointers to read/write routines for backward compatibility. 273 * The __weak directive allows the final application to overwrite 274 * them with a custom implementation. 275 */ 276 277 int32_t stts22h_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 278 uint8_t *data, 279 uint16_t len); 280 int32_t stts22h_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 281 uint8_t *data, 282 uint16_t len); 283 284 float_t stts22h_from_lsb_to_celsius(int16_t lsb); 285 286 typedef enum 287 { 288 STTS22H_POWER_DOWN = 0x00, 289 STTS22H_ONE_SHOT = 0x01, 290 STTS22H_1Hz = 0x04, 291 STTS22H_25Hz = 0x02, 292 STTS22H_50Hz = 0x12, 293 STTS22H_100Hz = 0x22, 294 STTS22H_200Hz = 0x32, 295 } stts22h_odr_temp_t; 296 int32_t stts22h_temp_data_rate_set(const stmdev_ctx_t *ctx, 297 stts22h_odr_temp_t val); 298 int32_t stts22h_temp_data_rate_get(const stmdev_ctx_t *ctx, 299 stts22h_odr_temp_t *val); 300 301 int32_t stts22h_block_data_update_set(const stmdev_ctx_t *ctx, uint8_t val); 302 int32_t stts22h_block_data_update_get(const stmdev_ctx_t *ctx, 303 uint8_t *val); 304 305 int32_t stts22h_temp_flag_data_ready_get(const stmdev_ctx_t *ctx, 306 uint8_t *val); 307 308 int32_t stts22h_temperature_raw_get(const stmdev_ctx_t *ctx, int16_t *val); 309 310 int32_t stts22h_dev_id_get(const stmdev_ctx_t *ctx, uint8_t *buff); 311 312 typedef struct 313 { 314 uint8_t busy : 1; 315 } stts22h_dev_status_t; 316 int32_t stts22h_dev_status_get(const stmdev_ctx_t *ctx, 317 stts22h_dev_status_t *val); 318 319 typedef enum 320 { 321 STTS22H_SMBUS_TIMEOUT_ENABLE = 0, 322 STTS22H_SMBUS_TIMEOUT_DISABLE = 1, 323 } stts22h_smbus_md_t; 324 int32_t stts22h_smbus_interface_set(const stmdev_ctx_t *ctx, 325 stts22h_smbus_md_t val); 326 int32_t stts22h_smbus_interface_get(const stmdev_ctx_t *ctx, 327 stts22h_smbus_md_t *val); 328 329 int32_t stts22h_auto_increment_set(const stmdev_ctx_t *ctx, uint8_t val); 330 int32_t stts22h_auto_increment_get(const stmdev_ctx_t *ctx, uint8_t *val); 331 332 int32_t stts22h_temp_trshld_high_set(const stmdev_ctx_t *ctx, uint8_t val); 333 int32_t stts22h_temp_trshld_high_get(const stmdev_ctx_t *ctx, uint8_t *val); 334 335 int32_t stts22h_temp_trshld_low_set(const stmdev_ctx_t *ctx, uint8_t val); 336 int32_t stts22h_temp_trshld_low_get(const stmdev_ctx_t *ctx, uint8_t *val); 337 338 typedef struct 339 { 340 uint8_t under_thl : 1; 341 uint8_t over_thh : 1; 342 } stts22h_temp_trlhd_src_t; 343 int32_t stts22h_temp_trshld_src_get(const stmdev_ctx_t *ctx, 344 stts22h_temp_trlhd_src_t *val); 345 346 /** 347 *@} 348 * 349 */ 350 351 #ifdef __cplusplus 352 } 353 #endif 354 355 #endif /* STTS22H_REGS_H */ 356 357 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 358
