1 /* 2 * Copyright (c) 2016 Open-RnD Sp. z o.o. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @brief Driver for UART port on STM32 family processor. 9 * 10 */ 11 12 #ifndef ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_ 13 #define ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_ 14 15 #include <zephyr/drivers/pinctrl.h> 16 #include <zephyr/drivers/reset.h> 17 #include <zephyr/drivers/uart.h> 18 19 #include <stm32_ll_usart.h> 20 21 #define STM32_UART_DEFAULT_BAUDRATE 115200 22 #define STM32_UART_DEFAULT_PARITY UART_CFG_PARITY_NONE 23 #define STM32_UART_DEFAULT_STOP_BITS UART_CFG_STOP_BITS_1 24 #define STM32_UART_DEFAULT_DATA_BITS UART_CFG_DATA_BITS_8 25 26 /* device config */ 27 struct uart_stm32_config { 28 /* USART instance */ 29 USART_TypeDef *usart; 30 /* Reset controller device configuration */ 31 const struct reset_dt_spec reset; 32 /* clock subsystem driving this peripheral */ 33 const struct stm32_pclken *pclken; 34 /* number of clock subsystems */ 35 size_t pclk_len; 36 /* switch to enable single wire / half duplex feature */ 37 bool single_wire; 38 /* enable tx/rx pin swap */ 39 bool tx_rx_swap; 40 /* enable rx pin inversion */ 41 bool rx_invert; 42 /* enable tx pin inversion */ 43 bool tx_invert; 44 /* enable de signal */ 45 bool de_enable; 46 /* de signal assertion time in 1/16 of a bit */ 47 uint8_t de_assert_time; 48 /* de signal deassertion time in 1/16 of a bit */ 49 uint8_t de_deassert_time; 50 /* enable de pin inversion */ 51 bool de_invert; 52 /* enable fifo */ 53 bool fifo_enable; 54 /* pin muxing */ 55 const struct pinctrl_dev_config *pcfg; 56 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) || \ 57 defined(CONFIG_PM) 58 uart_irq_config_func_t irq_config_func; 59 #endif 60 #if defined(CONFIG_PM) 61 /* Device defined as wake-up source */ 62 bool wakeup_source; 63 uint32_t wakeup_line; 64 #endif /* CONFIG_PM */ 65 }; 66 67 #ifdef CONFIG_UART_ASYNC_API 68 struct uart_dma_stream { 69 const struct device *dma_dev; 70 uint32_t dma_channel; 71 struct dma_config dma_cfg; 72 uint8_t priority; 73 bool src_addr_increment; 74 bool dst_addr_increment; 75 int fifo_threshold; 76 struct dma_block_config blk_cfg; 77 uint8_t *buffer; 78 size_t buffer_length; 79 size_t offset; 80 volatile size_t counter; 81 int32_t timeout; 82 struct k_work_delayable timeout_work; 83 bool enabled; 84 }; 85 #endif 86 87 /* driver data */ 88 struct uart_stm32_data { 89 /* clock device */ 90 const struct device *clock; 91 /* uart config */ 92 struct uart_config *uart_cfg; 93 #ifdef CONFIG_UART_INTERRUPT_DRIVEN 94 uart_irq_callback_user_data_t user_cb; 95 void *user_data; 96 #endif 97 98 #ifdef CONFIG_UART_ASYNC_API 99 const struct device *uart_dev; 100 uart_callback_t async_cb; 101 void *async_user_data; 102 struct uart_dma_stream dma_rx; 103 struct uart_dma_stream dma_tx; 104 uint8_t *rx_next_buffer; 105 size_t rx_next_buffer_len; 106 #endif 107 #ifdef CONFIG_PM 108 bool tx_poll_stream_on; 109 bool tx_int_stream_on; 110 bool pm_policy_state_on; 111 #endif 112 }; 113 114 #endif /* ZEPHYR_DRIVERS_SERIAL_UART_STM32_H_ */ 115
