1 /* 2 * Copyright (c) 2024 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Domain clocks */ 12 13 /* RM0477 */ 14 15 /** System clock */ 16 /* defined in stm32_common_clocks.h */ 17 18 /** Fixed clocks */ 19 /* Low speed clocks defined in stm32_common_clocks.h */ 20 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) 21 #define STM32_SRC_HSI48 (STM32_SRC_HSE + 1) 22 #define STM32_SRC_HSI_KER (STM32_SRC_HSI48 + 1) /* HSI + HSIKERON */ 23 #define STM32_SRC_CSI_KER (STM32_SRC_HSI_KER + 1) /* CSI + CSIKERON */ 24 /** PLL outputs */ 25 #define STM32_SRC_PLL1_P (STM32_SRC_CSI_KER + 1) 26 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) 27 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) 28 #define STM32_SRC_PLL1_S (STM32_SRC_PLL1_R + 1) 29 #define STM32_SRC_PLL2_P (STM32_SRC_PLL1_S + 1) 30 #define STM32_SRC_PLL2_Q (STM32_SRC_PLL2_P + 1) 31 #define STM32_SRC_PLL2_R (STM32_SRC_PLL2_Q + 1) 32 #define STM32_SRC_PLL2_S (STM32_SRC_PLL2_R + 1) 33 #define STM32_SRC_PLL2_T (STM32_SRC_PLL2_S + 1) 34 #define STM32_SRC_PLL3_P (STM32_SRC_PLL2_T + 1) 35 #define STM32_SRC_PLL3_Q (STM32_SRC_PLL3_P + 1) 36 #define STM32_SRC_PLL3_R (STM32_SRC_PLL3_Q + 1) 37 #define STM32_SRC_PLL3_S (STM32_SRC_PLL3_R + 1) 38 39 /** Clock muxes */ 40 #define STM32_SRC_CKPER (STM32_SRC_PLL3_S + 1) 41 /** Others: Not yet supported */ 42 43 /** Bus clocks */ 44 #define STM32_CLOCK_BUS_AHB1 0x138 45 #define STM32_CLOCK_BUS_AHB2 0x13C 46 #define STM32_CLOCK_BUS_AHB3 0x158 47 #define STM32_CLOCK_BUS_AHB4 0x140 48 #define STM32_CLOCK_BUS_AHB5 0x134 49 #define STM32_CLOCK_BUS_APB1 0x148 50 #define STM32_CLOCK_BUS_APB1_2 0x14C 51 #define STM32_CLOCK_BUS_APB2 0x150 52 #define STM32_CLOCK_BUS_APB4 0x154 53 #define STM32_CLOCK_BUS_APB5 0x144 54 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB5 55 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_AHB3 56 57 #define STM32_CLOCK_REG_MASK 0xFFU 58 #define STM32_CLOCK_REG_SHIFT 0U 59 #define STM32_CLOCK_SHIFT_MASK 0x1FU 60 #define STM32_CLOCK_SHIFT_SHIFT 8U 61 #define STM32_CLOCK_MASK_MASK 0x7U 62 #define STM32_CLOCK_MASK_SHIFT 13U 63 #define STM32_CLOCK_VAL_MASK 0x7U 64 #define STM32_CLOCK_VAL_SHIFT 16U 65 66 /** 67 * @brief STM32H7RS clock configuration bit field. 68 * 69 * - reg (0/1) [ 0 : 7 ] 70 * - shift (0..31) [ 8 : 12 ] 71 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 72 * - val (0..3) [ 16 : 18 ] 73 * 74 * @param reg RCC_DxCCIP register offset 75 * @param shift Position within RCC_DxCCIP. 76 * @param mask Mask for the RCC_DxCCIP field. 77 * @param val Clock value (0, 1, 2 or 3). 78 */ 79 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 80 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 81 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 82 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 83 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 84 85 /** @brief RCC_DxCCIP register offset (RM0477.pdf) */ 86 #define D1CCIPR_REG 0x4C 87 #define D2CCIPR_REG 0x50 88 #define D3CCIPR_REG 0x54 89 #define D4CCIPR_REG 0x58 90 91 /** @brief RCC_BDCR register offset */ 92 #define BDCR_REG 0x70 93 94 /** @brief RCC_CFGRx register offset */ 95 #define CFGR_REG 0x10 96 97 /** @brief Device domain clocks selection helpers (RM0477.pdf) */ 98 99 /* TODO to be completed */ 100 101 /** D1CCIPR devices */ 102 #define FMC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG) 103 #define SDMMC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG) 104 #define XSPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG) 105 #define XSPI2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG) 106 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG) 107 #define CKPER_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG) 108 109 /** D2CCIPR devices */ 110 #define USART234578_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG) 111 #define SPI23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG) 112 #define I2C23_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIPR_REG) 113 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG) 114 #define I3C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG) 115 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIPR_REG) 116 #define FDCAN_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIPR_REG) 117 118 /** D3CCIPR devices */ 119 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG) 120 #define SPI45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D3CCIPR_REG) 121 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, D3CCIPR_REG) 122 #define SAI1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 16, D3CCIPR_REG) 123 #define SAI2_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 20, D3CCIPR_REG) 124 125 /** D4CCIPR devices */ 126 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 0, D4CCIPR_REG) 127 #define SPI6_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 4, D4CCIPR_REG) 128 #define LPTIM23_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 8, D4CCIPR_REG) 129 #define LPTIM45_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, D4CCIPR_REG) 130 131 /** BDCR devices */ 132 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG) 133 134 /** CFGR devices */ 135 #define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x7, 22, CFGR_REG) 136 #define MCO1_PRE(val) STM32_MCO_CFGR(val, 0xF, 18, CFGR_REG) 137 #define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG) 138 #define MCO2_PRE(val) STM32_MCO_CFGR(val, 0xF, 25, CFGR_REG) 139 140 /* MCO prescaler : division factor */ 141 #define MCO_PRE_DIV_1 1 142 #define MCO_PRE_DIV_2 2 143 #define MCO_PRE_DIV_3 3 144 #define MCO_PRE_DIV_4 4 145 #define MCO_PRE_DIV_5 5 146 #define MCO_PRE_DIV_6 6 147 #define MCO_PRE_DIV_7 7 148 #define MCO_PRE_DIV_8 8 149 #define MCO_PRE_DIV_9 9 150 #define MCO_PRE_DIV_10 10 151 #define MCO_PRE_DIV_11 11 152 #define MCO_PRE_DIV_12 12 153 #define MCO_PRE_DIV_13 13 154 #define MCO_PRE_DIV_14 14 155 #define MCO_PRE_DIV_15 15 156 157 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32H7RS_CLOCK_H_ */ 158
