1 /* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Peripheral clock sources */ 12 13 /* RM0493, Figure 30, clock tree */ 14 15 /** System clock */ 16 /* defined in stm32_common_clocks.h */ 17 /** Fixed clocks */ 18 /* Low speed clocks defined in stm32_common_clocks.h */ 19 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) 20 #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1) 21 /** Bus clock */ 22 #define STM32_SRC_HCLK1 (STM32_SRC_HSI16 + 1) 23 #define STM32_SRC_HCLK5 (STM32_SRC_HCLK1 + 1) 24 #define STM32_SRC_PCLK1 (STM32_SRC_HCLK5 + 1) 25 #define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1) 26 #define STM32_SRC_PCLK7 (STM32_SRC_PCLK2 + 1) 27 /** PLL outputs */ 28 #define STM32_SRC_PLL1_P (STM32_SRC_PCLK7 + 1) 29 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) 30 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) 31 32 #define STM32_SRC_CLOCK_MIN STM32_SRC_PLL1_P 33 #define STM32_SRC_CLOCK_MAX STM32_SRC_SYSCLK 34 35 /** Bus clocks (Register address offsets) */ 36 #define STM32_CLOCK_BUS_AHB1 0x088 37 #define STM32_CLOCK_BUS_AHB2 0x08C 38 #define STM32_CLOCK_BUS_AHB4 0x094 39 #define STM32_CLOCK_BUS_AHB5 0x098 40 #define STM32_CLOCK_BUS_APB1 0x09C 41 #define STM32_CLOCK_BUS_APB1_2 0x0A0 42 #define STM32_CLOCK_BUS_APB2 0x0A4 43 #define STM32_CLOCK_BUS_APB7 0x0A8 44 45 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 46 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB7 47 48 /** 49 * @brief STM32WBA clock configuration bit field. 50 * 51 * - reg (1/2/3) [ 0 : 7 ] 52 * - shift (0..31) [ 8 : 12 ] 53 * - mask (0x1, 0x3, 0x7) [ 13 : 15 ] 54 * - val (0..7) [ 16 : 18 ] 55 * 56 * @param reg RCC_CCIPRx register offset 57 * @param shift Position within RCC_CCIPRx. 58 * @param mask Mask for the RCC_CCIPRx field. 59 * @param val Clock value (0, 1, ... 7). 60 */ 61 62 #define STM32_CLOCK_REG_MASK 0xFFU 63 #define STM32_CLOCK_REG_SHIFT 0U 64 #define STM32_CLOCK_SHIFT_MASK 0x1FU 65 #define STM32_CLOCK_SHIFT_SHIFT 8U 66 #define STM32_CLOCK_MASK_MASK 0x7U 67 #define STM32_CLOCK_MASK_SHIFT 13U 68 #define STM32_CLOCK_VAL_MASK 0x7U 69 #define STM32_CLOCK_VAL_SHIFT 16U 70 71 #define STM32_DOMAIN_CLOCK(val, mask, shift, reg) \ 72 ((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) | \ 73 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) | \ 74 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) | \ 75 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT)) 76 77 /** @brief RCC_CCIPRx register offset (RM0493.pdf) */ 78 #define CCIPR1_REG 0xE0 79 #define CCIPR2_REG 0xE4 80 #define CCIPR3_REG 0xE8 81 /** @brief RCC_BCDR1 register offset (RM0493.pdf) */ 82 #define BCDR1_REG 0xF0 83 84 /** @brief Device clk sources selection helpers */ 85 /** CCIPR1 devices */ 86 #define USART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG) 87 #define USART2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG) 88 #define I2C1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG) 89 #define LPTIM2_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG) 90 #define SPI1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG) 91 #define SYSTICK_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG) 92 #define TIMIC_SEL(val) STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG) 93 /** CCIPR2 devices */ 94 #define RNG_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG) 95 /** CCIPR3 devices */ 96 #define LPUART1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR3_REG) 97 #define SPI3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG) 98 #define I2C3_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG) 99 #define LPTIM1_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG) 100 #define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG) 101 /** BCDR1 devices */ 102 #define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BCDR1_REG) 103 104 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */ 105
