1 /* 2 * Copyright (c) 2016 Open-RnD Sp. z o.o. 3 * Copyright (c) 2016 BayLibre, SAS 4 * Copyright (c) 2017-2022 Linaro Limited. 5 * Copyright (c) 2017 RnDity Sp. z o.o. 6 * 7 * SPDX-License-Identifier: Apache-2.0 8 */ 9 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 10 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 11 12 #include <zephyr/drivers/clock_control.h> 13 14 #if defined(CONFIG_SOC_SERIES_STM32C0X) 15 #include <zephyr/dt-bindings/clock/stm32c0_clock.h> 16 #elif defined(CONFIG_SOC_SERIES_STM32F0X) 17 #include <zephyr/dt-bindings/clock/stm32f0_clock.h> 18 #elif defined(CONFIG_SOC_SERIES_STM32F1X) 19 #include <zephyr/dt-bindings/clock/stm32f1_clock.h> 20 #elif defined(CONFIG_SOC_SERIES_STM32F3X) 21 #include <zephyr/dt-bindings/clock/stm32f3_clock.h> 22 #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ 23 defined(CONFIG_SOC_SERIES_STM32F4X) 24 #include <zephyr/dt-bindings/clock/stm32f4_clock.h> 25 #elif defined(CONFIG_SOC_SERIES_STM32F7X) 26 #include <zephyr/dt-bindings/clock/stm32f7_clock.h> 27 #elif defined(CONFIG_SOC_SERIES_STM32G0X) 28 #include <zephyr/dt-bindings/clock/stm32g0_clock.h> 29 #elif defined(CONFIG_SOC_SERIES_STM32G4X) 30 #include <zephyr/dt-bindings/clock/stm32g4_clock.h> 31 #elif defined(CONFIG_SOC_SERIES_STM32L0X) 32 #include <zephyr/dt-bindings/clock/stm32l0_clock.h> 33 #elif defined(CONFIG_SOC_SERIES_STM32L1X) 34 #include <zephyr/dt-bindings/clock/stm32l1_clock.h> 35 #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \ 36 defined(CONFIG_SOC_SERIES_STM32L5X) 37 #include <zephyr/dt-bindings/clock/stm32l4_clock.h> 38 #elif defined(CONFIG_SOC_SERIES_STM32WBX) 39 #include <zephyr/dt-bindings/clock/stm32wb_clock.h> 40 #elif defined(CONFIG_SOC_SERIES_STM32WLX) 41 #include <zephyr/dt-bindings/clock/stm32wl_clock.h> 42 #elif defined(CONFIG_SOC_SERIES_STM32H5X) 43 #include <zephyr/dt-bindings/clock/stm32h5_clock.h> 44 #elif defined(CONFIG_SOC_SERIES_STM32H7X) 45 #include <zephyr/dt-bindings/clock/stm32h7_clock.h> 46 #elif defined(CONFIG_SOC_SERIES_STM32U5X) 47 #include <zephyr/dt-bindings/clock/stm32u5_clock.h> 48 #else 49 #include <zephyr/dt-bindings/clock/stm32_clock.h> 50 #endif 51 52 /** Common clock control device node for all STM32 chips */ 53 #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc) 54 55 /** RCC node related symbols */ 56 57 #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler) 58 #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler) 59 #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler) 60 #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler) 61 #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 62 #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 63 #define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 64 #define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler) 65 66 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler) 67 #define STM32_CORE_PRESCALER STM32_AHB_PRESCALER 68 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 69 #define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER 70 #endif 71 72 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 73 #define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER 74 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 75 #define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER 76 #else 77 #define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER 78 #endif 79 80 #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre) 81 #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre) 82 #define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1) 83 #define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2) 84 #define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre) 85 #define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre) 86 87 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc)) 88 89 /* To enable use of IS_ENABLED utility macro, these symbols 90 * should not be defined directly using DT_SAME_NODE. 91 */ 92 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll)) 93 #define STM32_SYSCLK_SRC_PLL 1 94 #endif 95 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 96 #define STM32_SYSCLK_SRC_HSI 1 97 #endif 98 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 99 #define STM32_SYSCLK_SRC_HSE 1 100 #endif 101 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 102 #define STM32_SYSCLK_SRC_MSI 1 103 #endif 104 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 105 #define STM32_SYSCLK_SRC_MSIS 1 106 #endif 107 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 108 #define STM32_SYSCLK_SRC_CSI 1 109 #endif 110 111 112 /** PLL node related symbols */ 113 114 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \ 115 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \ 116 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \ 117 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ 118 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ 119 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ 120 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ 121 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \ 122 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) 123 #define STM32_PLL_ENABLED 1 124 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) 125 #define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n) 126 #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p) 127 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1) 128 #define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q) 129 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1) 130 #define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r) 131 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1) 132 #endif 133 134 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay) 135 #define STM32_PLLI2S_ENABLED 1 136 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR 137 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 138 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 139 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 140 #endif 141 142 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f412_plli2s_clock, okay) 143 #define STM32_PLLI2S_ENABLED 1 144 #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m) 145 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 146 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 147 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 148 #endif 149 150 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \ 151 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) 152 #define STM32_PLL2_ENABLED 1 153 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) 154 #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n) 155 #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p) 156 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1) 157 #define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q) 158 #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1) 159 #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r) 160 #define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1) 161 #endif 162 163 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \ 164 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) 165 #define STM32_PLL3_ENABLED 1 166 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) 167 #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n) 168 #define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p) 169 #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1) 170 #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q) 171 #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1) 172 #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r) 173 #define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1) 174 #endif 175 176 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay) 177 #define STM32_PLL_ENABLED 1 178 #define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre) 179 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 180 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre) 181 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \ 182 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \ 183 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay) 184 #define STM32_PLL_ENABLED 1 185 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 186 #define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv) 187 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre) 188 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) 189 #define STM32_PLL_ENABLED 1 190 #define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div) 191 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 192 #endif 193 194 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay) 195 #define STM32_PLL2_ENABLED 1 196 #define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul) 197 #define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv) 198 #endif 199 200 /** PLL/PLL1 clock source */ 201 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) && \ 202 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) 203 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) 204 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 205 #define STM32_PLL_SRC_MSI 1 206 #endif 207 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 208 #define STM32_PLL_SRC_MSIS 1 209 #endif 210 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 211 #define STM32_PLL_SRC_HSI 1 212 #endif 213 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 214 #define STM32_PLL_SRC_CSI 1 215 #endif 216 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 217 #define STM32_PLL_SRC_HSE 1 218 #endif 219 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2)) 220 #define STM32_PLL_SRC_PLL2 1 221 #endif 222 223 #endif 224 225 /** PLL2 clock source */ 226 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) && \ 227 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks) 228 #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2)) 229 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 230 #define STM32_PLL2_SRC_MSIS 1 231 #endif 232 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 233 #define STM32_PLL2_SRC_HSI 1 234 #endif 235 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 236 #define STM32_PLL2_SRC_HSE 1 237 #endif 238 239 #endif 240 241 /** PLL3 clock source */ 242 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll3), okay) && \ 243 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks) 244 #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3)) 245 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 246 #define STM32_PLL3_SRC_MSIS 1 247 #endif 248 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 249 #define STM32_PLL3_SRC_HSI 1 250 #endif 251 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 252 #define STM32_PLL3_SRC_HSE 1 253 #endif 254 255 #endif 256 257 258 /** Fixed clocks related symbols */ 259 260 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay) 261 #define STM32_LSE_ENABLED 1 262 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 263 #define STM32_LSE_DRIVING 0 264 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 265 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay) 266 #define STM32_LSE_ENABLED 1 267 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 268 #define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability) 269 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 270 #else 271 #define STM32_LSE_ENABLED 0 272 #define STM32_LSE_FREQ 0 273 #define STM32_LSE_DRIVING 0 274 #define STM32_LSE_BYPASS 0 275 #endif 276 277 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \ 278 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay) 279 #define STM32_MSI_ENABLED 1 280 #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range) 281 #endif 282 283 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) 284 #define STM32_MSI_ENABLED 1 285 #define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode) 286 #endif 287 288 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) 289 #define STM32_MSIS_ENABLED 1 290 #define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range) 291 #define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode) 292 #else 293 #define STM32_MSIS_ENABLED 0 294 #define STM32_MSIS_RANGE 0 295 #define STM32_MSIS_PLL_MODE 0 296 #endif 297 298 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) 299 #define STM32_MSIK_ENABLED 1 300 #define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range) 301 #define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode) 302 #else 303 #define STM32_MSIK_ENABLED 0 304 #define STM32_MSIK_RANGE 0 305 #define STM32_MSIK_PLL_MODE 0 306 #endif 307 308 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay) 309 #define STM32_CSI_ENABLED 1 310 #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency) 311 #else 312 #define STM32_CSI_FREQ 0 313 #endif 314 315 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay) 316 #define STM32_LSI_ENABLED 1 317 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency) 318 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay) 319 #define STM32_LSI_ENABLED 1 320 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency) 321 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay) 322 #define STM32_LSI_ENABLED 1 323 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency) 324 #else 325 #define STM32_LSI_FREQ 0 326 #endif 327 328 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay) 329 #define STM32_HSI_DIV_ENABLED 0 330 #define STM32_HSI_ENABLED 1 331 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 332 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \ 333 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \ 334 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) 335 #define STM32_HSI_DIV_ENABLED 1 336 #define STM32_HSI_ENABLED 1 337 #define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div) 338 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 339 #else 340 #define STM32_HSI_DIV_ENABLED 0 341 #define STM32_HSI_DIVISOR 1 342 #define STM32_HSI_FREQ 0 343 #endif 344 345 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay) 346 #define STM32_HSE_ENABLED 1 347 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 348 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay) 349 #define STM32_HSE_ENABLED 1 350 #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass) 351 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 352 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay) 353 #define STM32_HSE_ENABLED 1 354 #define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo) 355 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 356 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 357 #else 358 #define STM32_HSE_FREQ 0 359 #endif 360 361 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay) 362 #define STM32_HSI48_ENABLED 1 363 #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency) 364 #endif 365 366 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay) 367 #define STM32_CKPER_ENABLED 1 368 #endif 369 370 /** Driver structure definition */ 371 372 struct stm32_pclken { 373 uint32_t bus; 374 uint32_t enr; 375 }; 376 377 /** Device tree clocks helpers */ 378 379 #define STM32_CLOCK_INFO(clk_index, node_id) \ 380 { \ 381 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \ 382 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) \ 383 } 384 #define STM32_DT_CLOCKS(node_id) \ 385 { \ 386 LISTIFY(DT_NUM_CLOCKS(node_id), \ 387 STM32_CLOCK_INFO, (,), node_id) \ 388 } 389 390 #define STM32_DT_INST_CLOCKS(inst) \ 391 STM32_DT_CLOCKS(DT_DRV_INST(inst)) 392 393 #define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || 394 #define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \ 395 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0) 396 397 #define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || 398 #define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \ 399 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0) 400 401 /** Clock source binding accessors */ 402 403 /** 404 * @brief Obtain register field from clock configuration. 405 * 406 * @param clock clock bit field value. 407 */ 408 #define STM32_CLOCK_REG_GET(clock) \ 409 (((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK) 410 411 /** 412 * @brief Obtain position field from clock configuration. 413 * 414 * @param clock Clock bit field value. 415 */ 416 #define STM32_CLOCK_SHIFT_GET(clock) \ 417 (((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK) 418 419 /** 420 * @brief Obtain mask field from clock configuration. 421 * 422 * @param clock Clock bit field value. 423 */ 424 #define STM32_CLOCK_MASK_GET(clock) \ 425 (((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK) 426 427 /** 428 * @brief Obtain value field from clock configuration. 429 * 430 * @param clock Clock bit field value. 431 */ 432 #define STM32_CLOCK_VAL_GET(clock) \ 433 (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK) 434 435 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */ 436
