1 /* 2 * Copyright (c) 2016 Open-RnD Sp. z o.o. 3 * Copyright (c) 2016 BayLibre, SAS 4 * Copyright (c) 2017-2022 Linaro Limited. 5 * Copyright (c) 2017 RnDity Sp. z o.o. 6 * Copyright (c) 2023 STMicroelectronics 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 11 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 12 13 #include <zephyr/drivers/clock_control.h> 14 15 #if defined(CONFIG_SOC_SERIES_STM32C0X) 16 #include <zephyr/dt-bindings/clock/stm32c0_clock.h> 17 #elif defined(CONFIG_SOC_SERIES_STM32F0X) 18 #include <zephyr/dt-bindings/clock/stm32f0_clock.h> 19 #elif defined(CONFIG_SOC_SERIES_STM32F1X) 20 #include <zephyr/dt-bindings/clock/stm32f1_clock.h> 21 #elif defined(CONFIG_SOC_SERIES_STM32F3X) 22 #include <zephyr/dt-bindings/clock/stm32f3_clock.h> 23 #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ 24 defined(CONFIG_SOC_SERIES_STM32F4X) 25 #include <zephyr/dt-bindings/clock/stm32f4_clock.h> 26 #elif defined(CONFIG_SOC_SERIES_STM32F7X) 27 #include <zephyr/dt-bindings/clock/stm32f7_clock.h> 28 #elif defined(CONFIG_SOC_SERIES_STM32G0X) 29 #include <zephyr/dt-bindings/clock/stm32g0_clock.h> 30 #elif defined(CONFIG_SOC_SERIES_STM32G4X) 31 #include <zephyr/dt-bindings/clock/stm32g4_clock.h> 32 #elif defined(CONFIG_SOC_SERIES_STM32L0X) 33 #include <zephyr/dt-bindings/clock/stm32l0_clock.h> 34 #elif defined(CONFIG_SOC_SERIES_STM32L1X) 35 #include <zephyr/dt-bindings/clock/stm32l1_clock.h> 36 #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \ 37 defined(CONFIG_SOC_SERIES_STM32L5X) 38 #include <zephyr/dt-bindings/clock/stm32l4_clock.h> 39 #elif defined(CONFIG_SOC_SERIES_STM32WBX) 40 #include <zephyr/dt-bindings/clock/stm32wb_clock.h> 41 #elif defined(CONFIG_SOC_SERIES_STM32WLX) 42 #include <zephyr/dt-bindings/clock/stm32wl_clock.h> 43 #elif defined(CONFIG_SOC_SERIES_STM32H5X) 44 #include <zephyr/dt-bindings/clock/stm32h5_clock.h> 45 #elif defined(CONFIG_SOC_SERIES_STM32H7X) 46 #include <zephyr/dt-bindings/clock/stm32h7_clock.h> 47 #elif defined(CONFIG_SOC_SERIES_STM32U5X) 48 #include <zephyr/dt-bindings/clock/stm32u5_clock.h> 49 #elif defined(CONFIG_SOC_SERIES_STM32WBAX) 50 #include <zephyr/dt-bindings/clock/stm32wba_clock.h> 51 #else 52 #include <zephyr/dt-bindings/clock/stm32_clock.h> 53 #endif 54 55 /** Common clock control device node for all STM32 chips */ 56 #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc) 57 58 /** RCC node related symbols */ 59 60 #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler) 61 #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler) 62 #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler) 63 #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler) 64 #define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler) 65 #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 66 #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 67 #define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1) 68 #define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 69 #define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler) 70 71 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler) 72 #define STM32_CORE_PRESCALER STM32_AHB_PRESCALER 73 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 74 #define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER 75 #endif 76 77 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 78 #define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER 79 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 80 #define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER 81 #else 82 #define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER 83 #endif 84 85 #define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler) 86 #define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler) 87 #define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler) 88 89 /** STM2H7 specifics RCC dividers */ 90 #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre) 91 #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre) 92 #define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1) 93 #define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2) 94 #define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre) 95 #define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre) 96 97 /** STM2WBA specifics RCC dividers */ 98 #define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div) 99 100 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc)) 101 102 /* To enable use of IS_ENABLED utility macro, these symbols 103 * should not be defined directly using DT_SAME_NODE. 104 */ 105 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll)) 106 #define STM32_SYSCLK_SRC_PLL 1 107 #endif 108 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 109 #define STM32_SYSCLK_SRC_HSI 1 110 #endif 111 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 112 #define STM32_SYSCLK_SRC_HSE 1 113 #endif 114 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 115 #define STM32_SYSCLK_SRC_MSI 1 116 #endif 117 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 118 #define STM32_SYSCLK_SRC_MSIS 1 119 #endif 120 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 121 #define STM32_SYSCLK_SRC_CSI 1 122 #endif 123 124 125 /** PLL node related symbols */ 126 127 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \ 128 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \ 129 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \ 130 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ 131 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ 132 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ 133 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ 134 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \ 135 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \ 136 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) 137 #define STM32_PLL_ENABLED 1 138 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) 139 #define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n) 140 #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p) 141 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1) 142 #define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q) 143 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1) 144 #define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r) 145 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1) 146 #define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn) 147 #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1) 148 #endif 149 150 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay) 151 #define STM32_PLLI2S_ENABLED 1 152 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR 153 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 154 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 155 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 156 #endif 157 158 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f412_plli2s_clock, okay) 159 #define STM32_PLLI2S_ENABLED 1 160 #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m) 161 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 162 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 163 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 164 #endif 165 166 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \ 167 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) 168 #define STM32_PLL2_ENABLED 1 169 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) 170 #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n) 171 #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p) 172 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1) 173 #define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q) 174 #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1) 175 #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r) 176 #define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1) 177 #define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn) 178 #define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1) 179 #endif 180 181 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \ 182 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) 183 #define STM32_PLL3_ENABLED 1 184 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) 185 #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n) 186 #define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p) 187 #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1) 188 #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q) 189 #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1) 190 #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r) 191 #define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1) 192 #define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn) 193 #define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1) 194 #endif 195 196 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay) 197 #define STM32_PLL_ENABLED 1 198 #define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre) 199 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 200 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre) 201 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \ 202 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \ 203 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay) 204 #define STM32_PLL_ENABLED 1 205 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 206 #define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv) 207 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre) 208 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) 209 #define STM32_PLL_ENABLED 1 210 #define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div) 211 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 212 #endif 213 214 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay) 215 #define STM32_PLL2_ENABLED 1 216 #define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul) 217 #define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv) 218 #endif 219 220 /** PLL/PLL1 clock source */ 221 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) && \ 222 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) 223 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) 224 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 225 #define STM32_PLL_SRC_MSI 1 226 #endif 227 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 228 #define STM32_PLL_SRC_MSIS 1 229 #endif 230 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 231 #define STM32_PLL_SRC_HSI 1 232 #endif 233 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 234 #define STM32_PLL_SRC_CSI 1 235 #endif 236 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 237 #define STM32_PLL_SRC_HSE 1 238 #endif 239 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2)) 240 #define STM32_PLL_SRC_PLL2 1 241 #endif 242 243 #endif 244 245 /** PLL2 clock source */ 246 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) && \ 247 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks) 248 #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2)) 249 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 250 #define STM32_PLL2_SRC_MSIS 1 251 #endif 252 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 253 #define STM32_PLL2_SRC_HSI 1 254 #endif 255 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 256 #define STM32_PLL2_SRC_HSE 1 257 #endif 258 259 #endif 260 261 /** PLL3 clock source */ 262 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll3), okay) && \ 263 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks) 264 #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3)) 265 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 266 #define STM32_PLL3_SRC_MSIS 1 267 #endif 268 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 269 #define STM32_PLL3_SRC_HSI 1 270 #endif 271 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 272 #define STM32_PLL3_SRC_HSE 1 273 #endif 274 275 #endif 276 277 278 /** Fixed clocks related symbols */ 279 280 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay) 281 #define STM32_LSE_ENABLED 1 282 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 283 #define STM32_LSE_DRIVING 0 284 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 285 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay) 286 #define STM32_LSE_ENABLED 1 287 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 288 #define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability) 289 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 290 #else 291 #define STM32_LSE_ENABLED 0 292 #define STM32_LSE_FREQ 0 293 #define STM32_LSE_DRIVING 0 294 #define STM32_LSE_BYPASS 0 295 #endif 296 297 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \ 298 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay) 299 #define STM32_MSI_ENABLED 1 300 #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range) 301 #endif 302 303 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) 304 #define STM32_MSI_ENABLED 1 305 #define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode) 306 #endif 307 308 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) 309 #define STM32_MSIS_ENABLED 1 310 #define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range) 311 #define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode) 312 #else 313 #define STM32_MSIS_ENABLED 0 314 #define STM32_MSIS_RANGE 0 315 #define STM32_MSIS_PLL_MODE 0 316 #endif 317 318 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) 319 #define STM32_MSIK_ENABLED 1 320 #define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range) 321 #define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode) 322 #else 323 #define STM32_MSIK_ENABLED 0 324 #define STM32_MSIK_RANGE 0 325 #define STM32_MSIK_PLL_MODE 0 326 #endif 327 328 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay) 329 #define STM32_CSI_ENABLED 1 330 #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency) 331 #else 332 #define STM32_CSI_FREQ 0 333 #endif 334 335 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay) 336 #define STM32_LSI_ENABLED 1 337 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency) 338 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay) 339 #define STM32_LSI_ENABLED 1 340 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency) 341 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay) 342 #define STM32_LSI_ENABLED 1 343 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency) 344 #else 345 #define STM32_LSI_FREQ 0 346 #endif 347 348 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay) 349 #define STM32_HSI_DIV_ENABLED 0 350 #define STM32_HSI_ENABLED 1 351 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 352 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \ 353 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \ 354 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) 355 #define STM32_HSI_DIV_ENABLED 1 356 #define STM32_HSI_ENABLED 1 357 #define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div) 358 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 359 #else 360 #define STM32_HSI_DIV_ENABLED 0 361 #define STM32_HSI_DIVISOR 1 362 #define STM32_HSI_FREQ 0 363 #endif 364 365 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay) 366 #define STM32_HSE_ENABLED 1 367 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 368 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay) 369 #define STM32_HSE_ENABLED 1 370 #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass) 371 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 372 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay) 373 #define STM32_HSE_ENABLED 1 374 #define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo) 375 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 376 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 377 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay) 378 #define STM32_HSE_ENABLED 1 379 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 380 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 381 #else 382 #define STM32_HSE_FREQ 0 383 #endif 384 385 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay) 386 #define STM32_HSI48_ENABLED 1 387 #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency) 388 #endif 389 390 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay) 391 #define STM32_CKPER_ENABLED 1 392 #endif 393 394 /** Driver structure definition */ 395 396 struct stm32_pclken { 397 uint32_t bus; 398 uint32_t enr; 399 }; 400 401 /** Device tree clocks helpers */ 402 403 #define STM32_CLOCK_INFO(clk_index, node_id) \ 404 { \ 405 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \ 406 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) \ 407 } 408 #define STM32_DT_CLOCKS(node_id) \ 409 { \ 410 LISTIFY(DT_NUM_CLOCKS(node_id), \ 411 STM32_CLOCK_INFO, (,), node_id) \ 412 } 413 414 #define STM32_DT_INST_CLOCKS(inst) \ 415 STM32_DT_CLOCKS(DT_DRV_INST(inst)) 416 417 #define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || 418 #define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \ 419 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0) 420 421 #define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || 422 #define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \ 423 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0) 424 425 /** Clock source binding accessors */ 426 427 /** 428 * @brief Obtain register field from clock configuration. 429 * 430 * @param clock clock bit field value. 431 */ 432 #define STM32_CLOCK_REG_GET(clock) \ 433 (((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK) 434 435 /** 436 * @brief Obtain position field from clock configuration. 437 * 438 * @param clock Clock bit field value. 439 */ 440 #define STM32_CLOCK_SHIFT_GET(clock) \ 441 (((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK) 442 443 /** 444 * @brief Obtain mask field from clock configuration. 445 * 446 * @param clock Clock bit field value. 447 */ 448 #define STM32_CLOCK_MASK_GET(clock) \ 449 (((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK) 450 451 /** 452 * @brief Obtain value field from clock configuration. 453 * 454 * @param clock Clock bit field value. 455 */ 456 #define STM32_CLOCK_VAL_GET(clock) \ 457 (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK) 458 459 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */ 460
