1 /* 2 * Copyright (c) 2023 STMicroelectronics 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ 7 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ 8 9 #include "stm32_common_clocks.h" 10 11 /** Peripheral clock sources */ 12 13 /* RM0493, Figure 30, clock tree */ 14 15 /** System clock */ 16 /* defined in stm32_common_clocks.h */ 17 /** Fixed clocks */ 18 /* Low speed clocks defined in stm32_common_clocks.h */ 19 #define STM32_SRC_HSE (STM32_SRC_LSI + 1) 20 #define STM32_SRC_HSI16 (STM32_SRC_HSE + 1) 21 /** Bus clock */ 22 #define STM32_SRC_HCLK1 (STM32_SRC_HSI16 + 1) 23 #define STM32_SRC_HCLK5 (STM32_SRC_HCLK1 + 1) 24 #define STM32_SRC_PCLK1 (STM32_SRC_HCLK5 + 1) 25 #define STM32_SRC_PCLK2 (STM32_SRC_PCLK1 + 1) 26 #define STM32_SRC_PCLK7 (STM32_SRC_PCLK2 + 1) 27 /** PLL outputs */ 28 #define STM32_SRC_PLL1_P (STM32_SRC_PCLK7 + 1) 29 #define STM32_SRC_PLL1_Q (STM32_SRC_PLL1_P + 1) 30 #define STM32_SRC_PLL1_R (STM32_SRC_PLL1_Q + 1) 31 32 #define STM32_SRC_CLOCK_MIN STM32_SRC_PLL1_P 33 #define STM32_SRC_CLOCK_MAX STM32_SRC_SYSCLK 34 35 /** Bus clocks (Register address offsets) */ 36 #define STM32_CLOCK_BUS_AHB1 0x088 37 #define STM32_CLOCK_BUS_AHB2 0x08C 38 #define STM32_CLOCK_BUS_AHB4 0x094 39 #define STM32_CLOCK_BUS_AHB5 0x098 40 #define STM32_CLOCK_BUS_APB1 0x09C 41 #define STM32_CLOCK_BUS_APB1_2 0x0A0 42 #define STM32_CLOCK_BUS_APB2 0x0A4 43 #define STM32_CLOCK_BUS_APB7 0x0A8 44 45 #define STM32_PERIPH_BUS_MIN STM32_CLOCK_BUS_AHB1 46 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB7 47 48 /** @brief RCC_CCIPRx register offset (RM0493.pdf) */ 49 #define CCIPR1_REG 0xE0 50 #define CCIPR2_REG 0xE4 51 #define CCIPR3_REG 0xE8 52 /** @brief RCC_BCDR1 register offset (RM0493.pdf) */ 53 #define BCDR1_REG 0xF0 54 55 /** @brief Device clk sources selection helpers */ 56 /** CCIPR1 devices */ 57 #define USART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG) 58 #define USART2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG) 59 #define I2C1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG) 60 #define LPTIM2_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG) 61 #define SPI1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG) 62 #define SYSTICK_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG) 63 #define TIMIC_SEL(val) STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG) 64 /** CCIPR2 devices */ 65 #define RNG_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG) 66 /** CCIPR3 devices */ 67 #define LPUART1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG) 68 #define SPI3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG) 69 #define I2C3_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG) 70 #define LPTIM1_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG) 71 #define ADC_SEL(val) STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG) 72 /** BCDR1 devices */ 73 #define RTC_SEL(val) STM32_DT_CLOCK_SELECT((val), 3, 8, BCDR1_REG) 74 /** @brief RCC_CFGRx register offset */ 75 #define CFGR1_REG 0x1C 76 /** CFGR1 devices */ 77 #define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG) 78 #define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG) 79 80 /* MCO prescaler : division factor */ 81 #define MCO_PRE_DIV_1 0 82 #define MCO_PRE_DIV_2 1 83 #define MCO_PRE_DIV_4 2 84 #define MCO_PRE_DIV_8 3 85 #define MCO_PRE_DIV_16 4 86 87 /* MCO clock output */ 88 #define MCO_SEL_SYSCLKPRE 1 89 #define MCO_SEL_HSI16 3 90 #define MCO_SEL_HSE32 4 91 #define MCO_SEL_PLL1RCLK 5 92 #define MCO_SEL_LSI 6 93 #define MCO_SEL_LSE 7 94 #define MCO_SEL_PLL1PCLK 8 95 #define MCO_SEL_PLL1QCLK 9 96 #define MCO_SEL_HCLK5 10 97 98 99 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */ 100
