1 /* 2 * Copyright (c) 2016 Open-RnD Sp. z o.o. 3 * Copyright (c) 2016 BayLibre, SAS 4 * Copyright (c) 2017-2022 Linaro Limited. 5 * Copyright (c) 2017 RnDity Sp. z o.o. 6 * Copyright (c) 2023 STMicroelectronics 7 * 8 * SPDX-License-Identifier: Apache-2.0 9 */ 10 #ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 11 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ 12 13 #include <zephyr/drivers/clock_control.h> 14 15 #if defined(CONFIG_SOC_SERIES_STM32C0X) 16 #include <zephyr/dt-bindings/clock/stm32c0_clock.h> 17 #elif defined(CONFIG_SOC_SERIES_STM32F0X) 18 #include <zephyr/dt-bindings/clock/stm32f0_clock.h> 19 #elif defined(CONFIG_SOC_SERIES_STM32F1X) 20 #include <zephyr/dt-bindings/clock/stm32f1_clock.h> 21 #elif defined(CONFIG_SOC_SERIES_STM32F3X) 22 #include <zephyr/dt-bindings/clock/stm32f3_clock.h> 23 #elif defined(CONFIG_SOC_SERIES_STM32F2X) || \ 24 defined(CONFIG_SOC_SERIES_STM32F4X) 25 #include <zephyr/dt-bindings/clock/stm32f4_clock.h> 26 #elif defined(CONFIG_SOC_SERIES_STM32F7X) 27 #include <zephyr/dt-bindings/clock/stm32f7_clock.h> 28 #elif defined(CONFIG_SOC_SERIES_STM32G0X) 29 #include <zephyr/dt-bindings/clock/stm32g0_clock.h> 30 #elif defined(CONFIG_SOC_SERIES_STM32G4X) 31 #include <zephyr/dt-bindings/clock/stm32g4_clock.h> 32 #elif defined(CONFIG_SOC_SERIES_STM32L0X) 33 #include <zephyr/dt-bindings/clock/stm32l0_clock.h> 34 #elif defined(CONFIG_SOC_SERIES_STM32L1X) 35 #include <zephyr/dt-bindings/clock/stm32l1_clock.h> 36 #elif defined(CONFIG_SOC_SERIES_STM32L4X) || \ 37 defined(CONFIG_SOC_SERIES_STM32L5X) 38 #include <zephyr/dt-bindings/clock/stm32l4_clock.h> 39 #elif defined(CONFIG_SOC_SERIES_STM32WBX) 40 #include <zephyr/dt-bindings/clock/stm32wb_clock.h> 41 #elif defined(CONFIG_SOC_SERIES_STM32WLX) 42 #include <zephyr/dt-bindings/clock/stm32wl_clock.h> 43 #elif defined(CONFIG_SOC_SERIES_STM32H5X) 44 #include <zephyr/dt-bindings/clock/stm32h5_clock.h> 45 #elif defined(CONFIG_SOC_SERIES_STM32H7X) 46 #include <zephyr/dt-bindings/clock/stm32h7_clock.h> 47 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX) 48 #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h> 49 #elif defined(CONFIG_SOC_SERIES_STM32U5X) 50 #include <zephyr/dt-bindings/clock/stm32u5_clock.h> 51 #elif defined(CONFIG_SOC_SERIES_STM32WBAX) 52 #include <zephyr/dt-bindings/clock/stm32wba_clock.h> 53 #else 54 #include <zephyr/dt-bindings/clock/stm32_clock.h> 55 #endif 56 57 /** Common clock control device node for all STM32 chips */ 58 #define STM32_CLOCK_CONTROL_NODE DT_NODELABEL(rcc) 59 60 /** RCC node related symbols */ 61 62 #define STM32_AHB_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb_prescaler) 63 #define STM32_APB1_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb1_prescaler) 64 #define STM32_APB2_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb2_prescaler) 65 #define STM32_APB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb3_prescaler) 66 #define STM32_APB5_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb5_prescaler) 67 #define STM32_APB7_PRESCALER DT_PROP(DT_NODELABEL(rcc), apb7_prescaler) 68 #define STM32_AHB3_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 69 #define STM32_AHB4_PRESCALER DT_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 70 #define STM32_AHB5_PRESCALER DT_PROP_OR(DT_NODELABEL(rcc), ahb5_prescaler, 1) 71 #define STM32_CPU1_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 72 #define STM32_CPU2_PRESCALER DT_PROP(DT_NODELABEL(rcc), cpu2_prescaler) 73 74 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb_prescaler) 75 #define STM32_CORE_PRESCALER STM32_AHB_PRESCALER 76 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu1_prescaler) 77 #define STM32_CORE_PRESCALER STM32_CPU1_PRESCALER 78 #endif 79 80 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler) 81 #define STM32_FLASH_PRESCALER STM32_AHB3_PRESCALER 82 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler) 83 #define STM32_FLASH_PRESCALER STM32_AHB4_PRESCALER 84 #else 85 #define STM32_FLASH_PRESCALER STM32_CORE_PRESCALER 86 #endif 87 88 #define STM32_ADC_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc_prescaler) 89 #define STM32_ADC12_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc12_prescaler) 90 #define STM32_ADC34_PRESCALER DT_PROP(DT_NODELABEL(rcc), adc34_prescaler) 91 92 /** STM2H7RS specific RCC dividers */ 93 #if defined(CONFIG_SOC_SERIES_STM32H7RSX) 94 #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), dcpre) 95 #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre) 96 #define STM32_PPRE1 DT_PROP(DT_NODELABEL(rcc), ppre1) 97 #define STM32_PPRE2 DT_PROP(DT_NODELABEL(rcc), ppre2) 98 #define STM32_PPRE4 DT_PROP(DT_NODELABEL(rcc), ppre4) 99 #define STM32_PPRE5 DT_PROP(DT_NODELABEL(rcc), ppre5) 100 #else 101 #define STM32_D1CPRE DT_PROP(DT_NODELABEL(rcc), d1cpre) 102 #define STM32_HPRE DT_PROP(DT_NODELABEL(rcc), hpre) 103 #define STM32_D2PPRE1 DT_PROP(DT_NODELABEL(rcc), d2ppre1) 104 #define STM32_D2PPRE2 DT_PROP(DT_NODELABEL(rcc), d2ppre2) 105 #define STM32_D1PPRE DT_PROP(DT_NODELABEL(rcc), d1ppre) 106 #define STM32_D3PPRE DT_PROP(DT_NODELABEL(rcc), d3ppre) 107 #endif /* CONFIG_SOC_SERIES_STM32H7RSX */ 108 109 /** STM2WBA specifics RCC dividers */ 110 #define STM32_AHB5_DIV DT_PROP(DT_NODELABEL(rcc), ahb5_div) 111 112 #define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc)) 113 114 /* To enable use of IS_ENABLED utility macro, these symbols 115 * should not be defined directly using DT_SAME_NODE. 116 */ 117 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll)) 118 #define STM32_SYSCLK_SRC_PLL 1 119 #endif 120 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 121 #define STM32_SYSCLK_SRC_HSI 1 122 #endif 123 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 124 #define STM32_SYSCLK_SRC_HSE 1 125 #endif 126 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 127 #define STM32_SYSCLK_SRC_MSI 1 128 #endif 129 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 130 #define STM32_SYSCLK_SRC_MSIS 1 131 #endif 132 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 133 #define STM32_SYSCLK_SRC_CSI 1 134 #endif 135 136 137 /** PLL node related symbols */ 138 139 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f2_pll_clock, okay) || \ 140 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f4_pll_clock, okay) || \ 141 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f7_pll_clock, okay) || \ 142 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g0_pll_clock, okay) || \ 143 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32g4_pll_clock, okay) || \ 144 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l4_pll_clock, okay) || \ 145 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32u5_pll_clock, okay) || \ 146 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wb_pll_clock, okay) || \ 147 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32wba_pll_clock, okay) || \ 148 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7_pll_clock, okay) || \ 149 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32h7rs_pll_clock, okay) 150 #define STM32_PLL_ENABLED 1 151 #define STM32_PLL_M_DIVISOR DT_PROP(DT_NODELABEL(pll), div_m) 152 #define STM32_PLL_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul_n) 153 #define STM32_PLL_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_p) 154 #define STM32_PLL_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_p, 1) 155 #define STM32_PLL_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_q) 156 #define STM32_PLL_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_q, 1) 157 #define STM32_PLL_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_r) 158 #define STM32_PLL_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_r, 1) 159 #define STM32_PLL_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), div_s) 160 #define STM32_PLL_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll), div_s, 1) 161 #define STM32_PLL_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll), fracn) 162 #define STM32_PLL_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll), fracn, 1) 163 #endif 164 165 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f4_plli2s_clock, okay) 166 #define STM32_PLLI2S_ENABLED 1 167 #define STM32_PLLI2S_M_DIVISOR STM32_PLL_M_DIVISOR 168 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 169 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 170 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 171 #endif 172 173 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f412_plli2s_clock, okay) 174 #define STM32_PLLI2S_ENABLED 1 175 #define STM32_PLLI2S_M_DIVISOR DT_PROP(DT_NODELABEL(plli2s), div_m) 176 #define STM32_PLLI2S_N_MULTIPLIER DT_PROP(DT_NODELABEL(plli2s), mul_n) 177 #define STM32_PLLI2S_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(plli2s), div_r) 178 #define STM32_PLLI2S_R_DIVISOR DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1) 179 #endif 180 181 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32u5_pll_clock, okay) || \ 182 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7_pll_clock, okay) || \ 183 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32h7rs_pll_clock, okay) 184 #define STM32_PLL2_ENABLED 1 185 #define STM32_PLL2_M_DIVISOR DT_PROP(DT_NODELABEL(pll2), div_m) 186 #define STM32_PLL2_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul_n) 187 #define STM32_PLL2_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_p) 188 #define STM32_PLL2_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_p, 1) 189 #define STM32_PLL2_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_q) 190 #define STM32_PLL2_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_q, 1) 191 #define STM32_PLL2_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_r) 192 #define STM32_PLL2_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_r, 1) 193 #define STM32_PLL2_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_s) 194 #define STM32_PLL2_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_s, 1) 195 #define STM32_PLL2_T_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), div_t) 196 #define STM32_PLL2_T_DIVISOR DT_PROP_OR(DT_NODELABEL(pll2), div_t, 1) 197 #define STM32_PLL2_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll2), fracn) 198 #define STM32_PLL2_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll2), fracn, 1) 199 #endif 200 201 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7_pll_clock, okay) || \ 202 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32u5_pll_clock, okay) || \ 203 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32h7rs_pll_clock, okay) 204 #define STM32_PLL3_ENABLED 1 205 #define STM32_PLL3_M_DIVISOR DT_PROP(DT_NODELABEL(pll3), div_m) 206 #define STM32_PLL3_N_MULTIPLIER DT_PROP(DT_NODELABEL(pll3), mul_n) 207 #define STM32_PLL3_P_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_p) 208 #define STM32_PLL3_P_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_p, 1) 209 #define STM32_PLL3_Q_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_q) 210 #define STM32_PLL3_Q_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_q, 1) 211 #define STM32_PLL3_R_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_r) 212 #define STM32_PLL3_R_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_r, 1) 213 #define STM32_PLL3_S_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), div_s) 214 #define STM32_PLL3_S_DIVISOR DT_PROP_OR(DT_NODELABEL(pll3), div_s, 1) 215 #define STM32_PLL3_FRACN_ENABLED DT_NODE_HAS_PROP(DT_NODELABEL(pll3), fracn) 216 #define STM32_PLL3_FRACN_VALUE DT_PROP_OR(DT_NODELABEL(pll3), fracn, 1) 217 #endif 218 219 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f1_pll_clock, okay) 220 #define STM32_PLL_ENABLED 1 221 #define STM32_PLL_XTPRE DT_PROP(DT_NODELABEL(pll), xtpre) 222 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 223 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), usbpre) 224 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f0_pll_clock, okay) || \ 225 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f100_pll_clock, okay) || \ 226 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32f105_pll_clock, okay) 227 #define STM32_PLL_ENABLED 1 228 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 229 #define STM32_PLL_PREDIV DT_PROP(DT_NODELABEL(pll), prediv) 230 #define STM32_PLL_USBPRE DT_PROP(DT_NODELABEL(pll), otgfspre) 231 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll), st_stm32l0_pll_clock, okay) 232 #define STM32_PLL_ENABLED 1 233 #define STM32_PLL_DIVISOR DT_PROP(DT_NODELABEL(pll), div) 234 #define STM32_PLL_MULTIPLIER DT_PROP(DT_NODELABEL(pll), mul) 235 #endif 236 237 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32f105_pll2_clock, okay) 238 #define STM32_PLL2_ENABLED 1 239 #define STM32_PLL2_MULTIPLIER DT_PROP(DT_NODELABEL(pll2), mul) 240 #define STM32_PLL2_PREDIV DT_PROP(DT_NODELABEL(pll2), prediv) 241 #endif 242 243 /** PLL/PLL1 clock source */ 244 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll), okay) && \ 245 DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks) 246 #define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll)) 247 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msi)) 248 #define STM32_PLL_SRC_MSI 1 249 #endif 250 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 251 #define STM32_PLL_SRC_MSIS 1 252 #endif 253 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 254 #define STM32_PLL_SRC_HSI 1 255 #endif 256 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_csi)) 257 #define STM32_PLL_SRC_CSI 1 258 #endif 259 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 260 #define STM32_PLL_SRC_HSE 1 261 #endif 262 #if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(pll2)) 263 #define STM32_PLL_SRC_PLL2 1 264 #endif 265 266 #endif 267 268 /** PLL2 clock source */ 269 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll2), okay) && \ 270 DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks) 271 #define DT_PLL2_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll2)) 272 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 273 #define STM32_PLL2_SRC_MSIS 1 274 #endif 275 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 276 #define STM32_PLL2_SRC_HSI 1 277 #endif 278 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 279 #define STM32_PLL2_SRC_HSE 1 280 #endif 281 282 #endif 283 284 /** PLL3 clock source */ 285 #if DT_NODE_HAS_STATUS(DT_NODELABEL(pll3), okay) && \ 286 DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks) 287 #define DT_PLL3_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll3)) 288 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis)) 289 #define STM32_PLL3_SRC_MSIS 1 290 #endif 291 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hsi)) 292 #define STM32_PLL3_SRC_HSI 1 293 #endif 294 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_hse)) 295 #define STM32_PLL3_SRC_HSE 1 296 #endif 297 298 #endif 299 300 301 /** Fixed clocks related symbols */ 302 303 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), fixed_clock, okay) 304 #define STM32_LSE_ENABLED 1 305 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 306 #define STM32_LSE_DRIVING 0 307 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 308 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lse), st_stm32_lse_clock, okay) 309 #define STM32_LSE_ENABLED 1 310 #define STM32_LSE_FREQ DT_PROP(DT_NODELABEL(clk_lse), clock_frequency) 311 #define STM32_LSE_DRIVING DT_PROP(DT_NODELABEL(clk_lse), driving_capability) 312 #define STM32_LSE_BYPASS DT_PROP(DT_NODELABEL(clk_lse), lse_bypass) 313 #else 314 #define STM32_LSE_ENABLED 0 315 #define STM32_LSE_FREQ 0 316 #define STM32_LSE_DRIVING 0 317 #define STM32_LSE_BYPASS 0 318 #endif 319 320 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) || \ 321 DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32l0_msi_clock, okay) 322 #define STM32_MSI_ENABLED 1 323 #define STM32_MSI_RANGE DT_PROP(DT_NODELABEL(clk_msi), msi_range) 324 #endif 325 326 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msi), st_stm32_msi_clock, okay) 327 #define STM32_MSI_ENABLED 1 328 #define STM32_MSI_PLL_MODE DT_PROP(DT_NODELABEL(clk_msi), msi_pll_mode) 329 #endif 330 331 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msis), st_stm32u5_msi_clock, okay) 332 #define STM32_MSIS_ENABLED 1 333 #define STM32_MSIS_RANGE DT_PROP(DT_NODELABEL(clk_msis), msi_range) 334 #define STM32_MSIS_PLL_MODE DT_PROP(DT_NODELABEL(clk_msis), msi_pll_mode) 335 #else 336 #define STM32_MSIS_ENABLED 0 337 #define STM32_MSIS_RANGE 0 338 #define STM32_MSIS_PLL_MODE 0 339 #endif 340 341 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_msik), st_stm32u5_msi_clock, okay) 342 #define STM32_MSIK_ENABLED 1 343 #define STM32_MSIK_RANGE DT_PROP(DT_NODELABEL(clk_msik), msi_range) 344 #define STM32_MSIK_PLL_MODE DT_PROP(DT_NODELABEL(clk_msik), msi_pll_mode) 345 #else 346 #define STM32_MSIK_ENABLED 0 347 #define STM32_MSIK_RANGE 0 348 #define STM32_MSIK_PLL_MODE 0 349 #endif 350 351 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_csi), fixed_clock, okay) 352 #define STM32_CSI_ENABLED 1 353 #define STM32_CSI_FREQ DT_PROP(DT_NODELABEL(clk_csi), clock_frequency) 354 #else 355 #define STM32_CSI_FREQ 0 356 #endif 357 358 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi), fixed_clock, okay) 359 #define STM32_LSI_ENABLED 1 360 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi), clock_frequency) 361 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi1), fixed_clock, okay) 362 #define STM32_LSI_ENABLED 1 363 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi1), clock_frequency) 364 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_lsi2), fixed_clock, okay) 365 #define STM32_LSI_ENABLED 1 366 #define STM32_LSI_FREQ DT_PROP(DT_NODELABEL(clk_lsi2), clock_frequency) 367 #else 368 #define STM32_LSI_FREQ 0 369 #endif 370 371 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), fixed_clock, okay) 372 #define STM32_HSI_DIV_ENABLED 0 373 #define STM32_HSI_ENABLED 1 374 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 375 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \ 376 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \ 377 || DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) 378 #define STM32_HSI_DIV_ENABLED 1 379 #define STM32_HSI_ENABLED 1 380 #define STM32_HSI_DIVISOR DT_PROP(DT_NODELABEL(clk_hsi), hsi_div) 381 #define STM32_HSI_FREQ DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency) 382 #else 383 #define STM32_HSI_DIV_ENABLED 0 384 #define STM32_HSI_DIVISOR 1 385 #define STM32_HSI_FREQ 0 386 #endif 387 388 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), fixed_clock, okay) 389 #define STM32_HSE_ENABLED 1 390 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 391 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32_hse_clock, okay) 392 #define STM32_HSE_ENABLED 1 393 #define STM32_HSE_BYPASS DT_PROP(DT_NODELABEL(clk_hse), hse_bypass) 394 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 395 #define STM32_HSE_CSS DT_PROP(DT_NODELABEL(clk_hse), css_enabled) 396 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wl_hse_clock, okay) 397 #define STM32_HSE_ENABLED 1 398 #define STM32_HSE_TCXO DT_PROP(DT_NODELABEL(clk_hse), hse_tcxo) 399 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 400 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 401 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32wba_hse_clock, okay) 402 #define STM32_HSE_ENABLED 1 403 #define STM32_HSE_DIV2 DT_PROP(DT_NODELABEL(clk_hse), hse_div2) 404 #define STM32_HSE_FREQ DT_PROP(DT_NODELABEL(clk_hse), clock_frequency) 405 #else 406 #define STM32_HSE_FREQ 0 407 #endif 408 409 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), fixed_clock, okay) 410 #define STM32_HSI48_ENABLED 1 411 #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency) 412 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi48), st_stm32_hsi48_clock, okay) 413 #define STM32_HSI48_ENABLED 1 414 #define STM32_HSI48_FREQ DT_PROP(DT_NODELABEL(clk_hsi48), clock_frequency) 415 #define STM32_HSI48_CRS_USB_SOF DT_PROP(DT_NODELABEL(clk_hsi48), crs_usb_sof) 416 #endif 417 418 #if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(perck), st_stm32_clock_mux, okay) 419 #define STM32_CKPER_ENABLED 1 420 #endif 421 422 /** Driver structure definition */ 423 424 struct stm32_pclken { 425 uint32_t bus; 426 uint32_t enr; 427 }; 428 429 /** Device tree clocks helpers */ 430 431 #define STM32_CLOCK_INFO(clk_index, node_id) \ 432 { \ 433 .enr = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bits), \ 434 .bus = DT_CLOCKS_CELL_BY_IDX(node_id, clk_index, bus) \ 435 } 436 #define STM32_DT_CLOCKS(node_id) \ 437 { \ 438 LISTIFY(DT_NUM_CLOCKS(node_id), \ 439 STM32_CLOCK_INFO, (,), node_id) \ 440 } 441 442 #define STM32_DT_INST_CLOCKS(inst) \ 443 STM32_DT_CLOCKS(DT_DRV_INST(inst)) 444 445 #define STM32_DOMAIN_CLOCK_INST_SUPPORT(inst) DT_INST_CLOCKS_HAS_IDX(inst, 1) || 446 #define STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT \ 447 (DT_INST_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_INST_SUPPORT) 0) 448 449 #define STM32_DOMAIN_CLOCK_SUPPORT(id) DT_CLOCKS_HAS_IDX(DT_NODELABEL(id), 1) || 450 #define STM32_DT_DEV_DOMAIN_CLOCK_SUPPORT \ 451 (DT_FOREACH_STATUS_OKAY(STM32_DOMAIN_CLOCK_SUPPORT) 0) 452 453 /** Clock source binding accessors */ 454 455 /** 456 * @brief Obtain register field from clock configuration. 457 * 458 * @param clock clock bit field value. 459 */ 460 #define STM32_CLOCK_REG_GET(clock) \ 461 (((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK) 462 463 /** 464 * @brief Obtain position field from clock configuration. 465 * 466 * @param clock Clock bit field value. 467 */ 468 #define STM32_CLOCK_SHIFT_GET(clock) \ 469 (((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK) 470 471 /** 472 * @brief Obtain mask field from clock configuration. 473 * 474 * @param clock Clock bit field value. 475 */ 476 #define STM32_CLOCK_MASK_GET(clock) \ 477 (((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK) 478 479 /** 480 * @brief Obtain value field from clock configuration. 481 * 482 * @param clock Clock bit field value. 483 */ 484 #define STM32_CLOCK_VAL_GET(clock) \ 485 (((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK) 486 487 #if defined(STM32_HSE_CSS) 488 /** 489 * @brief Called if the HSE clock security system detects a clock fault. 490 * 491 * The function is called in interrupt context. 492 * 493 * The default (weakly-linked) implementation does nothing and should be 494 * overridden. 495 */ 496 void stm32_hse_css_callback(void); 497 #endif 498 499 #endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_STM32_CLOCK_CONTROL_H_ */ 500
