1 /*$Id: //dwh/bluetooth/DWC_ble154combo/firmware/rel/1.32a-lca02/firmware/public_inc/common_types.h#3 $*/ 2 /** 3 ******************************************************************************** 4 * @file common_types.h 5 * @brief This file contains common includes for BLE FW LL. 6 ****************************************************************************** 7 * @copy 8 * This Synopsys DWC Bluetooth Low Energy Combo Link Layer/MAC software and 9 * associated documentation ( hereinafter the "Software") is an unsupported 10 * proprietary work of Synopsys, Inc. unless otherwise expressly agreed to in 11 * writing between Synopsys and you. The Software IS NOT an item of Licensed 12 * Software or a Licensed Product under any End User Software License Agreement 13 * or Agreement for Licensed Products with Synopsys or any supplement thereto. 14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included in 15 * the SOFTWARE may be the trademarks of their respective owners. 16 * 17 * Synopsys MIT License: 18 * Copyright (c) 2020-Present Synopsys, Inc 19 * 20 * Permission is hereby granted, free of charge, to any person obtaining a copy of 21 * the Software), to deal in the Software without restriction, including without 22 * limitation the rights to use, copy, modify, merge, publish, distribute, 23 * sublicense, and/or sell copies of the Software, and to permit persons to whom 24 * the Software is furnished to do so, subject to the following conditions: 25 * 26 * The above copyright notice and this permission notice shall be included in all 27 * copies or substantial portions of the Software. 28 * 29 * THIS SOFTWARE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 30 * IMPLIED, INCLUDING, BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 31 * FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT. IN NO EVENT SHALL THE 32 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 33 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT, OR OTHERWISE ARISING FROM, 34 * OUT OF, OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 35 * 36 * */ 37 38 /* Define to prevent recursive inclusion -------------------------------------*/ 39 40 #ifndef COMMON_TYPES_H_ 41 #define COMMON_TYPES_H_ 42 #include "_40nm_reg_files/DWC_ble154combo.h" 43 #include "bsp.h" 44 #include "ll_fw_config.h" 45 #include "mem_intf.h" 46 #include "os_wrapper.h" 47 48 49 /********************************************************************** */ 50 /****************** BLE MAC COMBO Configurations*********************** */ 51 /********************************************************************** */ 52 #ifdef BLE 53 #define SUPPORT_BLE 1 54 #else 55 #define SUPPORT_BLE 0 56 #endif 57 58 #ifdef MAC 59 #define SUPPORT_MAC 1 60 #else 61 #define SUPPORT_MAC 0 62 #endif 63 #ifdef ANT_ROLE 64 #define SUPPORT_ANT 1 65 66 #ifdef SUPPORT_ANT_TESTING 67 #define SUPPORT_ANT_HCI_UART 1 68 #else 69 #define SUPPORT_ANT_HCI_UART 0 70 #endif /* SUPPORT_ANT_HCI_UART*/ 71 72 #else 73 #define SUPPORT_ANT 0 74 #define SUPPORT_ANT_HCI_UART 0 75 #endif 76 77 #ifdef MAC_LAYER 78 #define MAC_LAYER_BUILD 1 79 #else 80 #define MAC_LAYER_BUILD 0 81 #endif 82 83 #ifdef SUPPORT_MAC_HCI_UART 84 #define SUPPORT_MAC_HCI_UART 1 85 #else 86 #define SUPPORT_MAC_HCI_UART 0 87 #endif 88 89 #ifdef SUPPORT_AUG_MAC_HCI_UART 90 #define SUPPORT_AUG_MAC_HCI_UART 1 91 #else 92 #define SUPPORT_AUG_MAC_HCI_UART 0 93 #endif 94 95 #if((!SUPPORT_BLE)&&(SUPPORT_MAC || SUPPORT_AUG_MAC_HCI_UART)&&(RAL_NUMBER_OF_INSTANCE>1)) 96 #error "BLE controller must be enabled to support MAC multiple Instances" 97 #endif 98 99 #if((SUPPORT_MAC)&&(SUPPORT_AUG_MAC_HCI_UART)&&(RAL_NUMBER_OF_INSTANCE<2)) 100 #error "RAL_NUMBER_OF_INSTANCE must be 2 to support MAC and Augmented MAC" 101 #endif 102 103 #if((!SUPPORT_BLE)&&(SUPPORT_MAC)&&(SUPPORT_ANT)) 104 #error "BLE controller must be enabled to support MAC and ANT Coexistence" 105 #endif 106 107 #define SUPPORT_COEXISTENCE ((SUPPORT_BLE&&SUPPORT_MAC) || (SUPPORT_BLE&&SUPPORT_ANT)) 108 #define SUPPORT_ANT_COEXISTENCE (SUPPORT_BLE&&SUPPORT_ANT) 109 /****************** User configuration **********************************/ 110 #define CS_TESTING TRUE 111 112 #define SUPPORT_GNRC_SCHDLR_IF (1) 113 /********************* Macros **********************************/ 114 115 #ifndef SUCCESS 116 #define SUCCESS 0 117 #endif 118 #ifndef GENERAL_FAILURE 119 #define GENERAL_FAILURE -1 120 #endif 121 #ifndef GENERAL_ERROR_STATUS 122 #define GENERAL_ERROR_STATUS 0xFF 123 #endif 124 125 #ifndef TRUE 126 #define TRUE 1 127 #endif /* TRUE */ 128 129 #ifndef FALSE 130 #define FALSE 0 131 #endif /* FALSE */ 132 133 #ifndef NULL 134 #define NULL ((void *)0) 135 #endif /* NULL */ 136 137 #define UNUSED_VALUE 0 138 #define UNUSED_PTR NULL 139 140 #define MEMSET(ptr_memory, value, memory_size) ble_memset(ptr_memory, value, memory_size) 141 #define MEMCPY(ptr_destination, ptr_source, memory_size) ble_memcpy(ptr_destination, ptr_source, memory_size) 142 #define MEMCMP(ptr_destination, ptr_source, memory_size) ble_memcmp(ptr_destination, ptr_source, memory_size) 143 #define MEMMOV(ptr_destination, ptr_source, memory_size) ble_memmov(ptr_destination, ptr_source, memory_size) 144 #define MEMCPY_N_BYTES(ptr_dest, ptr_src,no_bytes ,keep_endian) ble_memcpy_n_bytes(ptr_dest,ptr_src ,no_bytes ,keep_endian) 145 146 147 148 extern os_mutex_id g_ll_lock; 149 #define LL_LOCK() os_rcrsv_mutex_wait(g_ll_lock,0xffffffff) 150 #define LL_UNLOCK() os_rcrsv_mutex_release(g_ll_lock) 151 152 #ifndef SUPPORT_ANT_DIV 153 #define SUPPORT_ANT_DIV 0 154 #endif 155 156 #if SUPPORT_MAC 157 #define RADIO_MAC_TX_DONE_EVENT_MAX 1 158 #define RAL_SM_DONE_EVENT_MAX RADIO_TX_RX_PACKET_BLOCK_COUNT 159 #define ED_TIMER_EVENT_MAX 1 160 #define MAX_MLME_TIMER_EVENT MAC_NUMBER_OF_INSTANCE 161 #define MAX_DIRECT_DATA_TX_EVENT MAC_NUMBER_OF_INSTANCE 162 #define MAX_INDIRECT_DATA_TIMEOUT_EVENT MAX_NUMBER_OF_INDIRECT_DATA 163 #define PRDC_CLBR_TMR_EVENT_MAX 1 164 #define CSL_RCV_TMR_EVENT_MAX 1 165 166 /* Size in octets of extended address used in security processing */ 167 #define EXT_ADDRESS_LENGTH 8 168 #endif /* SUPPORT_MAC */ 169 170 #if SUPPORT_MAC && SUPPORT_OPENTHREAD_1_2 171 /* compiler flag to control supporting of CSL transmitter , RADIO TX at specific time , 1 supported , 0 not supported */ 172 #define CONFIG_MAC_CSL_TRANSMITTER_ENABLE 1 173 /* compiler flag to control supporting of CSL receiver , RADIO RX at specific time, 1 supported , 0 not supported */ 174 #define CONFIG_MAC_CSL_RECEIVER_ENABLE 1 175 /* compiler flag to control supporting of Radio security handling */ 176 #define SUPPORT_RADIO_SECURITY_OT_1_2 1 177 /* compiler flag to control supporting of Enhanced Ack Link metrics probing */ 178 #define SUPPORT_ENH_ACK_LINK_METRICS_PROBING_OT_1_2 1 179 /* compiler flag to control supporting of Time sync experimental feature of OT 1.2 180 * (it is not a thread 1.2 shall not be added except for with OT 1.2 for testing purpose) */ 181 #define SUPPORT_TIME_SYNC_OT_1_2 1 182 #else 183 #define CONFIG_MAC_CSL_TRANSMITTER_ENABLE 0 184 #define CONFIG_MAC_CSL_RECEIVER_ENABLE 0 185 #define SUPPORT_RADIO_SECURITY_OT_1_2 0 186 #define SUPPORT_ENH_ACK_LINK_METRICS_PROBING_OT_1_2 0 187 #define SUPPORT_TIME_SYNC_OT_1_2 0 188 #endif /*SUPPORT_MAC && SUPPORT_OPENTHREAD_1_2 */ 189 190 /* end of radio activity custom command flag */ 191 #define END_OF_RADIO_ACTIVITY_REPORTING 1 /* Enable\Disable end of radio activity reporting feature. Enable:1 - Disable:0 */ 192 193 /* Supported PHYs*/ 194 typedef enum { 195 LE_NO_CHANGE = 0x00, 196 LE_1M = 0x01, 197 LE_2M = 0x02, 198 LE_CODED_S8 = 0x03, 199 LE_CODED = 0x04, 200 #if (SUPPORT_LE_POWER_CONTROL) 201 LE_PHY_UNDEFINED = 0xFC, 202 NEW_PHY_CODED_S2 = 0xFD, 203 NEW_PHY_CODED_S8 = 0xFE, 204 NEW_PHY_CODED_COMBINED = 0xFF, 205 #endif /* SUPPORT_LE_POWER_CONTROL */ 206 207 /* PHY Recommendations - Combined Values */ 208 #if ((SUPPORT_CONNECTED_ISOCHRONOUS && SUPPORT_MASTER_CONNECTION) || SUPPORT_BRD_ISOCHRONOUS) 209 RECOMMEND_1M_2M = 0x03, 210 RECOMMEND_1M_CODED = 0x05, 211 RECOMMEND_2M_CODED = 0x06, 212 RECOMMEND_1M_2M_CODED = 0x07, 213 #endif /* ((SUPPORT_CONNECTED_ISOCHRONOUS && SUPPORT_MASTER_CONNECTION) || SUPPORT_BRD_ISOCHRONOUS) */ 214 } tx_rx_phy_e; 215 216 /** 217 * @brief time stamp structure. 218 */ 219 typedef struct time_st { 220 uint32_t time_stamp_base; 221 uint16_t time_stamp_fine; 222 uint8_t overflow_flag; 223 } ble_time_t, *ble_time_p; 224 typedef enum dpslp_state { 225 DEEP_SLEEP_ENABLE = 0x01, 226 DEEP_SLEEP_DISABLE = 0x00 227 } dpslp_state_e; 228 229 /** 230 * @enum crypto_endian_enum_t 231 * @brief States the available endian formats. 232 * 233 */ 234 typedef enum { 235 CRYPTO_LITTLE_ENDIAN, 236 CRYPTO_BIG_ENDIAN 237 } crypto_endian_enum_t; 238 239 /** 240 * @enum security_mode_enum_t 241 * @brief Contains the available security modes. 242 * 243 * Note: The enum values should be the same as specified in the register 244 * address header file. 245 */ 246 typedef enum { 247 ECB_DECRYPT = 0, 248 CCM_DECRYPT = 1, 249 ECB_ENCRYPT = 2, 250 CCM_ENCRYPT = 3, 251 CTR_ENCRYPT = 4, 252 CTR_DECRYPT = 5, 253 MODES_MAX_NUM 254 } security_mode_enum_t; 255 256 #if SUPPORT_MAC 257 typedef enum ral_phy_rate_enum { 258 #if SUPPORT_A_MAC 259 RAL_RATE_125K = 0x00, 260 RAL_RATE_1M = 0x02, 261 RAL_RATE_2M = 0x03, 262 #endif 263 RAL_RATE_256K = 0x01 264 } ral_phy_rate_enum_t; 265 266 #endif /*SUPPORT_MAC*/ 267 /** 268 * @enum extrnl_evnt_priority_e 269 * @brief External Event priority 270 */ 271 typedef enum _extrnl_evnt_priority_e 272 { 273 PRIORITY_DEFAULT, 274 PRIORITY_HIGH, 275 PRIORITY_CRITICAL 276 }extrnl_evnt_priority_e; 277 278 /** 279 * @enum extrnl_evnt_state_e 280 * @brief External Event Blocked State and reason 281 */ 282 typedef enum _extrnl_evnt_state_e 283 { 284 STATE_BLOCKED_UNKNOWN, 285 STATE_BLOCKED_PRIORITY, 286 STATE_BLOCKED_CANCELLED, 287 STATE_BLOCKED_LATE, 288 STATE_BLOCKED_DEADLINE, 289 STATE_NOT_BLOCKED 290 }extrnl_evnt_state_e; 291 292 /** 293 * @brief Enumeration of the source type used to drive the sleep timer. 294 */ 295 typedef enum _slptmr_src_type_e { 296 CRYSTAL_OSCILLATOR_SLPTMR = 0x00, 297 #if (USE_NON_ACCURATE_32K_SLEEP_CLK) 298 RCO_SLPTMR = 0x01, 299 RTC_SLPTMR = 0x02 300 #endif /* USE_NON_ACCURATE_32K_SLEEP_CLK */ 301 }slptmr_src_type_e; 302 303 /** 304 * @brief Enumeration of the antenna diversity interval type. 305 */ 306 #if SUPPORT_MAC && SUPPORT_ANT_DIV 307 typedef enum ant_intrv_type_enum { 308 NO_TYPE, 309 FIXED_TIME, 310 PACKETS_NUMBER 311 } ant_intrv_type_enum_t; 312 313 /* 314 * @brief structure that hold antenna diversity parameters information. 315 */ 316 typedef struct _antenna_diversity_st{ 317 ant_intrv_type_enum_t ant_intrv_type; /* antenna interval type: FIXED_TIME(us) or PACKETS_NUMBER(n) */ 318 uint32_t ant_intrv_value; /* antenna interval value based on type; us for FIXED_TIME, n for PACKETS_NUMBER */ 319 uint16_t wntd_coord_shrt_addr; /* wanted coordinator/router short address */ 320 uint8_t wntd_coord_ext_addr[EXT_ADDRESS_LENGTH]; /* wanted coordinator/router extended address */ 321 uint8_t max_rx_ack_retries; /* max number of retries to receive ack in case of ack error reception*/ 322 } antenna_diversity_st; 323 #endif /* SUPPORT_MAC && SUPPORT_ANT_DIV */ 324 325 /* 326 * @brief structure that hold some information about the data transmitted across layers. 327 */ 328 typedef struct ble_buff_hdr_st { 329 /* pointer to buffer allocated in TX/RX buffer*/ 330 uint8_t *buff_start; 331 /* pointer to next ble_buff_hdr node */ 332 struct ble_buff_hdr_st *next_pkt; 333 /* Total buffer size */ 334 uint16_t total_len; 335 /* offset to data location from the packet start pointed to by buff_start */ 336 uint16_t data_offset; 337 /* data size for the data pointed to by buff_start + data_offset*/ 338 uint16_t data_size; 339 /* bit field flags to be used for identifying buffer type data/control buffer, 340 * for data is it a BLE/MAC/ANT, does it contain complete SDU packet of it is a fragment, 341 * if it is a fragment is it the start or continuation or last fragment. */ 342 uint8_t ble_hdr_flags; 343 } pkt_buff_hdr_t ,ble_buff_hdr_t, *ble_buff_hdr_p; 344 345 #if (SUPPORT_BRD_ISOCHRONOUS || SUPPORT_SYNC_ISOCHRONOUS || (SUPPORT_CONNECTED_ISOCHRONOUS && ( SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION))) 346 /** 347 * @brief: PDU info structure 348 */ 349 typedef struct _iso_pdu_buff_hdr_st { 350 ble_buff_hdr_t pkt; /* PDU Packet */ 351 #if(SUPPORT_CONNECTED_ISOCHRONOUS && (SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) 352 uint8_t flsh_tmout_cnt; /* flush timeout counter */ 353 uint8_t flsh_tmout_subevnt_cnt; /* flush timeout subevent number */ 354 uint8_t rx_flsh_tmout_cnt_updtd; /* flush timeout count updated or not flag */ 355 #endif //(SUPPORT_CONNECTED_ISOCHRONOUS && (SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) 356 uint8_t status; 357 } iso_pdu_buff_hdr_st; 358 /** 359 * @brief: SDU info structure 360 */ 361 typedef struct _sdu_buf_hdr_st { 362 iso_pdu_buff_hdr_st* ptr_last_pdu_buff_hdr; /* pointer to the last pdu buffer header pointed to this sdu */ 363 struct _sdu_buf_hdr_st* ptr_nxt_sdu_buff_hdr; /* next sdu pointer */ 364 uint32_t*ptr_sdu_buffer; /* pointer to SDU buffer in system memory for rx*/ 365 uint32_t time_stamp; /* Time Stamp associated with this SDU */ 366 uint32_t time_offset; /* Time Offset used only in framed SDUs */ 367 uint16_t pkt_sqnc_num; /* Packet Sequence Number */ 368 uint16_t iso_sdu_len; /* ISO SDU data real length */ 369 uint8_t pkt_status_flag; 370 uint8_t pb_flag; /* PB_flag used in rx */ 371 /* 372 * the first one will have the value 10 complete sdu until a new sdu fragment will be received then it will be 00 first fragment 373 * the subsequent one will have the value 11 last fragment until a new sdu fragment will be received then it will be 01 continuation fragment 374 * 375 * */ 376 } iso_sdu_buf_hdr_st, *iso_sdu_buf_hdr_p; 377 #endif /* (SUPPORT_BRD_ISOCHRONOUS || SUPPORT_SYNC_ISOCHRONOUSs || (SUPPORT_CONNECTED_ISOCHRONOUS && ( SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION))) */ 378 379 #if SUPPORT_LE_PAWR_ADVERTISER_ROLE 380 /** 381 * brief: PAWR host buffer struct 382 */ 383 typedef struct _pawr_host_buffer { 384 uint8_t buffer[257]; 385 uint8_t total_data_lenth; 386 uint8_t number_of_reports; 387 }pawr_host_buffer; 388 #endif /* SUPPORT_LE_PAWR_ADVERTISER_ROLE */ 389 390 391 /* 392 * @brief Transport layer event 393 */ 394 typedef enum { 395 HCI_CMD_PCKT = 0x01, 396 HCI_ACL_DATA_PCKT = 0x02, 397 HCI_EVNT_PCKT = 0x04, 398 HCI_ISO_DATA_PCKT = 0x05, 399 400 401 #if (SUPPORT_MAC && SUPPORT_MAC_HCI_UART) 402 HCI_MAC_REQ = 0x0A, 403 HCI_MAC_CFM = 0x0B, 404 HCI_MAC_KEY_TBL_CFM = 0x0E, 405 #endif /* SUPPORT_MAC && SUPPORT_MAC_HCI_UART */ 406 #if (SUPPORT_ANT_HCI_UART) 407 HCI_ANT_REQ = 0x10, 408 HCI_ANT_CFM = 0x11, 409 #endif /* SUPPORT_ANT_HCI_UART */ 410 #if (SUPPORT_AUG_MAC_HCI_UART) 411 AUG_HCI_MAC_REQ = 0x0C, 412 AUG_HCI_MAC_CFM = 0x0D, 413 #endif /* SUPPORT_AUG_MAC_HCI_UART */ 414 415 } event_t; 416 417 418 419 /*constant flags to be used with ble_buff_hdr_t:ble_hdr_flags*/ 420 #define BLE_BUFF_HDR_STRT_PKT (1<<0) 421 #define BLE_BUFF_HDR_CNTRL_PKT (1<<1) 422 #define BLE_BUFF_HDR_BUFF_FRGMNTD (1<<2) 423 #define BLE_BUFF_HDR_EVNT_CMD_PCKT (1<<3) 424 #define BLE_BUFF_HDR_ACL_DATA_PCKT (1<<4) 425 426 #if ((SUPPORT_CONNECTED_ISOCHRONOUS && (SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) \ 427 ||(SUPPORT_BRD_ISOCHRONOUS || SUPPORT_SYNC_ISOCHRONOUS)) 428 #define BLE_BUFF_HDR_NULL_PCKT (1<<3) 429 /* 430 * BLE_BUFF_HDR_ISO_DATA_PCKT_BIT1 : BLE_BUFF_HDR_ISO_DATA_PCKT_BIT0 = Mode 431 * 1 : 1 = Unframed CIS Data PDU; end fragment of an SDU or a complete SDU. LLID (0b00) 432 * 0 : 1 = Unframed CIS Data PDU; start or continuation fragment of an SDU. 433 * 1 : 0 = Framed CIS Data PDU; one or more segments of an SDU. 434 * */ 435 #define BLE_BUFF_HDR_ISO_DATA_PCKT_BIT0 (1<<5) 436 #define BLE_BUFF_HDR_ISO_DATA_PCKT_BIT1 (1<<6) 437 #endif /* (SUPPORT_CONNECTED_ISOCHRONOUS && (SUPPORT_MASTER_CONNECTION || SUPPORT_SLAVE_CONNECTION)) */ 438 #if (SUPPORT_MAC && SUPPORT_MAC_HCI_UART) 439 #define BLE_BUFF_HDR_MAC_CMD_PCK (1<<6) 440 #define BLE_BUFF_HDR_MAC_KEY_TBL_CMD_PCK ((1<<7)|(1<<4)) 441 #endif /* (SUPPORT_MAC && SUPPORT_MAC_HCI_UART) */ 442 #if (SUPPORT_ANT_HCI_UART) 443 #define BLE_BUFF_HDR_ANT_CMD_PCK (1<<7) 444 #endif /* SUPPORT_ANT_HCI_UART */ 445 #if (SUPPORT_AUG_MAC_HCI_UART) 446 #define BLE_BUFF_HDR_AUG_MAC_CMD_PCK ((1<<7)|(1<<6)) 447 #endif 448 449 450 /** 451 * The default PHY periodic calibration period in second. this Macro can be set to any value , Zero means that phy periodic calibration is disabled 452 */ 453 #define DEFAULT_PHY_CALIBRATION_PERIOD 10 /* Time period for PHY calibration = 10s */ 454 455 #if defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) 456 #define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 1 457 #else 458 #define SUPPORT_MAC_PHY_CONT_TESTING_CMDS 0 459 #if(SUPPORT_MAC_PHY_CONT_TESTING_CMDS) 460 #error "SUPPORT_MAC_PHY_CONT_TESTING_CMDS must be enabled for PHY_40nm_3_00_a or PHY_40nm_3_40_a only" 461 #endif/*end of (SUPPORT_MAC_PHY_CONT_TESTING_CMDS) */ 462 #endif /*end of defined(PHY_40nm_3_00_a) || defined(PHY_40nm_3_40_a) */ 463 464 #ifndef EXTERNAL_CUSTOM_CMDS 465 #define EXTERNAL_CUSTOM_CMDS 0 /* Indicates that an external custom HCI commands module exists */ 466 #endif /* EXTERNAL_CUSTOM_CMDS */ 467 #define SUPPORT_ZIGBEE_PHY_CERTIFICATION 0 /* 0 disable , 1 enable .. used to enable support of hci command required to implement zigbee phy Test cases*/ 468 469 470 #if (!USE_HCI_TRANSPORT) && (SUPPORT_BLE) /* SUPPORT_HCI_EVENT_ONLY cannot be supported with default HCI_transport */ 471 /* if this marco is enabled it will enable the below features 472 * -Queue events - ACL - ISO - Reports into different queues 473 -Allow host to register callback to refuse current controller event and receive it later with another callback*/ 474 #define SUPPORT_HCI_EVENT_ONLY 1 475 476 #else 477 #define SUPPORT_HCI_EVENT_ONLY 0 478 #endif/* (!USE_HCI_TRANSPORT) && (SUPPORT_BLE) */ 479 480 #ifndef SUPPORT_HCI_EVENT_ONLY_TESTING 481 #define SUPPORT_HCI_EVENT_ONLY_TESTING 0 482 #endif /* SUPPORT_HCI_EVENT_ONLY_TESTING */ 483 484 #define SUPPORT_HW_AUDIO_SYNC_SIGNAL 0 485 486 #if SUPPORT_LE_PAWR_SYNC_ROLE 487 #define SUPPORT_PAWR_CUSTOM_SYNC 1 488 #else 489 #define SUPPORT_PAWR_CUSTOM_SYNC 0 490 #endif /* SUPPORT_LE_PAWR_SYNC_ROLE */ 491 492 #define PAWR_TESTING 0 493 #ifndef SUPPORT_LE_PAWR_ADVERTISER_ROLE 494 #define SUPPORT_LE_PAWR_ADVERTISER_ROLE 0 495 #endif 496 497 498 499 #define SUPPORT_TIM_UPDT 1 500 501 #define SUPPORT_RX_DTP_CONTROL 1 /* Enable\Disable ACL Rx data throughput feature */ 502 503 #ifndef SUPPORT_CUSTOM_ADV_SCAN_TESTING 504 #define SUPPORT_CUSTOM_ADV_SCAN_TESTING 0 505 #endif /* SUPPORT_CUSTOM_ADV_SCAN_TESTING */ 506 507 #ifndef SUPPORT_CHANNEL_SOUNDING 508 #define SUPPORT_CHANNEL_SOUNDING 0 509 #endif /* SUPPORT_CHANNEL_SOUNDING */ 510 511 #ifndef SUPPORT_EXT_FEATURE_SET 512 #define SUPPORT_EXT_FEATURE_SET 0 513 #endif /* SUPPORT_EXT_FEATURE_SET */ 514 515 516 #endif /*COMMON_TYPES_H_*/ 517
