1 /* 2 ****************************************************************************** 3 * @file st1vafe3bx_reg.h 4 * @author Sensors Software Solution Team 5 * @brief This file contains all the functions prototypes for the 6 * st1vafe3bx_reg.c driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2024 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef ST1VAFE3BX_REGS_H 23 #define ST1VAFE3BX_REGS_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include <stdint.h> 31 #include <stddef.h> 32 #include <math.h> 33 34 /** @addtogroup ST1VAFE3BX 35 * @{ 36 * 37 */ 38 39 /** @defgroup Endianness definitions 40 * @{ 41 * 42 */ 43 44 #ifndef DRV_BYTE_ORDER 45 #ifndef __BYTE_ORDER__ 46 47 #define DRV_LITTLE_ENDIAN 1234 48 #define DRV_BIG_ENDIAN 4321 49 50 /** if _BYTE_ORDER is not defined, choose the endianness of your architecture 51 * by uncommenting the define which fits your platform endianness 52 */ 53 //#define DRV_BYTE_ORDER DRV_BIG_ENDIAN 54 #define DRV_BYTE_ORDER DRV_LITTLE_ENDIAN 55 56 #else /* defined __BYTE_ORDER__ */ 57 58 #define DRV_LITTLE_ENDIAN __ORDER_LITTLE_ENDIAN__ 59 #define DRV_BIG_ENDIAN __ORDER_BIG_ENDIAN__ 60 #define DRV_BYTE_ORDER __BYTE_ORDER__ 61 62 #endif /* __BYTE_ORDER__*/ 63 #endif /* DRV_BYTE_ORDER */ 64 65 /** 66 * @} 67 * 68 */ 69 70 /** @defgroup STMicroelectronics sensors common types 71 * @{ 72 * 73 */ 74 75 #ifndef MEMS_SHARED_TYPES 76 #define MEMS_SHARED_TYPES 77 78 typedef struct 79 { 80 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 81 uint8_t bit0 : 1; 82 uint8_t bit1 : 1; 83 uint8_t bit2 : 1; 84 uint8_t bit3 : 1; 85 uint8_t bit4 : 1; 86 uint8_t bit5 : 1; 87 uint8_t bit6 : 1; 88 uint8_t bit7 : 1; 89 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 90 uint8_t bit7 : 1; 91 uint8_t bit6 : 1; 92 uint8_t bit5 : 1; 93 uint8_t bit4 : 1; 94 uint8_t bit3 : 1; 95 uint8_t bit2 : 1; 96 uint8_t bit1 : 1; 97 uint8_t bit0 : 1; 98 #endif /* DRV_BYTE_ORDER */ 99 } bitwise_t; 100 101 #define PROPERTY_DISABLE (0U) 102 #define PROPERTY_ENABLE (1U) 103 104 /** @addtogroup Interfaces_Functions 105 * @brief This section provide a set of functions used to read and 106 * write a generic register of the device. 107 * MANDATORY: return 0 -> no Error. 108 * @{ 109 * 110 */ 111 112 typedef int32_t (*stmdev_write_ptr)(void *ctx, uint8_t reg, 113 const uint8_t *data, uint16_t len); 114 typedef int32_t (*stmdev_read_ptr)(void *ctx, uint8_t reg, 115 uint8_t *data, uint16_t len); 116 typedef void (*stmdev_mdelay_ptr)(uint32_t millisec); 117 118 typedef struct 119 { 120 /** Component mandatory fields **/ 121 stmdev_write_ptr write_reg; 122 stmdev_read_ptr read_reg; 123 /** Component optional fields **/ 124 stmdev_mdelay_ptr mdelay; 125 /** Customizable optional pointer **/ 126 void *handle; 127 } stmdev_ctx_t; 128 129 /** 130 * @} 131 * 132 */ 133 134 #endif /* MEMS_SHARED_TYPES */ 135 136 #ifndef MEMS_UCF_SHARED_TYPES 137 #define MEMS_UCF_SHARED_TYPES 138 139 /** @defgroup Generic address-data structure definition 140 * @brief This structure is useful to load a predefined configuration 141 * of a sensor. 142 * You can create a sensor configuration by your own or using 143 * Unico / Unicleo tools available on STMicroelectronics 144 * web site. 145 * 146 * @{ 147 * 148 */ 149 150 typedef struct 151 { 152 uint8_t address; 153 uint8_t data; 154 } ucf_line_t; 155 156 /** 157 * @} 158 * 159 */ 160 161 #endif /* MEMS_UCF_SHARED_TYPES */ 162 163 /** 164 * @} 165 * 166 */ 167 168 /** @defgroup ST1VAFE3BX_Infos 169 * @{ 170 * 171 */ 172 173 /** I2C Device Address 8 bit format if SA0=0 -> 0x if SA0=1 -> 0x **/ 174 #define ST1VAFE3BX_I2C_ADD_L 0x41U 175 #define ST1VAFE3BX_I2C_ADD_H 0x43U 176 177 /** Device Identification (Who am I) **/ 178 #define ST1VAFE3BX_ID 0x48U 179 180 /** 181 * @} 182 * 183 */ 184 185 #define ST1VAFE3BX_EXT_CLK_CFG 0x08U 186 typedef struct 187 { 188 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 189 uint8_t not_used0 : 7; 190 uint8_t ext_clk_en : 1; 191 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 192 uint8_t ext_clk_en : 1; 193 uint8_t not_used0 : 7; 194 #endif /* DRV_BYTE_ORDER */ 195 } st1vafe3bx_ext_clk_cfg_t; 196 197 #define ST1VAFE3BX_PIN_CTRL 0x0CU 198 typedef struct 199 { 200 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 201 uint8_t sim : 1; 202 uint8_t pp_od : 1; 203 uint8_t cs_pu_dis : 1; 204 uint8_t h_lactive : 1; 205 uint8_t not_used0 : 2; 206 uint8_t sda_pu_en : 1; 207 uint8_t sdo_pu_en : 1; 208 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 209 uint8_t sdo_pu_en : 1; 210 uint8_t sda_pu_en : 1; 211 uint8_t not_used0 : 2; 212 uint8_t h_lactive : 1; 213 uint8_t cs_pu_dis : 1; 214 uint8_t pp_od : 1; 215 uint8_t sim : 1; 216 #endif /* DRV_BYTE_ORDER */ 217 } st1vafe3bx_pin_ctrl_t; 218 219 #define ST1VAFE3BX_WAKE_UP_DUR_EXT 0x0EU 220 typedef struct 221 { 222 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 223 uint8_t not_used0 : 4; 224 uint8_t wu_dur_extended : 1; 225 uint8_t not_used1 : 3; 226 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 227 uint8_t not_used1 : 3; 228 uint8_t wu_dur_extended : 1; 229 uint8_t not_used0 : 4; 230 #endif /* DRV_BYTE_ORDER */ 231 } st1vafe3bx_wake_up_dur_ext_t; 232 233 #define ST1VAFE3BX_WHO_AM_I 0x0FU 234 typedef struct 235 { 236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 237 uint8_t id : 8; 238 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 239 uint8_t id : 8; 240 #endif /* DRV_BYTE_ORDER */ 241 } st1vafe3bx_who_am_i_t; 242 243 #define ST1VAFE3BX_CTRL1 0x10U 244 typedef struct 245 { 246 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 247 uint8_t wu_z_en : 1; 248 uint8_t wu_y_en : 1; 249 uint8_t wu_x_en : 1; 250 uint8_t drdy_pulsed : 1; 251 uint8_t if_add_inc : 1; 252 uint8_t sw_reset : 1; 253 uint8_t int_pin_en : 1; 254 uint8_t smart_power_en : 1; 255 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 256 uint8_t smart_power_en : 1; 257 uint8_t int_pin_en : 1; 258 uint8_t sw_reset : 1; 259 uint8_t if_add_inc : 1; 260 uint8_t drdy_pulsed : 1; 261 uint8_t wu_x_en : 1; 262 uint8_t wu_y_en : 1; 263 uint8_t wu_z_en : 1; 264 #endif /* DRV_BYTE_ORDER */ 265 } st1vafe3bx_ctrl1_t; 266 267 #define ST1VAFE3BX_CTRL2 0x11U 268 typedef struct 269 { 270 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 271 uint8_t not_used0 : 3; 272 uint8_t int_drdy : 1; 273 uint8_t int_fifo_ovr : 1; 274 uint8_t int_fifo_th : 1; 275 uint8_t int_fifo_full : 1; 276 uint8_t int_boot : 1; 277 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 278 uint8_t int_boot : 1; 279 uint8_t int_fifo_full : 1; 280 uint8_t int_fifo_th : 1; 281 uint8_t int_fifo_ovr : 1; 282 uint8_t int_drdy : 1; 283 uint8_t not_used0 : 3; 284 #endif /* DRV_BYTE_ORDER */ 285 } st1vafe3bx_ctrl2_t; 286 287 #define ST1VAFE3BX_CTRL3 0x12U 288 typedef struct 289 { 290 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 291 uint8_t st_sign_x : 1; 292 uint8_t st_sign_y : 1; 293 uint8_t hp_en : 1; 294 uint8_t not_used0 : 5; 295 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 296 uint8_t not_used0 : 5; 297 uint8_t hp_en : 1; 298 uint8_t st_sign_y : 1; 299 uint8_t st_sign_x : 1; 300 #endif /* DRV_BYTE_ORDER */ 301 } st1vafe3bx_ctrl3_t; 302 303 #define ST1VAFE3BX_CTRL4 0x13U 304 typedef struct 305 { 306 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 307 uint8_t boot : 1; 308 uint8_t soc : 1; 309 uint8_t not_used0 : 1; 310 uint8_t fifo_en : 1; 311 uint8_t emb_func_en : 1; 312 uint8_t bdu : 1; 313 uint8_t inact_odr : 2; 314 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 315 uint8_t inact_odr : 2; 316 uint8_t bdu : 1; 317 uint8_t emb_func_en : 1; 318 uint8_t fifo_en : 1; 319 uint8_t not_used0 : 1; 320 uint8_t soc : 1; 321 uint8_t boot : 1; 322 #endif /* DRV_BYTE_ORDER */ 323 } st1vafe3bx_ctrl4_t; 324 325 #define ST1VAFE3BX_CTRL5 0x14U 326 typedef struct 327 { 328 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 329 uint8_t fs : 2; 330 uint8_t bw : 2; 331 uint8_t odr : 4; 332 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 333 uint8_t odr : 4; 334 uint8_t bw : 2; 335 uint8_t fs : 2; 336 #endif /* DRV_BYTE_ORDER */ 337 } st1vafe3bx_ctrl5_t; 338 339 #define ST1VAFE3BX_FIFO_CTRL 0x15U 340 typedef struct 341 { 342 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 343 uint8_t fifo_mode : 3; 344 uint8_t stop_on_fth : 1; 345 uint8_t fifo_en_adv : 1; 346 uint8_t not_used0 : 1; 347 uint8_t fifo_depth : 1; 348 uint8_t cfg_chg_en : 1; 349 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 350 uint8_t cfg_chg_en : 1; 351 uint8_t fifo_depth : 1; 352 uint8_t not_used0 : 1; 353 uint8_t fifo_en_adv : 1; 354 uint8_t stop_on_fth : 1; 355 uint8_t fifo_mode : 3; 356 #endif /* DRV_BYTE_ORDER */ 357 } st1vafe3bx_fifo_ctrl_t; 358 359 #define ST1VAFE3BX_FIFO_WTM 0x16U 360 typedef struct 361 { 362 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 363 uint8_t fth : 7; 364 uint8_t xl_only_fifo : 1; 365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 366 uint8_t xl_only_fifo : 1; 367 uint8_t fth : 7; 368 #endif /* DRV_BYTE_ORDER */ 369 } st1vafe3bx_fifo_wtm_t; 370 371 #define ST1VAFE3BX_INTERRUPT_CFG 0x17U 372 typedef struct 373 { 374 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 375 uint8_t interrupts_enable : 1; 376 uint8_t lir : 1; 377 uint8_t dis_rst_lir_all_int : 1; 378 uint8_t sleep_status_on_int : 1; 379 uint8_t not_used0 : 1; 380 uint8_t wake_ths_w : 1; 381 uint8_t not_used1 : 1; 382 uint8_t timestamp_en : 1; 383 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 384 uint8_t timestamp_en : 1; 385 uint8_t not_used1 : 1; 386 uint8_t wake_ths_w : 1; 387 uint8_t not_used0 : 1; 388 uint8_t sleep_status_on_int : 1; 389 uint8_t dis_rst_lir_all_int : 1; 390 uint8_t lir : 1; 391 uint8_t interrupts_enable : 1; 392 #endif /* DRV_BYTE_ORDER */ 393 } st1vafe3bx_interrupt_cfg_t; 394 395 #define ST1VAFE3BX_SIXD 0x18U 396 typedef struct 397 { 398 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 399 uint8_t not_used0 : 5; 400 uint8_t d6d_ths : 2; 401 uint8_t d4d_en : 1; 402 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 403 uint8_t d4d_en : 1; 404 uint8_t d6d_ths : 2; 405 uint8_t not_used0 : 5; 406 #endif /* DRV_BYTE_ORDER */ 407 } st1vafe3bx_sixd_t; 408 409 #define ST1VAFE3BX_WAKE_UP_THS 0x1CU 410 typedef struct 411 { 412 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 413 uint8_t wk_ths : 6; 414 uint8_t sleep_on : 1; 415 uint8_t not_used0 : 1; 416 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 417 uint8_t not_used0 : 1; 418 uint8_t sleep_on : 1; 419 uint8_t wk_ths : 6; 420 #endif /* DRV_BYTE_ORDER */ 421 } st1vafe3bx_wake_up_ths_t; 422 423 #define ST1VAFE3BX_WAKE_UP_DUR 0x1DU 424 typedef struct 425 { 426 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 427 uint8_t sleep_dur : 4; 428 uint8_t st_sign_z : 1; 429 uint8_t wake_dur : 2; 430 uint8_t ff_dur : 1; 431 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 432 uint8_t ff_dur : 1; 433 uint8_t wake_dur : 2; 434 uint8_t st_sign_z : 1; 435 uint8_t sleep_dur : 4; 436 #endif /* DRV_BYTE_ORDER */ 437 } st1vafe3bx_wake_up_dur_t; 438 439 #define ST1VAFE3BX_FREE_FALL 0x1EU 440 typedef struct 441 { 442 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 443 uint8_t ff_ths : 3; 444 uint8_t ff_dur : 5; 445 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 446 uint8_t ff_dur : 5; 447 uint8_t ff_ths : 3; 448 #endif /* DRV_BYTE_ORDER */ 449 } st1vafe3bx_free_fall_t; 450 451 #define ST1VAFE3BX_MD1_CFG 0x1FU 452 typedef struct 453 { 454 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 455 uint8_t int_emb_func : 1; 456 uint8_t int_timestamp : 1; 457 uint8_t int_6d : 1; 458 uint8_t int_tap : 1; 459 uint8_t int_ff : 1; 460 uint8_t int_wu : 1; 461 uint8_t not_used0 : 1; 462 uint8_t int_sleep_change : 1; 463 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 464 uint8_t int_sleep_change : 1; 465 uint8_t not_used0 : 1; 466 uint8_t int_wu : 1; 467 uint8_t int_ff : 1; 468 uint8_t int_tap : 1; 469 uint8_t int_6d : 1; 470 uint8_t int_timestamp : 1; 471 uint8_t int_emb_func : 1; 472 #endif /* DRV_BYTE_ORDER */ 473 } st1vafe3bx_md1_cfg_t; 474 475 #define ST1VAFE3BX_WAKE_UP_SRC 0x21U 476 typedef struct 477 { 478 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 479 uint8_t z_wu : 1; 480 uint8_t y_wu : 1; 481 uint8_t x_wu : 1; 482 uint8_t wu_ia : 1; 483 uint8_t sleep_state : 1; 484 uint8_t ff_ia : 1; 485 uint8_t sleep_change_ia : 1; 486 uint8_t not_used0 : 1; 487 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 488 uint8_t not_used0 : 1; 489 uint8_t sleep_change_ia : 1; 490 uint8_t ff_ia : 1; 491 uint8_t sleep_state : 1; 492 uint8_t wu_ia : 1; 493 uint8_t x_wu : 1; 494 uint8_t y_wu : 1; 495 uint8_t z_wu : 1; 496 #endif /* DRV_BYTE_ORDER */ 497 } st1vafe3bx_wake_up_src_t; 498 499 #define ST1VAFE3BX_TAP_SRC 0x22U 500 typedef struct 501 { 502 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 503 uint8_t not_used0 : 4; 504 uint8_t triple_tap_ia : 1; 505 uint8_t double_tap_ia : 1; 506 uint8_t single_tap_ia : 1; 507 uint8_t tap_ia : 1; 508 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 509 uint8_t tap_ia : 1; 510 uint8_t single_tap_ia : 1; 511 uint8_t double_tap_ia : 1; 512 uint8_t triple_tap_ia : 1; 513 uint8_t not_used0 : 4; 514 #endif /* DRV_BYTE_ORDER */ 515 } st1vafe3bx_tap_src_t; 516 517 #define ST1VAFE3BX_SIXD_SRC 0x23U 518 typedef struct 519 { 520 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 521 uint8_t xl : 1; 522 uint8_t xh : 1; 523 uint8_t yl : 1; 524 uint8_t yh : 1; 525 uint8_t zl : 1; 526 uint8_t zh : 1; 527 uint8_t d6d_ia : 1; 528 uint8_t not_used0 : 1; 529 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 530 uint8_t not_used0 : 1; 531 uint8_t d6d_ia : 1; 532 uint8_t zh : 1; 533 uint8_t zl : 1; 534 uint8_t yh : 1; 535 uint8_t yl : 1; 536 uint8_t xh : 1; 537 uint8_t xl : 1; 538 #endif /* DRV_BYTE_ORDER */ 539 } st1vafe3bx_sixd_src_t; 540 541 #define ST1VAFE3BX_ALL_INT_SRC 0x24U 542 typedef struct 543 { 544 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 545 uint8_t ff_ia_all : 1; 546 uint8_t wu_ia_all : 1; 547 uint8_t single_tap_all : 1; 548 uint8_t double_tap_all : 1; 549 uint8_t triple_tap_all : 1; 550 uint8_t d6d_ia_all : 1; 551 uint8_t sleep_change_ia_all : 1; 552 uint8_t not_used0 : 1; 553 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 554 uint8_t not_used0 : 1; 555 uint8_t sleep_change_ia_all : 1; 556 uint8_t d6d_ia_all : 1; 557 uint8_t triple_tap_all : 1; 558 uint8_t double_tap_all : 1; 559 uint8_t single_tap_all : 1; 560 uint8_t wu_ia_all : 1; 561 uint8_t ff_ia_all : 1; 562 #endif /* DRV_BYTE_ORDER */ 563 } st1vafe3bx_all_int_src_t; 564 565 #define ST1VAFE3BX_STATUS 0x25U 566 typedef struct 567 { 568 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 569 uint8_t drdy : 1; 570 uint8_t not_used0 : 4; 571 uint8_t int_global : 1; 572 uint8_t not_used1 : 2; 573 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 574 uint8_t not_used1 : 2; 575 uint8_t int_global : 1; 576 uint8_t not_used0 : 4; 577 uint8_t drdy : 1; 578 #endif /* DRV_BYTE_ORDER */ 579 } st1vafe3bx_status_register_t; 580 581 #define ST1VAFE3BX_FIFO_STATUS1 0x26U 582 typedef struct 583 { 584 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 585 uint8_t not_used0 : 6; 586 uint8_t fifo_ovr_ia : 1; 587 uint8_t fifo_wtm_ia : 1; 588 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 589 uint8_t fifo_wtm_ia : 1; 590 uint8_t fifo_ovr_ia : 1; 591 uint8_t not_used0 : 6; 592 #endif /* DRV_BYTE_ORDER */ 593 } st1vafe3bx_fifo_status1_t; 594 595 #define ST1VAFE3BX_FIFO_STATUS2 0x27U 596 typedef struct 597 { 598 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 599 uint8_t fss : 8; 600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 601 uint8_t fss : 8; 602 #endif /* DRV_BYTE_ORDER */ 603 } st1vafe3bx_fifo_status2_t; 604 605 #define ST1VAFE3BX_OUT_X_L 0x28U 606 typedef struct 607 { 608 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 609 uint8_t outx : 8; 610 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 611 uint8_t outx : 8; 612 #endif /* DRV_BYTE_ORDER */ 613 } st1vafe3bx_out_x_l_t; 614 615 #define ST1VAFE3BX_OUT_X_H 0x29U 616 typedef struct 617 { 618 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 619 uint8_t outx : 8; 620 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 621 uint8_t outx : 8; 622 #endif /* DRV_BYTE_ORDER */ 623 } st1vafe3bx_out_x_h_t; 624 625 #define ST1VAFE3BX_OUT_Y_L 0x2AU 626 typedef struct 627 { 628 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 629 uint8_t outy : 8; 630 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 631 uint8_t outy : 8; 632 #endif /* DRV_BYTE_ORDER */ 633 } st1vafe3bx_out_y_l_t; 634 635 #define ST1VAFE3BX_OUT_Y_H 0x2BU 636 typedef struct 637 { 638 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 639 uint8_t outy : 8; 640 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 641 uint8_t outy : 8; 642 #endif /* DRV_BYTE_ORDER */ 643 } st1vafe3bx_out_y_h_t; 644 645 #define ST1VAFE3BX_OUT_Z_L 0x2CU 646 typedef struct 647 { 648 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 649 uint8_t outz : 8; 650 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 651 uint8_t outz : 8; 652 #endif /* DRV_BYTE_ORDER */ 653 } st1vafe3bx_out_z_l_t; 654 655 #define ST1VAFE3BX_OUT_Z_H 0x2DU 656 typedef struct 657 { 658 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 659 uint8_t outz : 8; 660 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 661 uint8_t outz : 8; 662 #endif /* DRV_BYTE_ORDER */ 663 } st1vafe3bx_out_z_h_t; 664 665 #define ST1VAFE3BX_OUT_AH_BIO_L 0x2EU 666 typedef struct 667 { 668 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 669 uint8_t out_ah_bio : 8; 670 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 671 uint8_t out_ah_bio : 8; 672 #endif /* DRV_BYTE_ORDER */ 673 } st1vafe3bx_out_ah_bio_l_t; 674 675 #define ST1VAFE3BX_OUT_AH_BIO_H 0x2FU 676 typedef struct 677 { 678 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 679 uint8_t out_ah_bio : 8; 680 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 681 uint8_t out_ah_bio : 8; 682 #endif /* DRV_BYTE_ORDER */ 683 } st1vafe3bx_out_ah_bio_h_t; 684 685 #define ST1VAFE3BX_AH_BIO_CFG1 0x30U 686 typedef struct 687 { 688 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 689 uint8_t not_used0 : 3; 690 uint8_t ah_bio_zin_dis_ah2_bio1 : 1; 691 uint8_t ah_bio_zin_dis_ah2_bio2 : 1; 692 uint8_t not_used1 : 3; 693 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 694 uint8_t not_used1 : 3; 695 uint8_t ah_bio_zin_dis_ah2_bio2 : 1; 696 uint8_t ah_bio_zin_dis_ah2_bio1 : 1; 697 uint8_t not_used0 : 3; 698 #endif /* DRV_BYTE_ORDER */ 699 } st1vafe3bx_ah_bio_cfg1_t; 700 701 #define ST1VAFE3BX_AH_BIO_CFG2 0x31U 702 typedef struct 703 { 704 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 705 uint8_t ah_bio_en : 1; 706 uint8_t ah_bio_gain : 2; 707 uint8_t ah_bio_c_zin : 2; 708 uint8_t ah_bio_mode : 2; 709 uint8_t not_used0 : 1; 710 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 711 uint8_t not_used0 : 1; 712 uint8_t ah_bio_mode : 2; 713 uint8_t ah_bio_c_zin : 2; 714 uint8_t ah_bio_gain : 2; 715 uint8_t ah_bio_en : 1; 716 #endif /* DRV_BYTE_ORDER */ 717 } st1vafe3bx_ah_bio_cfg2_t; 718 719 #define ST1VAFE3BX_AH_BIO_CFG3 0x32U 720 typedef struct 721 { 722 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 723 uint8_t ah_bio_active : 1; 724 uint8_t not_used0 : 3; 725 uint8_t st : 2; 726 uint8_t not_used1 : 2; 727 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 728 uint8_t not_used1 : 2; 729 uint8_t st : 2; 730 uint8_t not_used0 : 3; 731 uint8_t ah_bio_active : 1; 732 #endif /* DRV_BYTE_ORDER */ 733 } st1vafe3bx_ah_bio_cfg3_t; 734 735 #define ST1VAFE3BX_I3C_IF_CTRL 0x33U 736 typedef struct 737 { 738 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 739 uint8_t bus_act_sel : 2; 740 uint8_t not_used0 : 3; 741 uint8_t asf_on : 1; 742 uint8_t not_used1 : 1; 743 uint8_t dis_drstdaa : 1; 744 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 745 uint8_t dis_drstdaa : 1; 746 uint8_t not_used1 : 1; 747 uint8_t asf_on : 1; 748 uint8_t not_used0 : 3; 749 uint8_t bus_act_sel : 2; 750 #endif /* DRV_BYTE_ORDER */ 751 } st1vafe3bx_i3c_if_ctrl_t; 752 753 #define ST1VAFE3BX_EMB_FUNC_STATUS_MAINPAGE 0x34U 754 typedef struct 755 { 756 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 757 uint8_t not_used0 : 3; 758 uint8_t is_step_det : 1; 759 uint8_t is_tilt : 1; 760 uint8_t is_sigmot : 1; 761 uint8_t not_used1 : 1; 762 uint8_t is_fsm_lc : 1; 763 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 764 uint8_t is_fsm_lc : 1; 765 uint8_t not_used1 : 1; 766 uint8_t is_sigmot : 1; 767 uint8_t is_tilt : 1; 768 uint8_t is_step_det : 1; 769 uint8_t not_used0 : 3; 770 #endif /* DRV_BYTE_ORDER */ 771 } st1vafe3bx_emb_func_status_mainpage_t; 772 773 #define ST1VAFE3BX_FSM_STATUS_MAINPAGE 0x35U 774 typedef struct 775 { 776 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 777 uint8_t is_fsm1 : 1; 778 uint8_t is_fsm2 : 1; 779 uint8_t is_fsm3 : 1; 780 uint8_t is_fsm4 : 1; 781 uint8_t is_fsm5 : 1; 782 uint8_t is_fsm6 : 1; 783 uint8_t is_fsm7 : 1; 784 uint8_t is_fsm8 : 1; 785 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 786 uint8_t is_fsm8 : 1; 787 uint8_t is_fsm7 : 1; 788 uint8_t is_fsm6 : 1; 789 uint8_t is_fsm5 : 1; 790 uint8_t is_fsm4 : 1; 791 uint8_t is_fsm3 : 1; 792 uint8_t is_fsm2 : 1; 793 uint8_t is_fsm1 : 1; 794 #endif /* DRV_BYTE_ORDER */ 795 } st1vafe3bx_fsm_status_mainpage_t; 796 797 #define ST1VAFE3BX_MLC_STATUS_MAINPAGE 0x36U 798 typedef struct 799 { 800 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 801 uint8_t is_mlc1 : 1; 802 uint8_t is_mlc2 : 1; 803 uint8_t is_mlc3 : 1; 804 uint8_t is_mlc4 : 1; 805 uint8_t not_used0 : 4; 806 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 807 uint8_t not_used0 : 4; 808 uint8_t is_mlc4 : 1; 809 uint8_t is_mlc3 : 1; 810 uint8_t is_mlc2 : 1; 811 uint8_t is_mlc1 : 1; 812 #endif /* DRV_BYTE_ORDER */ 813 } st1vafe3bx_mlc_status_mainpage_t; 814 815 #define ST1VAFE3BX_EN_DEVICE_CONFIG 0x3EU 816 typedef struct 817 { 818 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 819 uint8_t en_dev_conf : 1; 820 uint8_t not_used0 : 7; 821 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 822 uint8_t not_used0 : 7; 823 uint8_t en_dev_conf : 1; 824 #endif /* DRV_BYTE_ORDER */ 825 } st1vafe3bx_en_device_config_t; 826 827 #define ST1VAFE3BX_FUNC_CFG_ACCESS 0x3FU 828 typedef struct 829 { 830 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 831 uint8_t fsm_wr_ctrl_en : 1; 832 uint8_t not_used0 : 6; 833 uint8_t emb_func_reg_access : 1; 834 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 835 uint8_t emb_func_reg_access : 1; 836 uint8_t not_used0 : 6; 837 uint8_t fsm_wr_ctrl_en : 1; 838 #endif /* DRV_BYTE_ORDER */ 839 } st1vafe3bx_func_cfg_access_t; 840 841 #define ST1VAFE3BX_FIFO_DATA_OUT_TAG 0x40U 842 typedef struct 843 { 844 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 845 uint8_t not_used0 : 3; 846 uint8_t tag_sensor : 5; 847 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 848 uint8_t tag_sensor : 5; 849 uint8_t not_used0 : 3; 850 #endif /* DRV_BYTE_ORDER */ 851 } st1vafe3bx_fifo_data_out_tag_t; 852 853 #define ST1VAFE3BX_FIFO_DATA_OUT_X_L 0x41U 854 typedef struct 855 { 856 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 857 uint8_t fifo_data_out : 8; 858 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 859 uint8_t fifo_data_out : 8; 860 #endif /* DRV_BYTE_ORDER */ 861 } st1vafe3bx_fifo_data_out_x_l_t; 862 863 #define ST1VAFE3BX_FIFO_DATA_OUT_X_H 0x42U 864 typedef struct 865 { 866 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 867 uint8_t fifo_data_out : 8; 868 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 869 uint8_t fifo_data_out : 8; 870 #endif /* DRV_BYTE_ORDER */ 871 } st1vafe3bx_fifo_data_out_x_h_t; 872 873 #define ST1VAFE3BX_FIFO_DATA_OUT_Y_L 0x43U 874 typedef struct 875 { 876 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 877 uint8_t fifo_data_out : 8; 878 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 879 uint8_t fifo_data_out : 8; 880 #endif /* DRV_BYTE_ORDER */ 881 } st1vafe3bx_fifo_data_out_y_l_t; 882 883 #define ST1VAFE3BX_FIFO_DATA_OUT_Y_H 0x44U 884 typedef struct 885 { 886 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 887 uint8_t fifo_data_out : 8; 888 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 889 uint8_t fifo_data_out : 8; 890 #endif /* DRV_BYTE_ORDER */ 891 } st1vafe3bx_fifo_data_out_y_h_t; 892 893 #define ST1VAFE3BX_FIFO_DATA_OUT_Z_L 0x45U 894 typedef struct 895 { 896 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 897 uint8_t fifo_data_out : 8; 898 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 899 uint8_t fifo_data_out : 8; 900 #endif /* DRV_BYTE_ORDER */ 901 } st1vafe3bx_fifo_data_out_z_l_t; 902 903 #define ST1VAFE3BX_FIFO_DATA_OUT_Z_H 0x46U 904 typedef struct 905 { 906 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 907 uint8_t fifo_data_out : 8; 908 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 909 uint8_t fifo_data_out : 8; 910 #endif /* DRV_BYTE_ORDER */ 911 } st1vafe3bx_fifo_data_out_z_h_t; 912 913 #define ST1VAFE3BX_FIFO_BATCH_DEC 0x47U 914 typedef struct 915 { 916 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 917 uint8_t bdr_xl : 3; 918 uint8_t dec_ts_batch : 2; 919 uint8_t not_used0 : 3; 920 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 921 uint8_t not_used0 : 3; 922 uint8_t dec_ts_batch : 2; 923 uint8_t bdr_xl : 3; 924 #endif /* DRV_BYTE_ORDER */ 925 } st1vafe3bx_fifo_batch_dec_t; 926 927 #define ST1VAFE3BX_TAP_CFG0 0x6FU 928 typedef struct 929 { 930 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 931 uint8_t not_used0 : 1; 932 uint8_t invert_t : 5; 933 uint8_t axis : 2; 934 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 935 uint8_t axis : 2; 936 uint8_t invert_t : 5; 937 uint8_t not_used0 : 1; 938 #endif /* DRV_BYTE_ORDER */ 939 } st1vafe3bx_tap_cfg0_t; 940 941 #define ST1VAFE3BX_TAP_CFG1 0x70U 942 typedef struct 943 { 944 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 945 uint8_t post_still_t : 4; 946 uint8_t pre_still_ths : 4; 947 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 948 uint8_t pre_still_ths : 4; 949 uint8_t post_still_t : 4; 950 #endif /* DRV_BYTE_ORDER */ 951 } st1vafe3bx_tap_cfg1_t; 952 953 #define ST1VAFE3BX_TAP_CFG2 0x71U 954 typedef struct 955 { 956 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 957 uint8_t wait_t : 6; 958 uint8_t post_still_t : 2; 959 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 960 uint8_t post_still_t : 2; 961 uint8_t wait_t : 6; 962 #endif /* DRV_BYTE_ORDER */ 963 } st1vafe3bx_tap_cfg2_t; 964 965 #define ST1VAFE3BX_TAP_CFG3 0x72U 966 typedef struct 967 { 968 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 969 uint8_t latency_t : 4; 970 uint8_t post_still_ths : 4; 971 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 972 uint8_t post_still_ths : 4; 973 uint8_t latency_t : 4; 974 #endif /* DRV_BYTE_ORDER */ 975 } st1vafe3bx_tap_cfg3_t; 976 977 #define ST1VAFE3BX_TAP_CFG4 0x73U 978 typedef struct 979 { 980 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 981 uint8_t peak_ths : 6; 982 uint8_t not_used0 : 1; 983 uint8_t wait_end_latency : 1; 984 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 985 uint8_t wait_end_latency : 1; 986 uint8_t not_used0 : 1; 987 uint8_t peak_ths : 6; 988 #endif /* DRV_BYTE_ORDER */ 989 } st1vafe3bx_tap_cfg4_t; 990 991 #define ST1VAFE3BX_TAP_CFG5 0x74U 992 typedef struct 993 { 994 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 995 uint8_t rebound_t : 5; 996 uint8_t single_tap_en : 1; 997 uint8_t double_tap_en : 1; 998 uint8_t triple_tap_en : 1; 999 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1000 uint8_t triple_tap_en : 1; 1001 uint8_t double_tap_en : 1; 1002 uint8_t single_tap_en : 1; 1003 uint8_t rebound_t : 5; 1004 #endif /* DRV_BYTE_ORDER */ 1005 } st1vafe3bx_tap_cfg5_t; 1006 1007 #define ST1VAFE3BX_TAP_CFG6 0x75U 1008 typedef struct 1009 { 1010 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1011 uint8_t pre_still_n : 4; 1012 uint8_t pre_still_st : 4; 1013 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1014 uint8_t pre_still_st : 4; 1015 uint8_t pre_still_n : 4; 1016 #endif /* DRV_BYTE_ORDER */ 1017 } st1vafe3bx_tap_cfg6_t; 1018 1019 #define ST1VAFE3BX_TIMESTAMP0 0x7AU 1020 typedef struct 1021 { 1022 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1023 uint8_t timestamp : 8; 1024 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1025 uint8_t timestamp : 8; 1026 #endif /* DRV_BYTE_ORDER */ 1027 } st1vafe3bx_timestamp0_t; 1028 1029 #define ST1VAFE3BX_TIMESTAMP1 0x7BU 1030 typedef struct 1031 { 1032 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1033 uint8_t timestamp : 8; 1034 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1035 uint8_t timestamp : 8; 1036 #endif /* DRV_BYTE_ORDER */ 1037 } st1vafe3bx_timestamp1_t; 1038 1039 #define ST1VAFE3BX_TIMESTAMP2 0x7CU 1040 typedef struct 1041 { 1042 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1043 uint8_t timestamp : 8; 1044 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1045 uint8_t timestamp : 8; 1046 #endif /* DRV_BYTE_ORDER */ 1047 } st1vafe3bx_timestamp2_t; 1048 1049 #define ST1VAFE3BX_TIMESTAMP3 0x7DU 1050 typedef struct 1051 { 1052 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1053 uint8_t timestamp : 8; 1054 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1055 uint8_t timestamp : 8; 1056 #endif /* DRV_BYTE_ORDER */ 1057 } st1vafe3bx_timestamp3_t; 1058 1059 /** 1060 * @} 1061 * 1062 */ 1063 1064 /** @defgroup bitfields page embedded 1065 * @{ 1066 * 1067 */ 1068 1069 #define ST1VAFE3BX_PAGE_SEL 0x2U 1070 typedef struct 1071 { 1072 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1073 uint8_t not_used0 : 4; 1074 uint8_t page_sel : 4; 1075 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1076 uint8_t page_sel : 4; 1077 uint8_t not_used0 : 4; 1078 #endif /* DRV_BYTE_ORDER */ 1079 } st1vafe3bx_page_sel_t; 1080 1081 #define ST1VAFE3BX_EMB_FUNC_EN_A 0x4U 1082 typedef struct 1083 { 1084 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1085 uint8_t not_used0 : 3; 1086 uint8_t pedo_en : 1; 1087 uint8_t tilt_en : 1; 1088 uint8_t sign_motion_en : 1; 1089 uint8_t not_used1 : 1; 1090 uint8_t mlc_before_fsm_en : 1; 1091 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1092 uint8_t mlc_before_fsm_en : 1; 1093 uint8_t not_used1 : 1; 1094 uint8_t sign_motion_en : 1; 1095 uint8_t tilt_en : 1; 1096 uint8_t pedo_en : 1; 1097 uint8_t not_used0 : 3; 1098 #endif /* DRV_BYTE_ORDER */ 1099 } st1vafe3bx_emb_func_en_a_t; 1100 1101 #define ST1VAFE3BX_EMB_FUNC_EN_B 0x5U 1102 typedef struct 1103 { 1104 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1105 uint8_t fsm_en : 1; 1106 uint8_t not_used0 : 3; 1107 uint8_t mlc_en : 1; 1108 uint8_t not_used1 : 3; 1109 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1110 uint8_t not_used1 : 3; 1111 uint8_t mlc_en : 1; 1112 uint8_t not_used0 : 3; 1113 uint8_t fsm_en : 1; 1114 #endif /* DRV_BYTE_ORDER */ 1115 } st1vafe3bx_emb_func_en_b_t; 1116 1117 #define ST1VAFE3BX_EMB_FUNC_EXEC_STATUS 0x7U 1118 typedef struct 1119 { 1120 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1121 uint8_t emb_func_endop : 1; 1122 uint8_t emb_func_exec_ovr : 1; 1123 uint8_t not_used0 : 6; 1124 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1125 uint8_t not_used0 : 6; 1126 uint8_t emb_func_exec_ovr : 1; 1127 uint8_t emb_func_endop : 1; 1128 #endif /* DRV_BYTE_ORDER */ 1129 } st1vafe3bx_emb_func_exec_status_t; 1130 1131 #define ST1VAFE3BX_PAGE_ADDRESS 0x8U 1132 typedef struct 1133 { 1134 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1135 uint8_t page_addr : 8; 1136 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1137 uint8_t page_addr : 8; 1138 #endif /* DRV_BYTE_ORDER */ 1139 } st1vafe3bx_page_address_t; 1140 1141 #define ST1VAFE3BX_PAGE_VALUE 0x9U 1142 typedef struct 1143 { 1144 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1145 uint8_t page_value : 8; 1146 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1147 uint8_t page_value : 8; 1148 #endif /* DRV_BYTE_ORDER */ 1149 } st1vafe3bx_page_value_t; 1150 1151 #define ST1VAFE3BX_EMB_FUNC_INT 0x0AU 1152 typedef struct 1153 { 1154 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1155 uint8_t not_used0 : 3; 1156 uint8_t int_step_det : 1; 1157 uint8_t int_tilt : 1; 1158 uint8_t int_sig_mot : 1; 1159 uint8_t not_used1 : 1; 1160 uint8_t int_fsm_lc : 1; 1161 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1162 uint8_t int_fsm_lc : 1; 1163 uint8_t not_used1 : 1; 1164 uint8_t int_sig_mot : 1; 1165 uint8_t int_tilt : 1; 1166 uint8_t int_step_det : 1; 1167 uint8_t not_used0 : 3; 1168 #endif /* DRV_BYTE_ORDER */ 1169 } st1vafe3bx_emb_func_int_t; 1170 1171 #define ST1VAFE3BX_FSM_INT 0x0BU 1172 typedef struct 1173 { 1174 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1175 uint8_t int_fsm1 : 1; 1176 uint8_t int_fsm2 : 1; 1177 uint8_t int_fsm3 : 1; 1178 uint8_t int_fsm4 : 1; 1179 uint8_t int_fsm5 : 1; 1180 uint8_t int_fsm6 : 1; 1181 uint8_t int_fsm7 : 1; 1182 uint8_t int_fsm8 : 1; 1183 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1184 uint8_t int_fsm8 : 1; 1185 uint8_t int_fsm7 : 1; 1186 uint8_t int_fsm6 : 1; 1187 uint8_t int_fsm5 : 1; 1188 uint8_t int_fsm4 : 1; 1189 uint8_t int_fsm3 : 1; 1190 uint8_t int_fsm2 : 1; 1191 uint8_t int_fsm1 : 1; 1192 #endif /* DRV_BYTE_ORDER */ 1193 } st1vafe3bx_fsm_int_t; 1194 1195 #define ST1VAFE3BX_MLC_INT 0x0DU 1196 typedef struct 1197 { 1198 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1199 uint8_t int_mlc1 : 1; 1200 uint8_t int_mlc2 : 1; 1201 uint8_t int_mlc3 : 1; 1202 uint8_t int_mlc4 : 1; 1203 uint8_t not_used0 : 4; 1204 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1205 uint8_t not_used0 : 4; 1206 uint8_t int_mlc4 : 1; 1207 uint8_t int_mlc3 : 1; 1208 uint8_t int_mlc2 : 1; 1209 uint8_t int_mlc1 : 1; 1210 #endif /* DRV_BYTE_ORDER */ 1211 } st1vafe3bx_mlc_int_t; 1212 1213 #define ST1VAFE3BX_EMB_FUNC_STATUS 0x12U 1214 typedef struct 1215 { 1216 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1217 uint8_t not_used0 : 3; 1218 uint8_t is_step_det : 1; 1219 uint8_t is_tilt : 1; 1220 uint8_t is_sigmot : 1; 1221 uint8_t not_used1 : 1; 1222 uint8_t is_fsm_lc : 1; 1223 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1224 uint8_t is_fsm_lc : 1; 1225 uint8_t not_used1 : 1; 1226 uint8_t is_sigmot : 1; 1227 uint8_t is_tilt : 1; 1228 uint8_t is_step_det : 1; 1229 uint8_t not_used0 : 3; 1230 #endif /* DRV_BYTE_ORDER */ 1231 } st1vafe3bx_emb_func_status_t; 1232 1233 #define ST1VAFE3BX_FSM_STATUS 0x13U 1234 typedef struct 1235 { 1236 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1237 uint8_t is_fsm1 : 1; 1238 uint8_t is_fsm2 : 1; 1239 uint8_t is_fsm3 : 1; 1240 uint8_t is_fsm4 : 1; 1241 uint8_t is_fsm5 : 1; 1242 uint8_t is_fsm6 : 1; 1243 uint8_t is_fsm7 : 1; 1244 uint8_t is_fsm8 : 1; 1245 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1246 uint8_t is_fsm8 : 1; 1247 uint8_t is_fsm7 : 1; 1248 uint8_t is_fsm6 : 1; 1249 uint8_t is_fsm5 : 1; 1250 uint8_t is_fsm4 : 1; 1251 uint8_t is_fsm3 : 1; 1252 uint8_t is_fsm2 : 1; 1253 uint8_t is_fsm1 : 1; 1254 #endif /* DRV_BYTE_ORDER */ 1255 } st1vafe3bx_fsm_status_t; 1256 1257 #define ST1VAFE3BX_MLC_STATUS 0x15U 1258 typedef struct 1259 { 1260 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1261 uint8_t is_mlc1 : 1; 1262 uint8_t is_mlc2 : 1; 1263 uint8_t is_mlc3 : 1; 1264 uint8_t is_mlc4 : 1; 1265 uint8_t not_used0 : 4; 1266 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1267 uint8_t not_used0 : 4; 1268 uint8_t is_mlc4 : 1; 1269 uint8_t is_mlc3 : 1; 1270 uint8_t is_mlc2 : 1; 1271 uint8_t is_mlc1 : 1; 1272 #endif /* DRV_BYTE_ORDER */ 1273 } st1vafe3bx_mlc_status_t; 1274 1275 #define ST1VAFE3BX_PAGE_RW 0x17U 1276 typedef struct 1277 { 1278 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1279 uint8_t not_used0 : 5; 1280 uint8_t page_read : 1; 1281 uint8_t page_write : 1; 1282 uint8_t emb_func_lir : 1; 1283 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1284 uint8_t emb_func_lir : 1; 1285 uint8_t page_write : 1; 1286 uint8_t page_read : 1; 1287 uint8_t not_used0 : 5; 1288 #endif /* DRV_BYTE_ORDER */ 1289 } st1vafe3bx_page_rw_t; 1290 1291 #define ST1VAFE3BX_EMB_FUNC_FIFO_EN 0x18U 1292 typedef struct 1293 { 1294 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1295 uint8_t step_counter_fifo_en : 1; 1296 uint8_t mlc_fifo_en : 1; 1297 uint8_t mlc_filter_feature_fifo_en : 1; 1298 uint8_t fsm_fifo_en : 1; 1299 uint8_t not_used0 : 4; 1300 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1301 uint8_t not_used0 : 4; 1302 uint8_t fsm_fifo_en : 1; 1303 uint8_t mlc_filter_feature_fifo_en : 1; 1304 uint8_t mlc_fifo_en : 1; 1305 uint8_t step_counter_fifo_en : 1; 1306 #endif /* DRV_BYTE_ORDER */ 1307 } st1vafe3bx_emb_func_fifo_en_t; 1308 1309 #define ST1VAFE3BX_FSM_ENABLE 0x1AU 1310 typedef struct 1311 { 1312 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1313 uint8_t fsm1_en : 1; 1314 uint8_t fsm2_en : 1; 1315 uint8_t fsm3_en : 1; 1316 uint8_t fsm4_en : 1; 1317 uint8_t fsm5_en : 1; 1318 uint8_t fsm6_en : 1; 1319 uint8_t fsm7_en : 1; 1320 uint8_t fsm8_en : 1; 1321 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1322 uint8_t fsm8_en : 1; 1323 uint8_t fsm7_en : 1; 1324 uint8_t fsm6_en : 1; 1325 uint8_t fsm5_en : 1; 1326 uint8_t fsm4_en : 1; 1327 uint8_t fsm3_en : 1; 1328 uint8_t fsm2_en : 1; 1329 uint8_t fsm1_en : 1; 1330 #endif /* DRV_BYTE_ORDER */ 1331 } st1vafe3bx_fsm_enable_t; 1332 1333 #define ST1VAFE3BX_FSM_LONG_COUNTER_L 0x1CU 1334 typedef struct 1335 { 1336 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1337 uint8_t fsm_lc : 8; 1338 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1339 uint8_t fsm_lc : 8; 1340 #endif /* DRV_BYTE_ORDER */ 1341 } st1vafe3bx_fsm_long_counter_l_t; 1342 1343 #define ST1VAFE3BX_FSM_LONG_COUNTER_H 0x1DU 1344 typedef struct 1345 { 1346 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1347 uint8_t fsm_lc : 8; 1348 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1349 uint8_t fsm_lc : 8; 1350 #endif /* DRV_BYTE_ORDER */ 1351 } st1vafe3bx_fsm_long_counter_h_t; 1352 1353 #define ST1VAFE3BX_INT_ACK_MASK 0x1FU 1354 typedef struct 1355 { 1356 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1357 uint8_t iack_mask0 : 1; 1358 uint8_t iack_mask1 : 1; 1359 uint8_t iack_mask2 : 1; 1360 uint8_t iack_mask3 : 1; 1361 uint8_t iack_mask4 : 1; 1362 uint8_t iack_mask5 : 1; 1363 uint8_t iack_mask6 : 1; 1364 uint8_t iack_mask7 : 1; 1365 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1366 uint8_t iack_mask7 : 1; 1367 uint8_t iack_mask6 : 1; 1368 uint8_t iack_mask5 : 1; 1369 uint8_t iack_mask4 : 1; 1370 uint8_t iack_mask3 : 1; 1371 uint8_t iack_mask2 : 1; 1372 uint8_t iack_mask1 : 1; 1373 uint8_t iack_mask0 : 1; 1374 #endif /* DRV_BYTE_ORDER */ 1375 } st1vafe3bx_int_ack_mask_t; 1376 1377 #define ST1VAFE3BX_FSM_OUTS1 0x20U 1378 typedef struct 1379 { 1380 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1381 uint8_t n_v : 1; 1382 uint8_t p_v : 1; 1383 uint8_t n_z : 1; 1384 uint8_t p_z : 1; 1385 uint8_t n_y : 1; 1386 uint8_t p_y : 1; 1387 uint8_t n_x : 1; 1388 uint8_t p_x : 1; 1389 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1390 uint8_t p_x : 1; 1391 uint8_t n_x : 1; 1392 uint8_t p_y : 1; 1393 uint8_t n_y : 1; 1394 uint8_t p_z : 1; 1395 uint8_t n_z : 1; 1396 uint8_t p_v : 1; 1397 uint8_t n_v : 1; 1398 #endif /* DRV_BYTE_ORDER */ 1399 } st1vafe3bx_fsm_outs1_t; 1400 1401 #define ST1VAFE3BX_FSM_OUTS2 0x21U 1402 typedef struct 1403 { 1404 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1405 uint8_t n_v : 1; 1406 uint8_t p_v : 1; 1407 uint8_t n_z : 1; 1408 uint8_t p_z : 1; 1409 uint8_t n_y : 1; 1410 uint8_t p_y : 1; 1411 uint8_t n_x : 1; 1412 uint8_t p_x : 1; 1413 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1414 uint8_t p_x : 1; 1415 uint8_t n_x : 1; 1416 uint8_t p_y : 1; 1417 uint8_t n_y : 1; 1418 uint8_t p_z : 1; 1419 uint8_t n_z : 1; 1420 uint8_t p_v : 1; 1421 uint8_t n_v : 1; 1422 #endif /* DRV_BYTE_ORDER */ 1423 } st1vafe3bx_fsm_outs2_t; 1424 1425 #define ST1VAFE3BX_FSM_OUTS3 0x22U 1426 typedef struct 1427 { 1428 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1429 uint8_t n_v : 1; 1430 uint8_t p_v : 1; 1431 uint8_t n_z : 1; 1432 uint8_t p_z : 1; 1433 uint8_t n_y : 1; 1434 uint8_t p_y : 1; 1435 uint8_t n_x : 1; 1436 uint8_t p_x : 1; 1437 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1438 uint8_t p_x : 1; 1439 uint8_t n_x : 1; 1440 uint8_t p_y : 1; 1441 uint8_t n_y : 1; 1442 uint8_t p_z : 1; 1443 uint8_t n_z : 1; 1444 uint8_t p_v : 1; 1445 uint8_t n_v : 1; 1446 #endif /* DRV_BYTE_ORDER */ 1447 } st1vafe3bx_fsm_outs3_t; 1448 1449 #define ST1VAFE3BX_FSM_OUTS4 0x23U 1450 typedef struct 1451 { 1452 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1453 uint8_t n_v : 1; 1454 uint8_t p_v : 1; 1455 uint8_t n_z : 1; 1456 uint8_t p_z : 1; 1457 uint8_t n_y : 1; 1458 uint8_t p_y : 1; 1459 uint8_t n_x : 1; 1460 uint8_t p_x : 1; 1461 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1462 uint8_t p_x : 1; 1463 uint8_t n_x : 1; 1464 uint8_t p_y : 1; 1465 uint8_t n_y : 1; 1466 uint8_t p_z : 1; 1467 uint8_t n_z : 1; 1468 uint8_t p_v : 1; 1469 uint8_t n_v : 1; 1470 #endif /* DRV_BYTE_ORDER */ 1471 } st1vafe3bx_fsm_outs4_t; 1472 1473 #define ST1VAFE3BX_FSM_OUTS5 0x24U 1474 typedef struct 1475 { 1476 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1477 uint8_t n_v : 1; 1478 uint8_t p_v : 1; 1479 uint8_t n_z : 1; 1480 uint8_t p_z : 1; 1481 uint8_t n_y : 1; 1482 uint8_t p_y : 1; 1483 uint8_t n_x : 1; 1484 uint8_t p_x : 1; 1485 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1486 uint8_t p_x : 1; 1487 uint8_t n_x : 1; 1488 uint8_t p_y : 1; 1489 uint8_t n_y : 1; 1490 uint8_t p_z : 1; 1491 uint8_t n_z : 1; 1492 uint8_t p_v : 1; 1493 uint8_t n_v : 1; 1494 #endif /* DRV_BYTE_ORDER */ 1495 } st1vafe3bx_fsm_outs5_t; 1496 1497 #define ST1VAFE3BX_FSM_OUTS6 0x25U 1498 typedef struct 1499 { 1500 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1501 uint8_t n_v : 1; 1502 uint8_t p_v : 1; 1503 uint8_t n_z : 1; 1504 uint8_t p_z : 1; 1505 uint8_t n_y : 1; 1506 uint8_t p_y : 1; 1507 uint8_t n_x : 1; 1508 uint8_t p_x : 1; 1509 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1510 uint8_t p_x : 1; 1511 uint8_t n_x : 1; 1512 uint8_t p_y : 1; 1513 uint8_t n_y : 1; 1514 uint8_t p_z : 1; 1515 uint8_t n_z : 1; 1516 uint8_t p_v : 1; 1517 uint8_t n_v : 1; 1518 #endif /* DRV_BYTE_ORDER */ 1519 } st1vafe3bx_fsm_outs6_t; 1520 1521 #define ST1VAFE3BX_FSM_OUTS7 0x26U 1522 typedef struct 1523 { 1524 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1525 uint8_t n_v : 1; 1526 uint8_t p_v : 1; 1527 uint8_t n_z : 1; 1528 uint8_t p_z : 1; 1529 uint8_t n_y : 1; 1530 uint8_t p_y : 1; 1531 uint8_t n_x : 1; 1532 uint8_t p_x : 1; 1533 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1534 uint8_t p_x : 1; 1535 uint8_t n_x : 1; 1536 uint8_t p_y : 1; 1537 uint8_t n_y : 1; 1538 uint8_t p_z : 1; 1539 uint8_t n_z : 1; 1540 uint8_t p_v : 1; 1541 uint8_t n_v : 1; 1542 #endif /* DRV_BYTE_ORDER */ 1543 } st1vafe3bx_fsm_outs7_t; 1544 1545 #define ST1VAFE3BX_FSM_OUTS8 0x27U 1546 typedef struct 1547 { 1548 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1549 uint8_t n_v : 1; 1550 uint8_t p_v : 1; 1551 uint8_t n_z : 1; 1552 uint8_t p_z : 1; 1553 uint8_t n_y : 1; 1554 uint8_t p_y : 1; 1555 uint8_t n_x : 1; 1556 uint8_t p_x : 1; 1557 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1558 uint8_t p_x : 1; 1559 uint8_t n_x : 1; 1560 uint8_t p_y : 1; 1561 uint8_t n_y : 1; 1562 uint8_t p_z : 1; 1563 uint8_t n_z : 1; 1564 uint8_t p_v : 1; 1565 uint8_t n_v : 1; 1566 #endif /* DRV_BYTE_ORDER */ 1567 } st1vafe3bx_fsm_outs8_t; 1568 1569 #define ST1VAFE3BX_STEP_COUNTER_L 0x28U 1570 typedef struct 1571 { 1572 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1573 uint8_t step : 8; 1574 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1575 uint8_t step : 8; 1576 #endif /* DRV_BYTE_ORDER */ 1577 } st1vafe3bx_step_counter_l_t; 1578 1579 #define ST1VAFE3BX_STEP_COUNTER_H 0x29U 1580 typedef struct 1581 { 1582 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1583 uint8_t step : 8; 1584 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1585 uint8_t step : 8; 1586 #endif /* DRV_BYTE_ORDER */ 1587 } st1vafe3bx_step_counter_h_t; 1588 1589 #define ST1VAFE3BX_EMB_FUNC_SRC 0x2AU 1590 typedef struct 1591 { 1592 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1593 uint8_t not_used0 : 2; 1594 uint8_t stepcounter_bit_set : 1; 1595 uint8_t step_overflow : 1; 1596 uint8_t step_count_delta_ia : 1; 1597 uint8_t step_detected : 1; 1598 uint8_t not_used1 : 1; 1599 uint8_t pedo_rst_step : 1; 1600 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1601 uint8_t pedo_rst_step : 1; 1602 uint8_t not_used1 : 1; 1603 uint8_t step_detected : 1; 1604 uint8_t step_count_delta_ia : 1; 1605 uint8_t step_overflow : 1; 1606 uint8_t stepcounter_bit_set : 1; 1607 uint8_t not_used0 : 2; 1608 #endif /* DRV_BYTE_ORDER */ 1609 } st1vafe3bx_emb_func_src_t; 1610 1611 #define ST1VAFE3BX_EMB_FUNC_INIT_A 0x2CU 1612 typedef struct 1613 { 1614 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1615 uint8_t not_used0 : 3; 1616 uint8_t step_det_init : 1; 1617 uint8_t tilt_init : 1; 1618 uint8_t sig_mot_init : 1; 1619 uint8_t not_used1 : 1; 1620 uint8_t mlc_before_fsm_init : 1; 1621 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1622 uint8_t mlc_before_fsm_init : 1; 1623 uint8_t not_used1 : 1; 1624 uint8_t sig_mot_init : 1; 1625 uint8_t tilt_init : 1; 1626 uint8_t step_det_init : 1; 1627 uint8_t not_used0 : 3; 1628 #endif /* DRV_BYTE_ORDER */ 1629 } st1vafe3bx_emb_func_init_a_t; 1630 1631 #define ST1VAFE3BX_EMB_FUNC_INIT_B 0x2DU 1632 typedef struct 1633 { 1634 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1635 uint8_t fsm_init : 1; 1636 uint8_t not_used0 : 3; 1637 uint8_t mlc_init : 1; 1638 uint8_t not_used1 : 3; 1639 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1640 uint8_t not_used1 : 3; 1641 uint8_t mlc_init : 1; 1642 uint8_t not_used0 : 3; 1643 uint8_t fsm_init : 1; 1644 #endif /* DRV_BYTE_ORDER */ 1645 } st1vafe3bx_emb_func_init_b_t; 1646 1647 #define ST1VAFE3BX_MLC1_SRC 0x34U 1648 typedef struct 1649 { 1650 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1651 uint8_t mlc1_src : 8; 1652 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1653 uint8_t mlc1_src : 8; 1654 #endif /* DRV_BYTE_ORDER */ 1655 } st1vafe3bx_mlc1_src_t; 1656 1657 #define ST1VAFE3BX_MLC2_SRC 0x35U 1658 typedef struct 1659 { 1660 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1661 uint8_t mlc2_src : 8; 1662 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1663 uint8_t mlc2_src : 8; 1664 #endif /* DRV_BYTE_ORDER */ 1665 } st1vafe3bx_mlc2_src_t; 1666 1667 #define ST1VAFE3BX_MLC3_SRC 0x36U 1668 typedef struct 1669 { 1670 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1671 uint8_t mlc3_src : 8; 1672 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1673 uint8_t mlc3_src : 8; 1674 #endif /* DRV_BYTE_ORDER */ 1675 } st1vafe3bx_mlc3_src_t; 1676 1677 #define ST1VAFE3BX_MLC4_SRC 0x37U 1678 typedef struct 1679 { 1680 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1681 uint8_t mlc4_src : 8; 1682 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1683 uint8_t mlc4_src : 8; 1684 #endif /* DRV_BYTE_ORDER */ 1685 } st1vafe3bx_mlc4_src_t; 1686 1687 #define ST1VAFE3BX_FSM_ODR 0x39U 1688 typedef struct 1689 { 1690 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1691 uint8_t not_used0 : 3; 1692 uint8_t fsm_odr : 3; 1693 uint8_t not_used1 : 2; 1694 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1695 uint8_t not_used1 : 2; 1696 uint8_t fsm_odr : 3; 1697 uint8_t not_used0 : 3; 1698 #endif /* DRV_BYTE_ORDER */ 1699 } st1vafe3bx_fsm_odr_t; 1700 1701 #define ST1VAFE3BX_MLC_ODR 0x3AU 1702 typedef struct 1703 { 1704 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1705 uint8_t not_used0 : 4; 1706 uint8_t mlc_odr : 3; 1707 uint8_t not_used1 : 1; 1708 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1709 uint8_t not_used1 : 1; 1710 uint8_t mlc_odr : 3; 1711 uint8_t not_used0 : 4; 1712 #endif /* DRV_BYTE_ORDER */ 1713 } st1vafe3bx_mlc_odr_t; 1714 1715 /** 1716 * @} 1717 * 1718 */ 1719 1720 /** @defgroup bitfields page pg0_emb_adv 1721 * @{ 1722 * 1723 */ 1724 #define ST1VAFE3BX_EMB_ADV_PG_0 0x000U 1725 1726 #define ST1VAFE3BX_FSM_LC_TIMEOUT_L 0x54U 1727 typedef struct 1728 { 1729 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1730 uint8_t fsm_lc_timeout : 8; 1731 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1732 uint8_t fsm_lc_timeout : 8; 1733 #endif /* DRV_BYTE_ORDER */ 1734 } st1vafe3bx_fsm_lc_timeout_l_t; 1735 1736 #define ST1VAFE3BX_FSM_LC_TIMEOUT_H 0x55U 1737 typedef struct 1738 { 1739 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1740 uint8_t fsm_lc_timeout : 8; 1741 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1742 uint8_t fsm_lc_timeout : 8; 1743 #endif /* DRV_BYTE_ORDER */ 1744 } st1vafe3bx_fsm_lc_timeout_h_t; 1745 1746 #define ST1VAFE3BX_FSM_PROGRAMS 0x56U 1747 typedef struct 1748 { 1749 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1750 uint8_t fsm_n_prog : 8; 1751 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1752 uint8_t fsm_n_prog : 8; 1753 #endif /* DRV_BYTE_ORDER */ 1754 } st1vafe3bx_fsm_programs_t; 1755 1756 #define ST1VAFE3BX_FSM_START_ADD_L 0x58U 1757 typedef struct 1758 { 1759 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1760 uint8_t fsm_start : 8; 1761 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1762 uint8_t fsm_start : 8; 1763 #endif /* DRV_BYTE_ORDER */ 1764 } st1vafe3bx_fsm_start_add_l_t; 1765 1766 #define ST1VAFE3BX_FSM_START_ADD_H 0x59U 1767 typedef struct 1768 { 1769 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1770 uint8_t fsm_start : 8; 1771 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1772 uint8_t fsm_start : 8; 1773 #endif /* DRV_BYTE_ORDER */ 1774 } st1vafe3bx_fsm_start_add_h_t; 1775 1776 #define ST1VAFE3BX_PEDO_CMD_REG 0x5DU 1777 typedef struct 1778 { 1779 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1780 uint8_t not_used0 : 2; 1781 uint8_t fp_rejection_en : 1; 1782 uint8_t carry_count_en : 1; 1783 uint8_t not_used1 : 4; 1784 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1785 uint8_t not_used1 : 4; 1786 uint8_t carry_count_en : 1; 1787 uint8_t fp_rejection_en : 1; 1788 uint8_t not_used0 : 2; 1789 #endif /* DRV_BYTE_ORDER */ 1790 } st1vafe3bx_pedo_cmd_reg_t; 1791 1792 #define ST1VAFE3BX_PEDO_DEB_STEPS_CONF 0x5EU 1793 typedef struct 1794 { 1795 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1796 uint8_t deb_step : 8; 1797 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1798 uint8_t deb_step : 8; 1799 #endif /* DRV_BYTE_ORDER */ 1800 } st1vafe3bx_pedo_deb_steps_conf_t; 1801 1802 #define ST1VAFE3BX_PEDO_SC_DELTAT_L 0xAAU 1803 typedef struct 1804 { 1805 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1806 uint8_t pd_sc : 8; 1807 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1808 uint8_t pd_sc : 8; 1809 #endif /* DRV_BYTE_ORDER */ 1810 } st1vafe3bx_pedo_sc_deltat_l_t; 1811 1812 #define ST1VAFE3BX_PEDO_SC_DELTAT_H 0xABU 1813 typedef struct 1814 { 1815 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1816 uint8_t pd_sc : 8; 1817 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1818 uint8_t pd_sc : 8; 1819 #endif /* DRV_BYTE_ORDER */ 1820 } st1vafe3bx_pedo_sc_deltat_h_t; 1821 1822 #define ST1VAFE3BX_AH_BIO_SENSITIVITY_L 0xB6U 1823 typedef struct 1824 { 1825 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1826 uint8_t ah_bio_s : 8; 1827 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1828 uint8_t ah_bio_s : 8; 1829 #endif /* DRV_BYTE_ORDER */ 1830 } st1vafe3bx_ah_bio_sensitivity_l_t; 1831 1832 #define ST1VAFE3BX_AH_BIO_SENSITIVITY_H 0xB7U 1833 typedef struct 1834 { 1835 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1836 uint8_t ah_bio_s : 8; 1837 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1838 uint8_t ah_bio_s : 8; 1839 #endif /* DRV_BYTE_ORDER */ 1840 } st1vafe3bx_ah_bio_sensitivity_h_t; 1841 1842 #define ST1VAFE3BX_SMART_POWER_CTRL 0xD2U 1843 typedef struct 1844 { 1845 #if DRV_BYTE_ORDER == DRV_LITTLE_ENDIAN 1846 uint8_t smart_power_ctrl_win : 4; 1847 uint8_t smart_power_ctrl_dur : 4; 1848 #elif DRV_BYTE_ORDER == DRV_BIG_ENDIAN 1849 uint8_t smart_power_ctrl_dur : 4; 1850 uint8_t smart_power_ctrl_win : 4; 1851 #endif /* DRV_BYTE_ORDER */ 1852 } st1vafe3bx_smart_power_ctrl_t; 1853 1854 /** 1855 * @} 1856 * 1857 */ 1858 1859 typedef union 1860 { 1861 st1vafe3bx_ext_clk_cfg_t ext_clk_cfg; 1862 st1vafe3bx_pin_ctrl_t pin_ctrl; 1863 st1vafe3bx_wake_up_dur_ext_t wake_up_dur_ext; 1864 st1vafe3bx_who_am_i_t who_am_i; 1865 st1vafe3bx_ctrl1_t ctrl1; 1866 st1vafe3bx_ctrl2_t ctrl2; 1867 st1vafe3bx_ctrl3_t ctrl3; 1868 st1vafe3bx_ctrl4_t ctrl4; 1869 st1vafe3bx_ctrl5_t ctrl5; 1870 st1vafe3bx_fifo_ctrl_t fifo_ctrl; 1871 st1vafe3bx_fifo_wtm_t fifo_wtm; 1872 st1vafe3bx_interrupt_cfg_t interrupt_cfg; 1873 st1vafe3bx_sixd_t sixd; 1874 st1vafe3bx_wake_up_ths_t wake_up_ths; 1875 st1vafe3bx_wake_up_dur_t wake_up_dur; 1876 st1vafe3bx_free_fall_t free_fall; 1877 st1vafe3bx_md1_cfg_t md1_cfg; 1878 st1vafe3bx_wake_up_src_t wake_up_src; 1879 st1vafe3bx_tap_src_t tap_src; 1880 st1vafe3bx_sixd_src_t sixd_src; 1881 st1vafe3bx_all_int_src_t all_int_src; 1882 st1vafe3bx_status_register_t status; 1883 st1vafe3bx_fifo_status1_t fifo_status1; 1884 st1vafe3bx_fifo_status2_t fifo_status2; 1885 st1vafe3bx_out_x_l_t out_x_l; 1886 st1vafe3bx_out_x_h_t out_x_h; 1887 st1vafe3bx_out_y_l_t out_y_l; 1888 st1vafe3bx_out_y_h_t out_y_h; 1889 st1vafe3bx_out_z_l_t out_z_l; 1890 st1vafe3bx_out_z_h_t out_z_h; 1891 st1vafe3bx_out_ah_bio_l_t out_ah_bio_l; 1892 st1vafe3bx_out_ah_bio_h_t out_ah_bio_h; 1893 st1vafe3bx_ah_bio_cfg1_t ah_bio_cfg1; 1894 st1vafe3bx_ah_bio_cfg2_t ah_bio_cfg2; 1895 st1vafe3bx_ah_bio_cfg3_t ah_bio_cfg3; 1896 st1vafe3bx_i3c_if_ctrl_t i3c_if_ctrl; 1897 st1vafe3bx_emb_func_status_mainpage_t emb_func_status_mainpage; 1898 st1vafe3bx_fsm_status_mainpage_t fsm_status_mainpage; 1899 st1vafe3bx_mlc_status_mainpage_t mlc_status_mainpage; 1900 st1vafe3bx_en_device_config_t en_device_config; 1901 st1vafe3bx_func_cfg_access_t func_cfg_access; 1902 st1vafe3bx_fifo_data_out_tag_t fifo_data_out_tag; 1903 st1vafe3bx_fifo_data_out_x_l_t fifo_data_out_x_l; 1904 st1vafe3bx_fifo_data_out_x_h_t fifo_data_out_x_h; 1905 st1vafe3bx_fifo_data_out_y_l_t fifo_data_out_y_l; 1906 st1vafe3bx_fifo_data_out_y_h_t fifo_data_out_y_h; 1907 st1vafe3bx_fifo_data_out_z_l_t fifo_data_out_z_l; 1908 st1vafe3bx_fifo_data_out_z_h_t fifo_data_out_z_h; 1909 st1vafe3bx_fifo_batch_dec_t fifo_batch_dec; 1910 st1vafe3bx_tap_cfg0_t tap_cfg0; 1911 st1vafe3bx_tap_cfg1_t tap_cfg1; 1912 st1vafe3bx_tap_cfg2_t tap_cfg2; 1913 st1vafe3bx_tap_cfg3_t tap_cfg3; 1914 st1vafe3bx_tap_cfg4_t tap_cfg4; 1915 st1vafe3bx_tap_cfg5_t tap_cfg5; 1916 st1vafe3bx_tap_cfg6_t tap_cfg6; 1917 st1vafe3bx_timestamp0_t timestamp0; 1918 st1vafe3bx_timestamp1_t timestamp1; 1919 st1vafe3bx_timestamp2_t timestamp2; 1920 st1vafe3bx_timestamp3_t timestamp3; 1921 st1vafe3bx_page_sel_t page_sel; 1922 st1vafe3bx_emb_func_en_a_t emb_func_en_a; 1923 st1vafe3bx_emb_func_en_b_t emb_func_en_b; 1924 st1vafe3bx_emb_func_exec_status_t emb_func_exec_status; 1925 st1vafe3bx_page_address_t page_address; 1926 st1vafe3bx_page_value_t page_value; 1927 st1vafe3bx_emb_func_int_t emb_func_int; 1928 st1vafe3bx_fsm_int_t fsm_int; 1929 st1vafe3bx_mlc_int_t mlc_int; 1930 st1vafe3bx_emb_func_status_t emb_func_status; 1931 st1vafe3bx_fsm_status_t fsm_status; 1932 st1vafe3bx_mlc_status_t mlc_status; 1933 st1vafe3bx_page_rw_t page_rw; 1934 st1vafe3bx_emb_func_fifo_en_t emb_func_fifo_en; 1935 st1vafe3bx_fsm_enable_t fsm_enable; 1936 st1vafe3bx_fsm_long_counter_l_t fsm_long_counter_l; 1937 st1vafe3bx_fsm_long_counter_h_t fsm_long_counter_h; 1938 st1vafe3bx_int_ack_mask_t int_ack_mask; 1939 st1vafe3bx_fsm_outs1_t fsm_outs1; 1940 st1vafe3bx_fsm_outs2_t fsm_outs2; 1941 st1vafe3bx_fsm_outs3_t fsm_outs3; 1942 st1vafe3bx_fsm_outs4_t fsm_outs4; 1943 st1vafe3bx_fsm_outs5_t fsm_outs5; 1944 st1vafe3bx_fsm_outs6_t fsm_outs6; 1945 st1vafe3bx_fsm_outs7_t fsm_outs7; 1946 st1vafe3bx_fsm_outs8_t fsm_outs8; 1947 st1vafe3bx_step_counter_l_t step_counter_l; 1948 st1vafe3bx_step_counter_h_t step_counter_h; 1949 st1vafe3bx_emb_func_src_t emb_func_src; 1950 st1vafe3bx_emb_func_init_a_t emb_func_init_a; 1951 st1vafe3bx_emb_func_init_b_t emb_func_init_b; 1952 st1vafe3bx_mlc1_src_t mlc1_src; 1953 st1vafe3bx_mlc2_src_t mlc2_src; 1954 st1vafe3bx_mlc3_src_t mlc3_src; 1955 st1vafe3bx_mlc4_src_t mlc4_src; 1956 st1vafe3bx_fsm_odr_t fsm_odr; 1957 st1vafe3bx_mlc_odr_t mlc_odr; 1958 st1vafe3bx_fsm_lc_timeout_l_t fsm_lc_timeout_l; 1959 st1vafe3bx_fsm_lc_timeout_h_t fsm_lc_timeout_h; 1960 st1vafe3bx_fsm_programs_t fsm_programs; 1961 st1vafe3bx_fsm_start_add_l_t fsm_start_add_l; 1962 st1vafe3bx_fsm_start_add_h_t fsm_start_add_h; 1963 st1vafe3bx_pedo_cmd_reg_t pedo_cmd_reg; 1964 st1vafe3bx_pedo_deb_steps_conf_t pedo_deb_steps_conf; 1965 st1vafe3bx_pedo_sc_deltat_l_t pedo_sc_deltat_l; 1966 st1vafe3bx_pedo_sc_deltat_h_t pedo_sc_deltat_h; 1967 st1vafe3bx_ah_bio_sensitivity_l_t ah_bio_sensitivity_l; 1968 st1vafe3bx_ah_bio_sensitivity_h_t ah_bio_sensitivity_h; 1969 st1vafe3bx_smart_power_ctrl_t smart_power_ctrl; 1970 bitwise_t bitwise; 1971 uint8_t byte; 1972 } st1vafe3bx_reg_t; 1973 1974 /** 1975 * @} 1976 * 1977 */ 1978 1979 #ifndef __weak 1980 #define __weak __attribute__((weak)) 1981 #endif /* __weak */ 1982 1983 /* 1984 * These are the basic platform dependent I/O routines to read 1985 * and write device registers connected on a standard bus. 1986 * The driver keeps offering a default implementation based on function 1987 * pointers to read/write routines for backward compatibility. 1988 * The __weak directive allows the final application to overwrite 1989 * them with a custom implementation. 1990 */ 1991 1992 int32_t st1vafe3bx_read_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1993 uint8_t *data, 1994 uint16_t len); 1995 int32_t st1vafe3bx_write_reg(const stmdev_ctx_t *ctx, uint8_t reg, 1996 uint8_t *data, 1997 uint16_t len); 1998 1999 float_t st1vafe3bx_from_fs2g_to_mg(int16_t lsb); 2000 float_t st1vafe3bx_from_fs4g_to_mg(int16_t lsb); 2001 float_t st1vafe3bx_from_fs8g_to_mg(int16_t lsb); 2002 float_t st1vafe3bx_from_fs16g_to_mg(int16_t lsb); 2003 float_t st1vafe3bx_from_lsb_to_celsius(int16_t lsb); 2004 float_t st1vafe3bx_from_lsb_to_mv(int16_t lsb); 2005 2006 int32_t st1vafe3bx_device_id_get(const stmdev_ctx_t *ctx, uint8_t *val); 2007 2008 typedef enum 2009 { 2010 ST1VAFE3BX_SENSOR_ONLY_ON = 0x00, /* Initialize the driver for sensor usage */ 2011 ST1VAFE3BX_BOOT = 0x01, /* Restore calib. param. (it takes 10ms) */ 2012 ST1VAFE3BX_RESET = 0x02, /* Reset configuration registers */ 2013 ST1VAFE3BX_SENSOR_EMB_FUNC_ON = 0x03, /* Initialize the driver for sensor and/or 2014 embedded functions usage (it takes 10ms) */ 2015 ST1VAFE3BX_VAFE_ONLY_LP = 0x04, /* Enable sensor in vAFE only mode - low performance */ 2016 ST1VAFE3BX_VAFE_ONLY_HP = 0x05, /* Enable sensor in vAFE only mode - high performance */ 2017 } st1vafe3bx_init_t; 2018 int32_t st1vafe3bx_init_set(const stmdev_ctx_t *ctx, st1vafe3bx_init_t val); 2019 2020 typedef struct 2021 { 2022 uint8_t pwr_en : 1; /* Smart power enable */ 2023 uint8_t pwr_ctrl_win : 4; /* Number of consecutive windows */ 2024 uint8_t pwr_ctrl_dur : 4; /* Duration threshold */ 2025 } st1vafe3bx_smart_power_t; 2026 int32_t st1vafe3bx_smart_power_set(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t val); 2027 int32_t st1vafe3bx_smart_power_get(const stmdev_ctx_t *ctx, st1vafe3bx_smart_power_t *val); 2028 2029 typedef struct 2030 { 2031 uint8_t sw_reset : 1; /* Restoring configuration registers */ 2032 uint8_t boot : 1; /* Restoring calibration parameters */ 2033 uint8_t drdy : 1; /* Accelerometer data ready */ 2034 uint8_t power_down : 1; /* Monitors power-down. */ 2035 } st1vafe3bx_status_t; 2036 int32_t st1vafe3bx_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val); 2037 int32_t st1vafe3bx_drdy_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_status_t *val); 2038 2039 typedef struct 2040 { 2041 uint8_t is_step_det : 1; /* Step detected */ 2042 uint8_t is_tilt : 1; /* Tilt detected */ 2043 uint8_t is_sigmot : 1; /* Significant motion detected */ 2044 uint8_t is_fsm_lc : 1; /* FSM long counter timeout */ 2045 } st1vafe3bx_embedded_status_t; 2046 int32_t st1vafe3bx_embedded_status_get(const stmdev_ctx_t *ctx, st1vafe3bx_embedded_status_t *val); 2047 2048 typedef enum 2049 { 2050 ST1VAFE3BX_DRDY_LATCHED = 0x0, 2051 ST1VAFE3BX_DRDY_PULSED = 0x1, 2052 } st1vafe3bx_data_ready_mode_t; 2053 int32_t st1vafe3bx_data_ready_mode_set(const stmdev_ctx_t *ctx, st1vafe3bx_data_ready_mode_t val); 2054 int32_t st1vafe3bx_data_ready_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_data_ready_mode_t *val); 2055 2056 typedef enum 2057 { 2058 ST1VAFE3BX_OFF = 0x00, /* in power down */ 2059 ST1VAFE3BX_1Hz6_ULP = 0x01, /* @1Hz6 (ultra low power) */ 2060 ST1VAFE3BX_3Hz_ULP = 0x02, /* @3Hz (ultra low power) */ 2061 ST1VAFE3BX_25Hz_ULP = 0x03, /* @25Hz (ultra low power) */ 2062 ST1VAFE3BX_6Hz_LP = 0x04, /* @6Hz (low power) */ 2063 ST1VAFE3BX_12Hz5_LP = 0x05, /* @12Hz5 (low power) */ 2064 ST1VAFE3BX_25Hz_LP = 0x06, /* @25Hz (low power ) */ 2065 ST1VAFE3BX_50Hz_LP = 0x07, /* @50Hz (low power) */ 2066 ST1VAFE3BX_100Hz_LP = 0x08, /* @100Hz (low power) */ 2067 ST1VAFE3BX_200Hz_LP = 0x09, /* @200Hz (low power) */ 2068 ST1VAFE3BX_400Hz_LP = 0x0A, /* @400Hz (low power) */ 2069 ST1VAFE3BX_800Hz_LP = 0x0B, /* @800Hz (low power) */ 2070 ST1VAFE3BX_6Hz_HP = 0x14, /* @6Hz (high performance) */ 2071 ST1VAFE3BX_12Hz5_HP = 0x15, /* @12Hz5 (high performance) */ 2072 ST1VAFE3BX_25Hz_HP = 0x16, /* @25Hz (high performance ) */ 2073 ST1VAFE3BX_50Hz_HP = 0x17, /* @50Hz (high performance) */ 2074 ST1VAFE3BX_100Hz_HP = 0x18, /* @100Hz (high performance) */ 2075 ST1VAFE3BX_200Hz_HP = 0x19, /* @200Hz (high performance) */ 2076 ST1VAFE3BX_400Hz_HP = 0x1A, /* @400Hz (high performance) */ 2077 ST1VAFE3BX_800Hz_HP = 0x1B, /* @800Hz (high performance) */ 2078 ST1VAFE3BX_TRIG_PIN = 0x2E, /* Single-shot high latency by INT2 */ 2079 ST1VAFE3BX_TRIG_SW = 0x2F, /* Single-shot high latency by IF */ 2080 ST1VAFE3BX_3200Hz_VAFE_LP = 0x2B, /* @3200Hz (vAFE only low power) */ 2081 ST1VAFE3BX_800Hz_VAFE_HP = 0x3B, /* @800Hz (vAFE only high performance) */ 2082 } st1vafe3bx_odr_t; 2083 2084 typedef enum 2085 { 2086 ST1VAFE3BX_2g = 0, 2087 ST1VAFE3BX_4g = 1, 2088 ST1VAFE3BX_8g = 2, 2089 ST1VAFE3BX_16g = 3, 2090 } st1vafe3bx_fs_t; 2091 2092 typedef enum 2093 { 2094 ST1VAFE3BX_BW_VAFE_45Hz = 0, 2095 ST1VAFE3BX_BW_VAFE_90Hz = 1, 2096 ST1VAFE3BX_BW_VAFE_180Hz = 2, 2097 ST1VAFE3BX_BW_VAFE_360Hz = 3, 2098 ST1VAFE3BX_BW_VAFE_700Hz = 4, 2099 ST1VAFE3BX_BW_VAFE_1600Hz = 5, 2100 ST1VAFE3BX_BW_ODR_div_2 = 7, 2101 ST1VAFE3BX_BW_ODR_div_4 = 8, 2102 ST1VAFE3BX_BW_ODR_div_8 = 9, 2103 ST1VAFE3BX_BW_ODR_div_16 = 10, 2104 ST1VAFE3BX_BW_LP_3Hz = 11, 2105 ST1VAFE3BX_BW_LP_6Hz = 12, 2106 ST1VAFE3BX_BW_LP_12Hz5 = 13, 2107 } st1vafe3bx_bw_t; 2108 2109 typedef struct 2110 { 2111 /* if the hp_en bit is set the AH / vAFE data are in 14-bit format */ 2112 uint8_t hp_en : 1; 2113 st1vafe3bx_fs_t fs : 2; 2114 st1vafe3bx_odr_t odr; 2115 st1vafe3bx_bw_t bw; 2116 } st1vafe3bx_md_t; 2117 int32_t st1vafe3bx_mode_set(const stmdev_ctx_t *ctx, 2118 const st1vafe3bx_md_t *val); 2119 int32_t st1vafe3bx_mode_get(const stmdev_ctx_t *ctx, st1vafe3bx_md_t *val); 2120 2121 int32_t st1vafe3bx_trigger_sw(const stmdev_ctx_t *ctx, 2122 const st1vafe3bx_md_t *md); 2123 2124 typedef struct 2125 { 2126 uint8_t drdy : 1; 2127 uint8_t timestamp : 1; 2128 uint8_t free_fall : 1; 2129 uint8_t wake_up : 1; 2130 uint8_t wake_up_z : 1; 2131 uint8_t wake_up_y : 1; 2132 uint8_t wake_up_x : 1; 2133 uint8_t single_tap : 1; 2134 uint8_t double_tap : 1; 2135 uint8_t triple_tap : 1; 2136 uint8_t six_d : 1; 2137 uint8_t six_d_xl : 1; 2138 uint8_t six_d_xh : 1; 2139 uint8_t six_d_yl : 1; 2140 uint8_t six_d_yh : 1; 2141 uint8_t six_d_zl : 1; 2142 uint8_t six_d_zh : 1; 2143 uint8_t sleep_change : 1; 2144 uint8_t sleep_state : 1; 2145 uint8_t tilt : 1; 2146 uint8_t fifo_bdr : 1; 2147 uint8_t fifo_full : 1; 2148 uint8_t fifo_ovr : 1; 2149 uint8_t fifo_th : 1; 2150 } st1vafe3bx_all_sources_t; 2151 int32_t st1vafe3bx_all_sources_get(const stmdev_ctx_t *ctx, 2152 st1vafe3bx_all_sources_t *val); 2153 2154 typedef struct 2155 { 2156 float_t mg[3]; 2157 int16_t raw[3]; 2158 } st1vafe3bx_xl_data_t; 2159 int32_t st1vafe3bx_xl_data_get(const stmdev_ctx_t *ctx, 2160 const st1vafe3bx_md_t *md, 2161 st1vafe3bx_xl_data_t *data); 2162 2163 typedef struct 2164 { 2165 float_t mv; 2166 int16_t raw; 2167 } st1vafe3bx_ah_bio_data_t; 2168 int32_t st1vafe3bx_ah_bio_data_get(const stmdev_ctx_t *ctx, 2169 st1vafe3bx_ah_bio_data_t *data); 2170 2171 typedef enum 2172 { 2173 ST1VAFE3BX_XL_ST_DISABLE = 0x0, 2174 ST1VAFE3BX_XL_ST_POSITIVE = 0x1, 2175 ST1VAFE3BX_XL_ST_NEGATIVE = 0x2, 2176 } st1vafe3bx_xl_self_test_t; 2177 int32_t st1vafe3bx_self_test_sign_set(const stmdev_ctx_t *ctx, 2178 st1vafe3bx_xl_self_test_t val); 2179 int32_t st1vafe3bx_self_test_start(const stmdev_ctx_t *ctx, uint8_t val); 2180 int32_t st1vafe3bx_self_test_stop(const stmdev_ctx_t *ctx); 2181 2182 int32_t st1vafe3bx_enter_deep_power_down(const stmdev_ctx_t *ctx, uint8_t val); 2183 int32_t st1vafe3bx_exit_deep_power_down(const stmdev_ctx_t *ctx); 2184 2185 typedef struct 2186 { 2187 enum 2188 { 2189 ST1VAFE3BX_I3C_BUS_AVAIL_TIME_20US = 0x0, 2190 ST1VAFE3BX_I3C_BUS_AVAIL_TIME_50US = 0x1, 2191 ST1VAFE3BX_I3C_BUS_AVAIL_TIME_1MS = 0x2, 2192 ST1VAFE3BX_I3C_BUS_AVAIL_TIME_25MS = 0x3, 2193 } bus_act_sel; 2194 uint8_t asf_on : 1; 2195 uint8_t drstdaa_en : 1; 2196 } st1vafe3bx_i3c_cfg_t; 2197 int32_t st1vafe3bx_i3c_configure_set(const stmdev_ctx_t *ctx, 2198 const st1vafe3bx_i3c_cfg_t *val); 2199 int32_t st1vafe3bx_i3c_configure_get(const stmdev_ctx_t *ctx, 2200 st1vafe3bx_i3c_cfg_t *val); 2201 2202 typedef enum 2203 { 2204 ST1VAFE3BX_MAIN_MEM_BANK = 0x0, 2205 ST1VAFE3BX_EMBED_FUNC_MEM_BANK = 0x1, 2206 } st1vafe3bx_mem_bank_t; 2207 int32_t st1vafe3bx_mem_bank_set(const stmdev_ctx_t *ctx, 2208 st1vafe3bx_mem_bank_t val); 2209 int32_t st1vafe3bx_mem_bank_get(const stmdev_ctx_t *ctx, 2210 st1vafe3bx_mem_bank_t *val); 2211 2212 int32_t st1vafe3bx_ln_pg_write(const stmdev_ctx_t *ctx, uint16_t address, 2213 uint8_t *buf, uint8_t len); 2214 int32_t st1vafe3bx_ln_pg_read(const stmdev_ctx_t *ctx, uint16_t address, 2215 uint8_t *buf, uint8_t len); 2216 2217 int32_t st1vafe3bx_ext_clk_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2218 int32_t st1vafe3bx_ext_clk_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2219 2220 typedef struct 2221 { 2222 uint8_t sdo_pull_up : 1; /* 1 = pull up enable */ 2223 uint8_t sda_pull_up : 1; /* 1 = pull up enable */ 2224 uint8_t cs_pull_up : 1; /* 1 = pull up enable */ 2225 uint8_t int_push_pull : 1; /* 1 = push-pull / 0 = open-drain*/ 2226 } st1vafe3bx_pin_conf_t; 2227 int32_t st1vafe3bx_pin_conf_set(const stmdev_ctx_t *ctx, 2228 const st1vafe3bx_pin_conf_t *val); 2229 int32_t st1vafe3bx_pin_conf_get(const stmdev_ctx_t *ctx, 2230 st1vafe3bx_pin_conf_t *val); 2231 2232 typedef enum 2233 { 2234 ST1VAFE3BX_ACTIVE_HIGH = 0x0, 2235 ST1VAFE3BX_ACTIVE_LOW = 0x1, 2236 } st1vafe3bx_int_pin_polarity_t; 2237 int32_t st1vafe3bx_int_pin_polarity_set(const stmdev_ctx_t *ctx, 2238 st1vafe3bx_int_pin_polarity_t val); 2239 int32_t st1vafe3bx_int_pin_polarity_get(const stmdev_ctx_t *ctx, 2240 st1vafe3bx_int_pin_polarity_t *val); 2241 2242 typedef enum 2243 { 2244 ST1VAFE3BX_SPI_4_WIRE = 0x0, /* SPI 4 wires */ 2245 ST1VAFE3BX_SPI_3_WIRE = 0x1, /* SPI 3 wires */ 2246 } st1vafe3bx_spi_mode; 2247 int32_t st1vafe3bx_spi_mode_set(const stmdev_ctx_t *ctx, 2248 st1vafe3bx_spi_mode val); 2249 int32_t st1vafe3bx_spi_mode_get(const stmdev_ctx_t *ctx, 2250 st1vafe3bx_spi_mode *val); 2251 2252 typedef struct 2253 { 2254 uint8_t drdy : 1; /* Accelerometer data ready */ 2255 uint8_t boot : 1; /* Restoring calibration parameters */ 2256 uint8_t fifo_th : 1; /* FIFO threshold reached */ 2257 uint8_t fifo_ovr : 1; /* FIFO overrun */ 2258 uint8_t fifo_full : 1; /* FIFO full */ 2259 uint8_t free_fall : 1; /* free fall event */ 2260 uint8_t six_d : 1; /* orientation change (6D/4D detection) */ 2261 uint8_t tap : 1; /* all tap event */ 2262 uint8_t wake_up : 1; /* wake up event */ 2263 uint8_t sleep_change : 1; /* Act/Inact (or Vice-versa) status changed */ 2264 uint8_t emb_function : 1; /* Embedded Function */ 2265 uint8_t timestamp : 1; /* Timestamp */ 2266 } st1vafe3bx_pin_int_route_t; 2267 int32_t st1vafe3bx_pin_int_route_set(const stmdev_ctx_t *ctx, 2268 const st1vafe3bx_pin_int_route_t *val); 2269 int32_t st1vafe3bx_pin_int_route_get(const stmdev_ctx_t *ctx, 2270 st1vafe3bx_pin_int_route_t *val); 2271 2272 typedef struct 2273 { 2274 uint8_t step_det : 1; /* route step detection event on INT pad */ 2275 uint8_t tilt : 1; /* route tilt event on INT pad */ 2276 uint8_t sig_mot : 1; /* route significant motion event on INT pad */ 2277 uint8_t fsm_lc : 1; /* route FSM long counter event on INT pad */ 2278 } st1vafe3bx_emb_pin_int_route_t; 2279 int32_t st1vafe3bx_emb_pin_int_route_set(const stmdev_ctx_t *ctx, 2280 const st1vafe3bx_emb_pin_int_route_t *val); 2281 int32_t st1vafe3bx_emb_pin_int_route_get(const stmdev_ctx_t *ctx, 2282 st1vafe3bx_emb_pin_int_route_t *val); 2283 2284 typedef enum 2285 { 2286 ST1VAFE3BX_INT_DISABLED = 0x0, 2287 ST1VAFE3BX_INT_LEVEL = 0x1, 2288 ST1VAFE3BX_INT_LATCHED = 0x2, 2289 } st1vafe3bx_int_cfg_t; 2290 2291 typedef struct 2292 { 2293 st1vafe3bx_int_cfg_t int_cfg; 2294 uint8_t sleep_status_on_int : 1; /* route sleep_status on interrupt */ 2295 uint8_t dis_rst_lir_all_int : 1; /* disable LIR reset when reading ALL_INT_SRC */ 2296 } st1vafe3bx_int_config_t; 2297 int32_t st1vafe3bx_int_config_set(const stmdev_ctx_t *ctx, 2298 const st1vafe3bx_int_config_t *val); 2299 int32_t st1vafe3bx_int_config_get(const stmdev_ctx_t *ctx, 2300 st1vafe3bx_int_config_t *val); 2301 2302 typedef enum 2303 { 2304 ST1VAFE3BX_EMBEDDED_INT_LEVEL = 0x0, 2305 ST1VAFE3BX_EMBEDDED_INT_LATCHED = 0x1, 2306 } st1vafe3bx_embedded_int_config_t; 2307 int32_t st1vafe3bx_embedded_int_cfg_set(const stmdev_ctx_t *ctx, 2308 st1vafe3bx_embedded_int_config_t val); 2309 int32_t st1vafe3bx_embedded_int_cfg_get(const stmdev_ctx_t *ctx, 2310 st1vafe3bx_embedded_int_config_t *val); 2311 2312 typedef struct 2313 { 2314 enum st1vafe3bx_operation_t 2315 { 2316 ST1VAFE3BX_BYPASS_MODE = 0x0, 2317 ST1VAFE3BX_FIFO_MODE = 0x1, 2318 ST1VAFE3BX_STREAM_TO_FIFO_MODE = 0x3, 2319 ST1VAFE3BX_BYPASS_TO_STREAM_MODE = 0x4, 2320 ST1VAFE3BX_STREAM_MODE = 0x6, 2321 ST1VAFE3BX_BYPASS_TO_FIFO_MODE = 0x7, 2322 ST1VAFE3BX_FIFO_OFF = 0x8, 2323 } operation; 2324 2325 enum st1vafe3bx_store_t 2326 { 2327 ST1VAFE3BX_FIFO_1X = 0, 2328 ST1VAFE3BX_FIFO_2X = 1, 2329 } store; 2330 2331 uint8_t xl_only : 1; /* only XL samples (16-bit) are stored in FIFO */ 2332 2333 uint8_t watermark : 7; /* (0 disable) max 127 @16bit, even and max 256 @8bit.*/ 2334 uint8_t cfg_change_in_fifo : 1; 2335 struct 2336 { 2337 enum st1vafe3bx_dec_ts_t 2338 { 2339 ST1VAFE3BX_DEC_TS_OFF = 0x0, 2340 ST1VAFE3BX_DEC_TS_1 = 0x1, 2341 ST1VAFE3BX_DEC_TS_8 = 0x2, 2342 ST1VAFE3BX_DEC_TS_32 = 0x3, 2343 } dec_ts; /* decimation for timestamp batching*/ 2344 2345 enum st1vafe3bx_bdr_xl_t 2346 { 2347 ST1VAFE3BX_BDR_ODR = 0x0, 2348 ST1VAFE3BX_BDR_ODR_DIV_2 = 0x1, 2349 ST1VAFE3BX_BDR_ODR_DIV_4 = 0x2, 2350 ST1VAFE3BX_BDR_ODR_DIV_8 = 0x3, 2351 ST1VAFE3BX_BDR_ODR_DIV_16 = 0x4, 2352 ST1VAFE3BX_BDR_ODR_DIV_32 = 0x5, 2353 ST1VAFE3BX_BDR_ODR_DIV_64 = 0x6, 2354 ST1VAFE3BX_BDR_ODR_OFF = 0x7, 2355 } bdr_xl; /* accelerometer batch data rate*/ 2356 } batch; 2357 } st1vafe3bx_fifo_mode_t; 2358 int32_t st1vafe3bx_fifo_mode_set(const stmdev_ctx_t *ctx, 2359 st1vafe3bx_fifo_mode_t val); 2360 int32_t st1vafe3bx_fifo_mode_get(const stmdev_ctx_t *ctx, 2361 st1vafe3bx_fifo_mode_t *val); 2362 2363 int32_t st1vafe3bx_fifo_data_level_get(const stmdev_ctx_t *ctx, uint16_t *val); 2364 int32_t st1vafe3bx_fifo_wtm_flag_get(const stmdev_ctx_t *ctx, uint8_t *val); 2365 2366 typedef enum 2367 { 2368 ST1VAFE3BX_FIFO_EMPTY_TAG = 0x0, 2369 ST1VAFE3BX_XL_ONLY = 0x2, 2370 ST1VAFE3BX_XL_ONLY_2X_TAG = 0x3, 2371 ST1VAFE3BX_TIMESTAMP_CFG_CHG_TAG = 0x4, 2372 ST1VAFE3BX_STEP_COUNTER_TAG = 0x12, 2373 ST1VAFE3BX_MLC_RESULT_TAG = 0x1A, 2374 ST1VAFE3BX_MLC_FILTER_TAG = 0x1B, 2375 ST1VAFE3BX_MLC_FEATURE_TAG = 0x1C, 2376 ST1VAFE3BX_FSM_RESULT_TAG = 0x1D, 2377 ST1VAFE3BX_AH_VAFE_ONLY_TAG = 0x1E, 2378 ST1VAFE3BX_XL_AND_AH_VAFE1_TAG = 0x1F, 2379 } st1vafe3bx_fifo_sensor_tag_t; 2380 int32_t st1vafe3bx_fifo_sensor_tag_get(const stmdev_ctx_t *ctx, 2381 st1vafe3bx_fifo_sensor_tag_t *val); 2382 2383 int32_t st1vafe3bx_fifo_out_raw_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2384 2385 typedef struct 2386 { 2387 uint8_t tag; 2388 struct 2389 { 2390 float_t mg[3]; 2391 int16_t raw[3]; 2392 } xl[2]; 2393 struct 2394 { 2395 float_t mv; 2396 int16_t raw; 2397 } ah_bio; 2398 2399 struct 2400 { 2401 uint32_t steps; 2402 uint32_t timestamp; 2403 } pedo; 2404 struct 2405 { 2406 uint8_t cfg_change : 1; /* 1 if ODR/BDR configuration is changed */ 2407 uint8_t odr : 4; /* ODR */ 2408 uint8_t bw : 2; /* BW */ 2409 uint8_t lp_hp : 1; /* Power: 0 for LP, 1 for HP */ 2410 uint8_t ah_en : 1; /* AH is enabled */ 2411 uint8_t fs : 2; /* FS */ 2412 uint8_t dec_ts : 2; /* Timestamp decimator value */ 2413 uint8_t odr_xl_batch : 1; /* Accelerometer ODR is batched */ 2414 uint32_t timestamp; 2415 } cfg_chg; 2416 } st1vafe3bx_fifo_data_t; 2417 int32_t st1vafe3bx_fifo_data_get(const stmdev_ctx_t *ctx, 2418 const st1vafe3bx_md_t *md, 2419 const st1vafe3bx_fifo_mode_t *fmd, 2420 st1vafe3bx_fifo_data_t *data); 2421 2422 2423 typedef struct 2424 { 2425 uint8_t ah_bio_zin_dis_1 : 1; 2426 uint8_t ah_bio_zin_dis_2 : 1; 2427 2428 enum 2429 { 2430 ST1VAFE3BX_DIFFERENTIAL_MODE = 0x0, 2431 ST1VAFE3BX_SINGLE_MODE_01 = 0x1, 2432 ST1VAFE3BX_SINGLE_MODE_10 = 0x2, 2433 ST1VAFE3BX_FORCED_RESET = 0x3, 2434 } mode; 2435 2436 enum 2437 { 2438 ST1VAFE3BX_100MOhm = 0x0, 2439 ST1VAFE3BX_200MOhm = 0x1, 2440 ST1VAFE3BX_500MOhm = 0x2, 2441 ST1VAFE3BX_1GOhm = 0x3, 2442 } zin; 2443 2444 enum 2445 { 2446 ST1VAFE3BX_GAIN_2 = 0x0, 2447 ST1VAFE3BX_GAIN_4 = 0x1, 2448 ST1VAFE3BX_GAIN_8 = 0x2, 2449 ST1VAFE3BX_GAIN_16 = 0x3, 2450 } gain; 2451 } st1vafe3bx_ah_bio_config_t; 2452 int32_t st1vafe3bx_ah_bio_config_set(const stmdev_ctx_t *ctx, 2453 st1vafe3bx_ah_bio_config_t val); 2454 int32_t st1vafe3bx_ah_bio_config_get(const stmdev_ctx_t *ctx, 2455 st1vafe3bx_ah_bio_config_t *val); 2456 2457 int32_t st1vafe3bx_enter_vafe_only(const stmdev_ctx_t *ctx); 2458 int32_t st1vafe3bx_exit_vafe_only(const stmdev_ctx_t *ctx); 2459 int32_t st1vafe3bx_ah_bio_active(const stmdev_ctx_t *ctx, uint8_t filter_on); 2460 2461 typedef struct 2462 { 2463 uint8_t false_step_rej : 1; 2464 uint8_t step_counter_enable : 1; 2465 uint8_t step_counter_in_fifo : 1; 2466 } st1vafe3bx_stpcnt_mode_t; 2467 int32_t st1vafe3bx_stpcnt_mode_set(const stmdev_ctx_t *ctx, 2468 st1vafe3bx_stpcnt_mode_t val); 2469 int32_t st1vafe3bx_stpcnt_mode_get(const stmdev_ctx_t *ctx, 2470 st1vafe3bx_stpcnt_mode_t *val); 2471 2472 int32_t st1vafe3bx_stpcnt_steps_get(const stmdev_ctx_t *ctx, uint16_t *val); 2473 2474 int32_t st1vafe3bx_stpcnt_rst_step_set(const stmdev_ctx_t *ctx); 2475 2476 int32_t st1vafe3bx_stpcnt_debounce_set(const stmdev_ctx_t *ctx, uint8_t val); 2477 int32_t st1vafe3bx_stpcnt_debounce_get(const stmdev_ctx_t *ctx, uint8_t *val); 2478 2479 int32_t st1vafe3bx_stpcnt_period_set(const stmdev_ctx_t *ctx, uint16_t val); 2480 int32_t st1vafe3bx_stpcnt_period_get(const stmdev_ctx_t *ctx, uint16_t *val); 2481 2482 int32_t st1vafe3bx_tilt_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2483 int32_t st1vafe3bx_tilt_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2484 int32_t st1vafe3bx_sigmot_mode_set(const stmdev_ctx_t *ctx, uint8_t val); 2485 int32_t st1vafe3bx_sigmot_mode_get(const stmdev_ctx_t *ctx, uint8_t *val); 2486 2487 2488 int32_t st1vafe3bx_ff_duration_set(const stmdev_ctx_t *ctx, uint8_t val); 2489 int32_t st1vafe3bx_ff_duration_get(const stmdev_ctx_t *ctx, uint8_t *val); 2490 2491 typedef enum 2492 { 2493 ST1VAFE3BX_156_mg = 0x0, 2494 ST1VAFE3BX_219_mg = 0x1, 2495 ST1VAFE3BX_250_mg = 0x2, 2496 ST1VAFE3BX_312_mg = 0x3, 2497 ST1VAFE3BX_344_mg = 0x4, 2498 ST1VAFE3BX_406_mg = 0x5, 2499 ST1VAFE3BX_469_mg = 0x6, 2500 ST1VAFE3BX_500_mg = 0x7, 2501 } st1vafe3bx_ff_thresholds_t; 2502 int32_t st1vafe3bx_ff_thresholds_set(const stmdev_ctx_t *ctx, 2503 st1vafe3bx_ff_thresholds_t val); 2504 int32_t st1vafe3bx_ff_thresholds_get(const stmdev_ctx_t *ctx, 2505 st1vafe3bx_ff_thresholds_t *val); 2506 2507 typedef enum 2508 { 2509 ST1VAFE3BX_DEG_80 = 0x0, 2510 ST1VAFE3BX_DEG_70 = 0x1, 2511 ST1VAFE3BX_DEG_60 = 0x2, 2512 ST1VAFE3BX_DEG_50 = 0x3, 2513 } st1vafe3bx_threshold_t; 2514 2515 typedef enum 2516 { 2517 ST1VAFE3BX_6D = 0x0, 2518 ST1VAFE3BX_4D = 0x1, 2519 } st1vafe3bx_mode_t; 2520 2521 typedef struct 2522 { 2523 st1vafe3bx_threshold_t threshold; 2524 st1vafe3bx_mode_t mode; 2525 } st1vafe3bx_sixd_config_t; 2526 2527 int32_t st1vafe3bx_sixd_config_set(const stmdev_ctx_t *ctx, 2528 st1vafe3bx_sixd_config_t val); 2529 int32_t st1vafe3bx_sixd_config_get(const stmdev_ctx_t *ctx, 2530 st1vafe3bx_sixd_config_t *val); 2531 2532 typedef enum 2533 { 2534 ST1VAFE3BX_0_ODR = 0x000, /* 0 ODR time */ 2535 ST1VAFE3BX_1_ODR = 0x001, /* 1 ODR time */ 2536 ST1VAFE3BX_2_ODR = 0x002, /* 2 ODR time */ 2537 ST1VAFE3BX_3_ODR = 0x100, /* 3 ODR time */ 2538 ST1VAFE3BX_7_ODR = 0x101, /* 7 ODR time */ 2539 ST1VAFE3BX_11_ODR = 0x102, /* 11 ODR time */ 2540 ST1VAFE3BX_15_ODR = 0x103, /* 15 ODR time */ 2541 } st1vafe3bx_wake_dur_t; 2542 2543 typedef enum 2544 { 2545 ST1VAFE3BX_SLEEP_OFF = 0, 2546 ST1VAFE3BX_SLEEP_ON = 1, 2547 } st1vafe3bx_wake_enable_t; 2548 2549 typedef enum 2550 { 2551 ST1VAFE3BX_ODR_NO_CHANGE = 0, /* no odr change during inactivity state */ 2552 ST1VAFE3BX_ODR_1_6_HZ = 1, /* set odr to 1.6Hz during inactivity state */ 2553 ST1VAFE3BX_ODR_3_HZ = 1, /* set odr to 3Hz during inactivity state */ 2554 ST1VAFE3BX_ODR_25_HZ = 1, /* set odr to 25Hz during inactivity state */ 2555 } st1vafe3bx_inact_odr_t; 2556 2557 typedef struct 2558 { 2559 st1vafe3bx_wake_dur_t wake_dur; 2560 uint8_t sleep_dur : 4; /* 1 LSB == 512 ODR time */ 2561 uint8_t wake_ths : 7; /* wakeup threshold */ 2562 uint8_t wake_ths_weight : 1; /* 0: 1LSB = FS_XL/2^6, 1: 1LSB = FS_XL/2^8 */ 2563 st1vafe3bx_wake_enable_t wake_enable; 2564 st1vafe3bx_inact_odr_t inact_odr; 2565 } st1vafe3bx_wakeup_config_t; 2566 2567 int32_t st1vafe3bx_wakeup_config_set(const stmdev_ctx_t *ctx, 2568 st1vafe3bx_wakeup_config_t val); 2569 int32_t st1vafe3bx_wakeup_config_get(const stmdev_ctx_t *ctx, 2570 st1vafe3bx_wakeup_config_t *val); 2571 2572 typedef enum 2573 { 2574 ST1VAFE3BX_TAP_NONE = 0x0, /* No axis */ 2575 ST1VAFE3BX_TAP_ON_X = 0x1, /* Detect tap on X axis */ 2576 ST1VAFE3BX_TAP_ON_Y = 0x2, /* Detect tap on Y axis */ 2577 ST1VAFE3BX_TAP_ON_Z = 0x3, /* Detect tap on Z axis */ 2578 } st1vafe3bx_axis_t; 2579 2580 typedef struct 2581 { 2582 st1vafe3bx_axis_t axis; 2583 uint8_t inverted_peak_time : 5; /* 1 LSB == 1 sample */ 2584 uint8_t pre_still_ths : 4; /* 1 LSB == 62.5 mg */ 2585 uint8_t post_still_ths : 4; /* 1 LSB == 62.5 mg */ 2586 uint8_t post_still_time : 6; /* samples num during stationary condition */ 2587 uint8_t shock_wait_time : 6; /* samples num during shock condition */ 2588 uint8_t latency : 4; /* samples max num between taps */ 2589 uint8_t wait_end_latency : 1; /* wait end of latency time to generate tap events */ 2590 uint8_t peak_ths : 6; /* 1 LSB == 62.5 mg */ 2591 uint8_t rebound : 5; /* samples num during rebound condition */ 2592 uint8_t pre_still_start : 4; /* pre still start */ 2593 uint8_t pre_still_n : 4; /* pre still n */ 2594 uint8_t single_tap_on : 1; /* enable single tap */ 2595 uint8_t double_tap_on : 1; /* enable double tap */ 2596 uint8_t triple_tap_on : 1; /* enable triple tap */ 2597 } st1vafe3bx_tap_config_t; 2598 2599 int32_t st1vafe3bx_tap_config_set(const stmdev_ctx_t *ctx, 2600 st1vafe3bx_tap_config_t val); 2601 int32_t st1vafe3bx_tap_config_get(const stmdev_ctx_t *ctx, 2602 st1vafe3bx_tap_config_t *val); 2603 2604 int32_t st1vafe3bx_timestamp_set(const stmdev_ctx_t *ctx, uint8_t val); 2605 int32_t st1vafe3bx_timestamp_get(const stmdev_ctx_t *ctx, uint8_t *val); 2606 2607 int32_t st1vafe3bx_timestamp_raw_get(const stmdev_ctx_t *ctx, uint32_t *val); 2608 2609 int32_t st1vafe3bx_long_cnt_flag_data_ready_get(const stmdev_ctx_t *ctx, 2610 uint8_t *val); 2611 2612 int32_t st1vafe3bx_emb_fsm_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2613 int32_t st1vafe3bx_emb_fsm_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2614 2615 typedef struct 2616 { 2617 st1vafe3bx_fsm_enable_t fsm_enable; 2618 } st1vafe3bx_emb_fsm_enable_t; 2619 int32_t st1vafe3bx_fsm_enable_set(const stmdev_ctx_t *ctx, 2620 st1vafe3bx_emb_fsm_enable_t *val); 2621 int32_t st1vafe3bx_fsm_enable_get(const stmdev_ctx_t *ctx, 2622 st1vafe3bx_emb_fsm_enable_t *val); 2623 2624 int32_t st1vafe3bx_long_cnt_set(const stmdev_ctx_t *ctx, uint16_t val); 2625 int32_t st1vafe3bx_long_cnt_get(const stmdev_ctx_t *ctx, uint16_t *val); 2626 2627 int32_t st1vafe3bx_fsm_status_get(const stmdev_ctx_t *ctx, 2628 st1vafe3bx_fsm_status_mainpage_t *val); 2629 int32_t st1vafe3bx_fsm_out_get(const stmdev_ctx_t *ctx, uint8_t *val); 2630 2631 typedef enum 2632 { 2633 ST1VAFE3BX_ODR_FSM_12Hz5 = 0x00, 2634 ST1VAFE3BX_ODR_FSM_25Hz = 0x01, 2635 ST1VAFE3BX_ODR_FSM_50Hz = 0x02, 2636 ST1VAFE3BX_ODR_FSM_100Hz = 0x03, 2637 ST1VAFE3BX_ODR_FSM_200Hz = 0x04, 2638 ST1VAFE3BX_ODR_FSM_400Hz = 0x05, 2639 ST1VAFE3BX_ODR_FSM_800Hz = 0x06, 2640 ST1VAFE3BX_ODR_FSM_VAFE_50Hz = 0x10, 2641 ST1VAFE3BX_ODR_FSM_VAFE_100Hz = 0x11, 2642 ST1VAFE3BX_ODR_FSM_VAFE_200Hz = 0x12, 2643 ST1VAFE3BX_ODR_FSM_VAFE_400Hz = 0x13, 2644 ST1VAFE3BX_ODR_FSM_VAFE_800Hz = 0x14, 2645 ST1VAFE3BX_ODR_FSM_VAFE_1600Hz = 0x15, 2646 } st1vafe3bx_fsm_val_odr_t; 2647 int32_t st1vafe3bx_fsm_data_rate_set(const stmdev_ctx_t *ctx, 2648 st1vafe3bx_fsm_val_odr_t val); 2649 int32_t st1vafe3bx_fsm_data_rate_get(const stmdev_ctx_t *ctx, 2650 st1vafe3bx_fsm_val_odr_t *val); 2651 2652 int32_t st1vafe3bx_fsm_init_set(const stmdev_ctx_t *ctx, uint8_t val); 2653 int32_t st1vafe3bx_fsm_init_get(const stmdev_ctx_t *ctx, uint8_t *val); 2654 2655 int32_t st1vafe3bx_fsm_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2656 int32_t st1vafe3bx_fsm_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2657 2658 int32_t st1vafe3bx_long_cnt_int_value_set(const stmdev_ctx_t *ctx, 2659 uint16_t val); 2660 int32_t st1vafe3bx_long_cnt_int_value_get(const stmdev_ctx_t *ctx, 2661 uint16_t *val); 2662 2663 int32_t st1vafe3bx_fsm_programs_num_set(const stmdev_ctx_t *ctx, uint8_t val); 2664 int32_t st1vafe3bx_fsm_programs_num_get(const stmdev_ctx_t *ctx, uint8_t *val); 2665 2666 int32_t st1vafe3bx_fsm_start_address_set(const stmdev_ctx_t *ctx, 2667 uint16_t val); 2668 int32_t st1vafe3bx_fsm_start_address_get(const stmdev_ctx_t *ctx, 2669 uint16_t *val); 2670 2671 typedef enum 2672 { 2673 ST1VAFE3BX_MLC_OFF = 0, 2674 ST1VAFE3BX_MLC_ON = 1, 2675 ST1VAFE3BX_MLC_ON_BEFORE_FSM = 2, 2676 } st1vafe3bx_mlc_mode_t; 2677 int32_t st1vafe3bx_mlc_set(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t val); 2678 int32_t st1vafe3bx_mlc_get(const stmdev_ctx_t *ctx, st1vafe3bx_mlc_mode_t *val); 2679 2680 int32_t st1vafe3bx_mlc_status_get(const stmdev_ctx_t *ctx, 2681 st1vafe3bx_mlc_status_mainpage_t *val); 2682 2683 int32_t st1vafe3bx_mlc_out_get(const stmdev_ctx_t *ctx, uint8_t *buff); 2684 2685 typedef enum 2686 { 2687 ST1VAFE3BX_ODR_PRGS_12Hz5 = 0x00, 2688 ST1VAFE3BX_ODR_PRGS_25Hz = 0x01, 2689 ST1VAFE3BX_ODR_PRGS_50Hz = 0x02, 2690 ST1VAFE3BX_ODR_PRGS_100Hz = 0x03, 2691 ST1VAFE3BX_ODR_PRGS_200Hz = 0x04, 2692 ST1VAFE3BX_ODR_PRGS_VAFE_50Hz = 0x10, 2693 ST1VAFE3BX_ODR_PRGS_VAFE_100Hz = 0x11, 2694 ST1VAFE3BX_ODR_PRGS_VAFE_200Hz = 0x12, 2695 ST1VAFE3BX_ODR_PRGS_VAFE_400Hz = 0x13, 2696 ST1VAFE3BX_ODR_PRGS_VAFE_800Hz = 0x14, 2697 ST1VAFE3BX_ODR_PRGS_VAFE_1600Hz = 0x15, 2698 } st1vafe3bx_mlc_odr_val_t; 2699 int32_t st1vafe3bx_mlc_data_rate_set(const stmdev_ctx_t *ctx, 2700 st1vafe3bx_mlc_odr_val_t val); 2701 int32_t st1vafe3bx_mlc_data_rate_get(const stmdev_ctx_t *ctx, 2702 st1vafe3bx_mlc_odr_val_t *val); 2703 2704 int32_t st1vafe3bx_mlc_fifo_en_set(const stmdev_ctx_t *ctx, uint8_t val); 2705 int32_t st1vafe3bx_mlc_fifo_en_get(const stmdev_ctx_t *ctx, uint8_t *val); 2706 2707 #ifdef __cplusplus 2708 } 2709 #endif 2710 2711 #endif /* ST1VAFE3BX_REGS_H */ 2712 2713 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 2714
