1 /*
2 * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT renesas_ra_uart_sci
8
9 #include <zephyr/drivers/uart.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
12 #include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
13 #include <zephyr/drivers/pinctrl.h>
14 #include <zephyr/irq.h>
15 #include <zephyr/spinlock.h>
16
17 #include <zephyr/logging/log.h>
18
19 LOG_MODULE_REGISTER(ra_uart_sci, CONFIG_UART_LOG_LEVEL);
20
21 enum {
22 UART_RA_INT_RXI,
23 UART_RA_INT_TXI,
24 UART_RA_INT_ERI,
25 NUM_OF_UART_RA_INT,
26 };
27
28 struct uart_ra_cfg {
29 mem_addr_t regs;
30 const struct device *clock_dev;
31 const struct clock_control_ra_subsys_cfg clock_id;
32 const struct pinctrl_dev_config *pcfg;
33 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
34 int (*irq_config_func)(const struct device *dev);
35 #endif
36 };
37
38 struct uart_ra_data {
39 struct uart_config current_config;
40 uint32_t clk_rate;
41 struct k_spinlock lock;
42 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
43 uint32_t irqn[NUM_OF_UART_RA_INT];
44 uart_irq_callback_user_data_t callback;
45 void *cb_data;
46 #endif
47 };
48
49 #define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS))
50
51 /* Registers */
52 #define SMR 0x00 /*!< Serial Mode Register */
53 #define BRR 0x01 /*!< Bit Rate Register */
54 #define SCR 0x02 /*!< Serial Control Register */
55 #define TDR 0x03 /*!< Transmit Data Register */
56 #define SSR 0x04 /*!< Serial Status Register */
57 #define RDR 0x05 /*!< Receive Data Register */
58 #define SEMR 0x07 /*!< Serial Extended Mode Register */
59 #define MDDR 0x12 /*!< Modulation Duty Register */
60 #define LSR 0x18 /*!< Line Status Register */
61
62 /*
63 * SMR (Serial Mode Register)
64 *
65 * - CKS[0..2]: Clock Select
66 * - MP[2..3]: Multi-Processor Mode(Valid only in asynchronous mode)
67 * - STOP[3..4]: Stop Bit Length(Valid only in asynchronous mode)
68 * - PM[4..5]: Parity Mode (Valid only when the PE bit is 1)
69 * - PE[5..6]: Parity Enable(Valid only in asynchronous mode)
70 * - CHR[6..7]: Character Length(Valid only in asynchronous mode)
71 * - CM[7..8]: Communication Mode
72 */
73 #define SMR_CKS_POS (0)
74 #define SMR_CKS_LEN (2)
75 #define SMR_MP_POS (2)
76 #define SMR_MP_LEN (1)
77 #define SMR_STOP_POS (3)
78 #define SMR_STOP_LEN (1)
79 #define SMR_PM_POS (4)
80 #define SMR_PM_LEN (1)
81 #define SMR_PE_POS (5)
82 #define SMR_PE_LEN (1)
83 #define SMR_CHR_POS (6)
84 #define SMR_CHR_LEN (1)
85 #define SMR_CM_POS (7)
86 #define SMR_CM_LEN (1)
87
88 /**
89 * SCR (Serial Control Register)
90 *
91 * - CKE[0..2]: Clock Enable
92 * - TEIE[2..3]: Transmit End Interrupt Enable
93 * - MPIE[3..4]: Multi-Processor Interrupt Enable (Valid in asynchronous
94 * - RE[4..5]: Receive Enable
95 * - TE[5..6]: Transmit Enable
96 * - RIE[6..7]: Receive Interrupt Enable
97 * - TIE[7..8]: Transmit Interrupt Enable
98 */
99 #define SCR_CKE_POS (0)
100 #define SCR_CKE_LEN (2)
101 #define SCR_TEIE_POS (2)
102 #define SCR_TEIE_LEN (1)
103 #define SCR_MPIE_POS (3)
104 #define SCR_MPIE_LEN (1)
105 #define SCR_RE_POS (4)
106 #define SCR_RE_LEN (1)
107 #define SCR_TE_POS (5)
108 #define SCR_TE_LEN (1)
109 #define SCR_RIE_POS (6)
110 #define SCR_RIE_LEN (1)
111 #define SCR_TIE_POS (7)
112 #define SCR_TIE_LEN (1)
113
114 /**
115 * SSR (Serial Status Register)
116 *
117 * - MPBT[0..1]: Multi-Processor Bit Transfer
118 * - MPB[1..2]: Multi-Processor
119 * - TEND[2..3]: Transmit End Flag
120 * - PER[3..4]: Parity Error Flag
121 * - FER[4..5]: Framing Error Flag
122 * - ORER[5..6]: Overrun Error Flag
123 * - RDRF[6..7]: Receive Data Full Flag
124 * - TDRE[7..8]: Transmit Data Empty Flag
125 */
126 #define SSR_MPBT_POS (0)
127 #define SSR_MPBT_LEN (1)
128 #define SSR_MPB_POS (1)
129 #define SSR_MPB_LEN (1)
130 #define SSR_TEND_POS (2)
131 #define SSR_TEND_LEN (1)
132 #define SSR_PER_POS (3)
133 #define SSR_PER_LEN (1)
134 #define SSR_FER_POS (4)
135 #define SSR_FER_LEN (1)
136 #define SSR_ORER_POS (5)
137 #define SSR_ORER_LEN (1)
138 #define SSR_RDRF_POS (6)
139 #define SSR_RDRF_LEN (1)
140 #define SSR_TDRE_POS (7)
141 #define SSR_TDRE_LEN (1)
142
143 /**
144 * SEMR (Serial Extended Mode Register)
145 *
146 * - ACS0[0..1]: Asynchronous Mode Clock Source Select
147 * - PADIS[1..2]: Preamble function Disable
148 * - BRME[2..3]: Bit Rate Modulation Enable
149 * - ABCSE[3..4]: Asynchronous Mode Extended Base Clock Select
150 * - ABCS[4..5]: Asynchronous Mode Base Clock Select
151 * - NFEN[5..6]: Digital Noise Filter Function Enable
152 * - BGDM[6..7]: Baud Rate Generator Double-Speed Mode Select
153 * - RXDESEL[7..8]: Asynchronous Start Bit Edge Detection Select
154 */
155 #define SEMR_ACS0_POS (0)
156 #define SEMR_ACS0_LEN (1)
157 #define SEMR_PADIS_POS (1)
158 #define SEMR_PADIS_LEN (1)
159 #define SEMR_BRME_POS (2)
160 #define SEMR_BRME_LEN (1)
161 #define SEMR_ABCSE_POS (3)
162 #define SEMR_ABCSE_LEN (1)
163 #define SEMR_ABCS_POS (4)
164 #define SEMR_ABCS_LEN (1)
165 #define SEMR_NFEN_POS (5)
166 #define SEMR_NFEN_LEN (1)
167 #define SEMR_BGDM_POS (6)
168 #define SEMR_BGDM_LEN (1)
169 #define SEMR_RXDESEL_POS (7)
170 #define SEMR_RXDESEL_LEN (1)
171
172 /**
173 * LSR (Line Status Register)
174 *
175 * - ORER[0..1]: Overrun Error Flag
176 * - FNUM[2..7]: Framing Error Count
177 * - PNUM[8..13]: Parity Error Count
178 */
179 #define LSR_ORER_POS (0)
180 #define LSR_ORER_LEN (1)
181 #define LSR_FNUM_POS (2)
182 #define LSR_FNUM_LEN (5)
183 #define LSR_PNUM_POS (8)
184 #define LSR_PNUM_LEN (5)
185
uart_ra_read_8(const struct device * dev,uint32_t offs)186 static uint8_t uart_ra_read_8(const struct device *dev, uint32_t offs)
187 {
188 const struct uart_ra_cfg *config = dev->config;
189
190 return sys_read8(config->regs + offs);
191 }
192
uart_ra_write_8(const struct device * dev,uint32_t offs,uint8_t value)193 static void uart_ra_write_8(const struct device *dev, uint32_t offs, uint8_t value)
194 {
195 const struct uart_ra_cfg *config = dev->config;
196
197 sys_write8(value, config->regs + offs);
198 }
199
uart_ra_read_16(const struct device * dev,uint32_t offs)200 static uint16_t uart_ra_read_16(const struct device *dev, uint32_t offs)
201 {
202 const struct uart_ra_cfg *config = dev->config;
203
204 return sys_read16(config->regs + offs);
205 }
206
uart_ra_write_16(const struct device * dev,uint32_t offs,uint16_t value)207 static void uart_ra_write_16(const struct device *dev, uint32_t offs, uint16_t value)
208 {
209 const struct uart_ra_cfg *config = dev->config;
210
211 sys_write16(value, config->regs + offs);
212 }
213
uart_ra_set_baudrate(const struct device * dev,uint32_t baud_rate)214 static void uart_ra_set_baudrate(const struct device *dev, uint32_t baud_rate)
215 {
216 struct uart_ra_data *data = dev->data;
217 uint8_t reg_val;
218
219 reg_val = uart_ra_read_8(dev, SEMR);
220 reg_val |= (REG_MASK(SEMR_BGDM) | REG_MASK(SEMR_ABCS));
221 reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE));
222 uart_ra_write_8(dev, SEMR, reg_val);
223
224 reg_val = (data->clk_rate / (8 * data->current_config.baudrate)) - 1;
225 uart_ra_write_8(dev, BRR, reg_val);
226 }
227
uart_ra_poll_in(const struct device * dev,unsigned char * p_char)228 static int uart_ra_poll_in(const struct device *dev, unsigned char *p_char)
229 {
230 struct uart_ra_data *data = dev->data;
231 int ret = 0;
232
233 k_spinlock_key_t key = k_spin_lock(&data->lock);
234
235 /* If interrupts are enabled, return -EINVAL */
236 if ((uart_ra_read_8(dev, SCR) & REG_MASK(SCR_RIE))) {
237 ret = -EINVAL;
238 goto unlock;
239 }
240
241 if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
242 ret = -1;
243 goto unlock;
244 }
245
246 *p_char = uart_ra_read_8(dev, RDR);
247 unlock:
248 k_spin_unlock(&data->lock, key);
249
250 return ret;
251 }
252
uart_ra_poll_out(const struct device * dev,unsigned char out_char)253 static void uart_ra_poll_out(const struct device *dev, unsigned char out_char)
254 {
255 struct uart_ra_data *data = dev->data;
256 uint8_t reg_val;
257 k_spinlock_key_t key = k_spin_lock(&data->lock);
258
259 while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
260 !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
261 ;
262 }
263
264 /* If interrupts are enabled, temporarily disable them */
265 reg_val = uart_ra_read_8(dev, SCR);
266 uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE));
267
268 uart_ra_write_8(dev, TDR, out_char);
269 while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
270 !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
271 ;
272 }
273
274 uart_ra_write_8(dev, SCR, reg_val);
275 k_spin_unlock(&data->lock, key);
276 }
277
uart_ra_err_check(const struct device * dev)278 static int uart_ra_err_check(const struct device *dev)
279 {
280 struct uart_ra_data *data = dev->data;
281
282 uint8_t reg_val;
283 int errors = 0;
284 k_spinlock_key_t key;
285
286 key = k_spin_lock(&data->lock);
287 reg_val = uart_ra_read_8(dev, SSR);
288
289 if (reg_val & REG_MASK(SSR_PER)) {
290 errors |= UART_ERROR_PARITY;
291 }
292
293 if (reg_val & REG_MASK(SSR_FER)) {
294 errors |= UART_ERROR_FRAMING;
295 }
296
297 if (reg_val & REG_MASK(SSR_ORER)) {
298 errors |= UART_ERROR_OVERRUN;
299 }
300
301 reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER));
302 uart_ra_write_8(dev, SSR, reg_val);
303
304 k_spin_unlock(&data->lock, key);
305
306 return errors;
307 }
308
uart_ra_configure(const struct device * dev,const struct uart_config * cfg)309 static int uart_ra_configure(const struct device *dev, const struct uart_config *cfg)
310 {
311 struct uart_ra_data *data = dev->data;
312
313 uint16_t reg_val;
314 k_spinlock_key_t key;
315
316 if (cfg->parity != UART_CFG_PARITY_NONE || cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
317 cfg->data_bits != UART_CFG_DATA_BITS_8 || cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
318 return -ENOTSUP;
319 }
320
321 key = k_spin_lock(&data->lock);
322
323 /* Disable Transmit and Receive */
324 reg_val = uart_ra_read_8(dev, SCR);
325 reg_val &= ~(REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
326 uart_ra_write_8(dev, SCR, reg_val);
327
328 /* Resetting Errors Registers */
329 reg_val = uart_ra_read_8(dev, SSR);
330 reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER) |
331 REG_MASK(SSR_RDRF) | REG_MASK(SSR_TDRE));
332 uart_ra_write_8(dev, SSR, reg_val);
333
334 reg_val = uart_ra_read_16(dev, LSR);
335 reg_val &= ~(REG_MASK(LSR_ORER));
336 uart_ra_write_16(dev, LSR, reg_val);
337
338 /* Select internal clock */
339 reg_val = uart_ra_read_8(dev, SCR);
340 reg_val &= ~(REG_MASK(SCR_CKE));
341 uart_ra_write_8(dev, SCR, reg_val);
342
343 /* Serial Configuration (8N1) & Clock divider selection */
344 reg_val = uart_ra_read_8(dev, SMR);
345 reg_val &= ~(REG_MASK(SMR_CM) | REG_MASK(SMR_CHR) | REG_MASK(SMR_PE) | REG_MASK(SMR_PM) |
346 REG_MASK(SMR_STOP) | REG_MASK(SMR_CKS));
347 uart_ra_write_8(dev, SMR, reg_val);
348
349 /* Set baudrate */
350 uart_ra_set_baudrate(dev, cfg->baudrate);
351
352 /* Enable Transmit & Receive + disable Interrupts */
353 reg_val = uart_ra_read_8(dev, SCR);
354 reg_val |= (REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
355 reg_val &=
356 ~(REG_MASK(SCR_TIE) | REG_MASK(SCR_RIE) | REG_MASK(SCR_MPIE) | REG_MASK(SCR_TEIE));
357 uart_ra_write_8(dev, SCR, reg_val);
358
359 data->current_config = *cfg;
360
361 k_spin_unlock(&data->lock, key);
362
363 return 0;
364 }
365
366 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
uart_ra_config_get(const struct device * dev,struct uart_config * cfg)367 static int uart_ra_config_get(const struct device *dev, struct uart_config *cfg)
368 {
369 struct uart_ra_data *data = dev->data;
370
371 *cfg = data->current_config;
372
373 return 0;
374 }
375 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
376
uart_ra_init(const struct device * dev)377 static int uart_ra_init(const struct device *dev)
378 {
379 const struct uart_ra_cfg *config = dev->config;
380 struct uart_ra_data *data = dev->data;
381 int ret;
382
383 /* Configure dt provided device signals when available */
384 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
385 if (ret < 0) {
386 return ret;
387 }
388
389 if (!device_is_ready(config->clock_dev)) {
390 return -ENODEV;
391 }
392
393 ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_id);
394 if (ret < 0) {
395 return ret;
396 }
397
398 ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->clock_id,
399 &data->clk_rate);
400 if (ret < 0) {
401 return ret;
402 }
403
404 ret = uart_ra_configure(dev, &data->current_config);
405 if (ret != 0) {
406 return ret;
407 }
408
409 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
410 ret = config->irq_config_func(dev);
411 if (ret != 0) {
412 return ret;
413 }
414 #endif
415
416 return 0;
417 }
418
419 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
420
uart_ra_irq_is_enabled(const struct device * dev,uint32_t irq)421 static bool uart_ra_irq_is_enabled(const struct device *dev, uint32_t irq)
422 {
423 return uart_ra_read_8(dev, SCR) & irq;
424 }
425
uart_ra_fifo_fill(const struct device * dev,const uint8_t * tx_data,int len)426 static int uart_ra_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
427 {
428 struct uart_ra_data *data = dev->data;
429 uint8_t reg_val;
430 k_spinlock_key_t key;
431
432 if (len <= 0 || tx_data == NULL) {
433 return 0;
434 }
435
436 key = k_spin_lock(&data->lock);
437 reg_val = uart_ra_read_8(dev, SCR);
438 reg_val &= ~(REG_MASK(SCR_TIE));
439 uart_ra_write_8(dev, SCR, reg_val);
440
441 uart_ra_write_8(dev, TDR, tx_data[0]);
442
443 reg_val |= REG_MASK(SCR_TIE);
444 uart_ra_write_8(dev, SCR, reg_val);
445
446 k_spin_unlock(&data->lock, key);
447
448 return 1;
449 }
450
uart_ra_fifo_read(const struct device * dev,uint8_t * rx_data,const int size)451 static int uart_ra_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
452 {
453 uint8_t data;
454
455 if (size <= 0) {
456 return 0;
457 }
458
459 if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
460 return 0;
461 }
462
463 data = uart_ra_read_8(dev, RDR);
464
465 if (rx_data) {
466 rx_data[0] = data;
467 }
468
469 return 1;
470 }
471
uart_ra_irq_tx_enable(const struct device * dev)472 static void uart_ra_irq_tx_enable(const struct device *dev)
473 {
474 struct uart_ra_data *data = dev->data;
475 k_spinlock_key_t key;
476 uint16_t reg_val;
477
478 key = k_spin_lock(&data->lock);
479
480 reg_val = uart_ra_read_8(dev, SCR);
481 reg_val |= (REG_MASK(SCR_TIE));
482 uart_ra_write_8(dev, SCR, reg_val);
483
484 irq_enable(data->irqn[UART_RA_INT_TXI]);
485
486 k_spin_unlock(&data->lock, key);
487 }
488
uart_ra_irq_tx_disable(const struct device * dev)489 static void uart_ra_irq_tx_disable(const struct device *dev)
490 {
491 struct uart_ra_data *data = dev->data;
492 k_spinlock_key_t key;
493 uint16_t reg_val;
494
495 key = k_spin_lock(&data->lock);
496
497 reg_val = uart_ra_read_8(dev, SCR);
498 reg_val &= ~(REG_MASK(SCR_TIE));
499 uart_ra_write_8(dev, SCR, reg_val);
500
501 irq_disable(data->irqn[UART_RA_INT_TXI]);
502
503 k_spin_unlock(&data->lock, key);
504 }
505
uart_ra_irq_tx_ready(const struct device * dev)506 static int uart_ra_irq_tx_ready(const struct device *dev)
507 {
508 const uint8_t reg_val = uart_ra_read_8(dev, SSR);
509 const uint8_t mask = REG_MASK(SSR_TEND) & REG_MASK(SSR_TDRE);
510
511 return (reg_val & mask) == mask;
512 }
513
uart_ra_irq_rx_enable(const struct device * dev)514 static void uart_ra_irq_rx_enable(const struct device *dev)
515 {
516 struct uart_ra_data *data = dev->data;
517 k_spinlock_key_t key;
518 uint16_t reg_val;
519
520 key = k_spin_lock(&data->lock);
521
522 reg_val = uart_ra_read_8(dev, SCR);
523 reg_val |= REG_MASK(SCR_RIE);
524 uart_ra_write_8(dev, SCR, reg_val);
525
526 irq_enable(data->irqn[UART_RA_INT_RXI]);
527
528 k_spin_unlock(&data->lock, key);
529 }
530
uart_ra_irq_rx_disable(const struct device * dev)531 static void uart_ra_irq_rx_disable(const struct device *dev)
532 {
533 struct uart_ra_data *data = dev->data;
534 k_spinlock_key_t key;
535 uint16_t reg_val;
536
537 key = k_spin_lock(&data->lock);
538
539 reg_val = uart_ra_read_8(dev, SCR);
540 reg_val &= ~REG_MASK(SCR_RIE);
541 uart_ra_write_8(dev, SCR, reg_val);
542
543 irq_disable(data->irqn[UART_RA_INT_RXI]);
544
545 k_spin_unlock(&data->lock, key);
546 }
547
uart_ra_irq_rx_ready(const struct device * dev)548 static int uart_ra_irq_rx_ready(const struct device *dev)
549 {
550 return !!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF));
551 }
552
uart_ra_irq_err_enable(const struct device * dev)553 static void uart_ra_irq_err_enable(const struct device *dev)
554 {
555 struct uart_ra_data *data = dev->data;
556
557 irq_enable(data->irqn[UART_RA_INT_ERI]);
558 }
559
uart_ra_irq_err_disable(const struct device * dev)560 static void uart_ra_irq_err_disable(const struct device *dev)
561 {
562 struct uart_ra_data *data = dev->data;
563
564 irq_disable(data->irqn[UART_RA_INT_ERI]);
565 }
566
uart_ra_irq_is_pending(const struct device * dev)567 static int uart_ra_irq_is_pending(const struct device *dev)
568 {
569 return (uart_ra_irq_rx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_RIE))) ||
570 (uart_ra_irq_tx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_TIE)));
571 }
572
uart_ra_irq_update(const struct device * dev)573 static int uart_ra_irq_update(const struct device *dev)
574 {
575 return 1;
576 }
577
uart_ra_irq_callback_set(const struct device * dev,uart_irq_callback_user_data_t cb,void * cb_data)578 static void uart_ra_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
579 void *cb_data)
580 {
581 struct uart_ra_data *data = dev->data;
582
583 data->callback = cb;
584 data->cb_data = cb_data;
585 }
586
587 /**
588 * @brief Interrupt service routine.
589 *
590 * This simply calls the callback function, if one exists.
591 *
592 * @param arg Argument to ISR.
593 */
uart_ra_isr(const struct device * dev)594 static inline void uart_ra_isr(const struct device *dev)
595 {
596 struct uart_ra_data *data = dev->data;
597
598 if (data->callback) {
599 data->callback(dev, data->cb_data);
600 }
601 }
602
uart_ra_isr_rxi(const void * param)603 static void uart_ra_isr_rxi(const void *param)
604 {
605 const struct device *dev = param;
606 struct uart_ra_data *data = dev->data;
607
608 uart_ra_isr(dev);
609 ra_icu_clear_int_flag(data->irqn[UART_RA_INT_RXI]);
610 }
611
uart_ra_isr_txi(const void * param)612 static void uart_ra_isr_txi(const void *param)
613 {
614 const struct device *dev = param;
615 struct uart_ra_data *data = dev->data;
616
617 uart_ra_isr(dev);
618 ra_icu_clear_int_flag(data->irqn[UART_RA_INT_TXI]);
619 }
620
uart_ra_isr_eri(const void * param)621 static void uart_ra_isr_eri(const void *param)
622 {
623 const struct device *dev = param;
624 struct uart_ra_data *data = dev->data;
625
626 uart_ra_isr(dev);
627 ra_icu_clear_int_flag(data->irqn[UART_RA_INT_ERI]);
628 }
629
630 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
631
632 static DEVICE_API(uart, uart_ra_driver_api) = {
633 .poll_in = uart_ra_poll_in,
634 .poll_out = uart_ra_poll_out,
635 .err_check = uart_ra_err_check,
636 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
637 .configure = uart_ra_configure,
638 .config_get = uart_ra_config_get,
639 #endif
640 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
641 .fifo_fill = uart_ra_fifo_fill,
642 .fifo_read = uart_ra_fifo_read,
643 .irq_tx_enable = uart_ra_irq_tx_enable,
644 .irq_tx_disable = uart_ra_irq_tx_disable,
645 .irq_tx_ready = uart_ra_irq_tx_ready,
646 .irq_rx_enable = uart_ra_irq_rx_enable,
647 .irq_rx_disable = uart_ra_irq_rx_disable,
648 .irq_rx_ready = uart_ra_irq_rx_ready,
649 .irq_err_enable = uart_ra_irq_err_enable,
650 .irq_err_disable = uart_ra_irq_err_disable,
651 .irq_is_pending = uart_ra_irq_is_pending,
652 .irq_update = uart_ra_irq_update,
653 .irq_callback_set = uart_ra_irq_callback_set,
654 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
655 };
656
657 /* Device Instantiation */
658 #define UART_RA_INIT_CFG(n) \
659 PINCTRL_DT_DEFINE(DT_INST_PARENT(n)); \
660 static const struct uart_ra_cfg uart_ra_cfg_##n = { \
661 .regs = DT_REG_ADDR(DT_INST_PARENT(n)), \
662 .clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))), \
663 .clock_id = \
664 { \
665 .mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp), \
666 .stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, stop_bit), \
667 }, \
668 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)), \
669 IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, \
670 (.irq_config_func = irq_config_func_##n,))}
671
672 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
673
674 #define RA_IRQ_CONNECT_DYNAMIC(n, name, dev, isr) \
675 ra_icu_irq_connect_dynamic(DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, irq), \
676 DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, priority), isr, dev, \
677 DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, flags));
678
679 #define RA_IRQ_DISCONNECT_DYNAMIC(n, name, dev, isr) \
680 ra_icu_irq_disconnect_dynamic(irqn, 0, NULL, NULL, 0)
681
682 #define UART_RA_CONFIG_FUNC(n) \
683 static int irq_config_func_##n(const struct device *dev) \
684 { \
685 struct uart_ra_data *data = dev->data; \
686 int irqn; \
687 \
688 irqn = RA_IRQ_CONNECT_DYNAMIC(n, rxi, dev, uart_ra_isr_rxi); \
689 if (irqn < 0) { \
690 return irqn; \
691 } \
692 data->irqn[UART_RA_INT_RXI] = irqn; \
693 irqn = RA_IRQ_CONNECT_DYNAMIC(n, txi, dev, uart_ra_isr_txi); \
694 if (irqn < 0) { \
695 goto err_txi; \
696 } \
697 data->irqn[UART_RA_INT_TXI] = irqn; \
698 irqn = RA_IRQ_CONNECT_DYNAMIC(n, eri, dev, uart_ra_isr_eri); \
699 if (irqn < 0) { \
700 goto err_eri; \
701 } \
702 data->irqn[UART_RA_INT_ERI] = irqn; \
703 return 0; \
704 \
705 err_eri: \
706 RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_TXI], eri, dev, uart_ra_isr_eri); \
707 err_txi: \
708 RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_RXI], txi, dev, uart_ra_isr_txi); \
709 \
710 return irqn; \
711 }
712 #else
713 #define UART_RA_CONFIG_FUNC(n)
714 #endif
715
716 #define UART_RA_INIT(n) \
717 UART_RA_CONFIG_FUNC(n) \
718 UART_RA_INIT_CFG(n); \
719 \
720 static struct uart_ra_data uart_ra_data_##n = { \
721 .current_config = { \
722 .baudrate = DT_INST_PROP(n, current_speed), \
723 .parity = UART_CFG_PARITY_NONE, \
724 .stop_bits = UART_CFG_STOP_BITS_1, \
725 .data_bits = UART_CFG_DATA_BITS_8, \
726 .flow_ctrl = UART_CFG_FLOW_CTRL_NONE, \
727 }, \
728 }; \
729 \
730 DEVICE_DT_INST_DEFINE(n, uart_ra_init, NULL, &uart_ra_data_##n, &uart_ra_cfg_##n, \
731 PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_ra_driver_api);
732
733 DT_INST_FOREACH_STATUS_OKAY(UART_RA_INIT)
734
