1 /* 2 * Copyright (c) 2022 Intel Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef __INTEL_DAI_DRIVER_SSP_H__ 8 #define __INTEL_DAI_DRIVER_SSP_H__ 9 10 #include <stdint.h> 11 #include <zephyr/drivers/dai.h> 12 #include "dai-params-intel-ipc3.h" 13 #include "dai-params-intel-ipc4.h" 14 15 #define DAI_INTEL_SSP_MASK(b_hi, b_lo) \ 16 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo)) 17 #define DAI_INTEL_SSP_SET_BIT(b, x) (((x) & 1) << (b)) 18 #define DAI_INTEL_SSP_SET_BITS(b_hi, b_lo, x) \ 19 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo)) 20 #define DAI_INTEL_SSP_GET_BIT(b, x) \ 21 (((x) & (1ULL << (b))) >> (b)) 22 #define DAI_INTEL_SSP_GET_BITS(b_hi, b_lo, x) \ 23 (((x) & MASK(b_hi, b_lo)) >> (b_lo)) 24 #define DAI_INTEL_SSP_IS_BIT_SET(reg, bit) (((reg >> bit) & (0x1)) != 0) 25 26 /* ssp_freq array constants */ 27 #define DAI_INTEL_SSP_NUM_FREQ 3 28 #define DAI_INTEL_SSP_MAX_FREQ_INDEX (DAI_INTEL_SSP_NUM_FREQ - 1) 29 #define DAI_INTEL_SSP_DEFAULT_IDX 1 30 31 /* the SSP port fifo depth */ 32 #define DAI_INTEL_SSP_FIFO_DEPTH 16 33 34 /* the watermark for the SSP fifo depth setting */ 35 #define DAI_INTEL_SSP_FIFO_WATERMARK 8 36 37 /* minimal SSP port delay in cycles */ 38 #define DAI_INTEL_SSP_PLATFORM_DELAY 1600 39 /* minimal SSP port delay in useconds */ 40 #define DAI_INTEL_SSP_PLATFORM_DELAY_US 42 41 #define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY 12 42 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8 43 44 /** \brief Number of SSP MCLKs available */ 45 #define DAI_INTEL_SSP_NUM_MCLK 2 46 47 #define DAI_INTEL_SSP_CLOCK_XTAL_OSCILLATOR 0x0 48 #define DAI_INTEL_SSP_CLOCK_AUDIO_CARDINAL 0x1 49 #define DAI_INTEL_SSP_CLOCK_PLL_FIXED 0x2 50 51 /* SSP register offsets */ 52 #define SSCR0 0x00 53 #define SSCR1 0x04 54 #define SSSR 0x08 55 #define SSITR 0x0C 56 #define SSDR 0x10 57 #define SSTO 0x28 58 #define SSPSP 0x2C 59 #define SSTSA 0x30 60 #define SSRSA 0x34 61 #define SSTSS 0x38 62 #define SSCR2 0x40 63 64 /* SSCR0 bits */ 65 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1) 66 #define SSCR0_DSIZE_GET(x) (((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1) 67 #define SSCR0_FRF DAI_INTEL_SSP_MASK(5, 4) 68 #define SSCR0_MOT DAI_INTEL_SSP_SET_BITS(5, 4, 0) 69 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1) 70 #define SSCR0_NAT DAI_INTEL_SSP_SET_BITS(5, 4, 2) 71 #define SSCR0_PSP DAI_INTEL_SSP_SET_BITS(5, 4, 3) 72 #define SSCR0_ECS BIT(6) 73 #define SSCR0_SSE BIT(7) 74 #define SSCR0_SCR_MASK DAI_INTEL_SSP_MASK(19, 8) 75 #define SSCR0_SCR(x) DAI_INTEL_SSP_SET_BITS(19, 8, x) 76 #define SSCR0_EDSS BIT(20) 77 #define SSCR0_NCS BIT(21) 78 #define SSCR0_RIM BIT(22) 79 #define SSCR0_TIM BIT(23) 80 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1) 81 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1) 82 #define SSCR0_ACS BIT(30) 83 #define SSCR0_MOD BIT(31) 84 85 /* SSCR1 bits */ 86 #define SSCR1_RIE BIT(0) 87 #define SSCR1_TIE BIT(1) 88 #define SSCR1_LBM BIT(2) 89 #define SSCR1_SPO BIT(3) 90 #define SSCR1_SPH BIT(4) 91 #define SSCR1_MWDS BIT(5) 92 #define SSCR1_TFT_MASK DAI_INTEL_SSP_MASK(9, 6) 93 #define SSCR1_TFT(x) DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1) 94 #define SSCR1_RFT_MASK DAI_INTEL_SSP_MASK(13, 10) 95 #define SSCR1_RFT(x) DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1) 96 #define SSCR1_EFWR BIT(14) 97 #define SSCR1_STRF BIT(15) 98 #define SSCR1_IFS BIT(16) 99 #define SSCR1_PINTE BIT(18) 100 #define SSCR1_TINTE BIT(19) 101 #define SSCR1_RSRE BIT(20) 102 #define SSCR1_TSRE BIT(21) 103 #define SSCR1_TRAIL BIT(22) 104 #define SSCR1_RWOT BIT(23) 105 #define SSCR1_SFRMDIR BIT(24) 106 #define SSCR1_SCLKDIR BIT(25) 107 #define SSCR1_ECRB BIT(26) 108 #define SSCR1_ECRA BIT(27) 109 #define SSCR1_SCFR BIT(28) 110 #define SSCR1_EBCEI BIT(29) 111 #define SSCR1_TTE BIT(30) 112 #define SSCR1_TTELP BIT(31) 113 114 #define SSCR2_TURM1 BIT(1) 115 #define SSCR2_PSPSRWFDFD BIT(3) 116 #define SSCR2_PSPSTWFDFD BIT(4) 117 #define SSCR2_SDFD BIT(14) 118 #define SSCR2_SDPM BIT(16) 119 #define SSCR2_LJDFD BIT(17) 120 #define SSCR2_MMRATF BIT(18) 121 #define SSCR2_SMTATF BIT(19) 122 #define SSCR2_SFRMEN BIT(20) 123 #define SSCR2_ACIOLBS BIT(21) 124 125 /* SSR bits */ 126 #define SSSR_TNF BIT(2) 127 #define SSSR_RNE BIT(3) 128 #define SSSR_BSY BIT(4) 129 #define SSSR_TFS BIT(5) 130 #define SSSR_RFS BIT(6) 131 #define SSSR_ROR BIT(7) 132 #define SSSR_TUR BIT(21) 133 134 /* SSPSP bits */ 135 #define SSPSP_SCMODE(x) DAI_INTEL_SSP_SET_BITS(1, 0, x) 136 #define SSPSP_SFRMP(x) DAI_INTEL_SSP_SET_BIT(2, x) 137 #define SSPSP_ETDS BIT(3) 138 #define SSPSP_STRTDLY(x) DAI_INTEL_SSP_SET_BITS(6, 4, x) 139 #define SSPSP_DMYSTRT(x) DAI_INTEL_SSP_SET_BITS(8, 7, x) 140 #define SSPSP_SFRMDLY(x) DAI_INTEL_SSP_SET_BITS(15, 9, x) 141 #define SSPSP_SFRMWDTH(x) DAI_INTEL_SSP_SET_BITS(21, 16, x) 142 #define SSPSP_DMYSTOP(x) DAI_INTEL_SSP_SET_BITS(24, 23, x) 143 #define SSPSP_DMYSTOP_BITS 2 144 #define SSPSP_DMYSTOP_MASK DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0) 145 #define SSPSP_FSRT BIT(25) 146 #define SSPSP_EDMYSTOP(x) DAI_INTEL_SSP_SET_BITS(28, 26, x) 147 148 #define SSPSP2 0x44 149 #define SSPSP2_FEP_MASK 0xff 150 151 #define SSCR3 0x48 152 #define SSIOC 0x4C 153 #define SSP_REG_MAX SSIOC 154 155 /* SSTSA bits */ 156 #define SSTSA_SSTSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x) 157 #define SSTSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0)) 158 #define SSTSA_TXEN BIT(8) 159 160 /* SSRSA bits */ 161 #define SSRSA_SSRSA(x) DAI_INTEL_SSP_SET_BITS(7, 0, x) 162 #define SSRSA_GET(x) ((x) & DAI_INTEL_SSP_MASK(7, 0)) 163 #define SSRSA_RXEN BIT(8) 164 165 /* SSCR3 bits */ 166 #define SSCR3_FRM_MST_EN BIT(0) 167 #define SSCR3_I2S_MODE_EN BIT(1) 168 #define SSCR3_I2S_FRM_POL(x) DAI_INTEL_SSP_SET_BIT(2, x) 169 #define SSCR3_I2S_TX_SS_FIX_EN BIT(3) 170 #define SSCR3_I2S_RX_SS_FIX_EN BIT(4) 171 #define SSCR3_I2S_TX_EN BIT(9) 172 #define SSCR3_I2S_RX_EN BIT(10) 173 #define SSCR3_CLK_EDGE_SEL BIT(12) 174 #define SSCR3_STRETCH_TX BIT(14) 175 #define SSCR3_STRETCH_RX BIT(15) 176 #define SSCR3_MST_CLK_EN BIT(16) 177 #define SSCR3_SYN_FIX_EN BIT(17) 178 179 /* SSCR4 bits */ 180 #define SSCR4_TOT_FRM_PRD(x) ((x) << 7) 181 182 /* SSCR5 bits */ 183 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1) 184 #define SSCR5_FRM_POLARITY(x) DAI_INTEL_SSP_SET_BIT(0, x) 185 186 /* SFIFOTT bits */ 187 #define SFIFOTT_TX(x) ((x) - 1) 188 #define SFIFOTT_RX(x) (((x) - 1) << 16) 189 190 /* SFIFOL bits */ 191 #define SFIFOL_TFL(x) ((x) & 0xFFFF) 192 #define SFIFOL_RFL(x) ((x) >> 16) 193 194 #define SSTSA_TSEN BIT(8) 195 #define SSRSA_RSEN BIT(8) 196 197 #define SSCR3_TFL_MASK DAI_INTEL_SSP_MASK(5, 0) 198 #define SSCR3_RFL_MASK DAI_INTEL_SSP_MASK(13, 8) 199 #define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0)) 200 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0)) 201 #define SSCR3_TX(x) DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1) 202 #define SSCR3_RX(x) DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1) 203 204 #define SSIOC_TXDPDEB BIT(1) 205 #define SSIOC_SFCR BIT(4) 206 #define SSIOC_SCOE BIT(5) 207 208 /* For 8000 Hz rate one sample is transmitted within 125us */ 209 #define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125 210 211 /* SSP flush retry counts maximum */ 212 #define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX 16 213 214 #define SSP_CLK_MCLK_ES_REQ BIT(0) 215 #define SSP_CLK_MCLK_ACTIVE BIT(1) 216 #define SSP_CLK_BCLK_ES_REQ BIT(2) 217 #define SSP_CLK_BCLK_ACTIVE BIT(3) 218 219 #define I2SLCTL_OFFSET 0x04 220 221 #if defined(CONFIG_SOC_INTEL_ACE15_MTPM) || defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS) 222 #define I2SLCTL_SPA(x) BIT(0 + x) 223 #define I2SLCTL_CPA(x) BIT(8 + x) 224 #elif defined(CONFIG_SOC_INTEL_ACE20_LNL) 225 #define I2SLCTL_OFLEN BIT(4) 226 #define I2SLCTL_SPA(x) BIT(16 + x) 227 #define I2SLCTL_CPA(x) BIT(23 + x) 228 #define PCMS0CM_OFFSET 0x16 229 #define PCMS1CM_OFFSET 0x1A 230 #else 231 #error "Missing ssp definitions" 232 #endif 233 234 #define I2CLCTL_MLCS(x) DAI_INTEL_SSP_SET_BITS(30, 27, x) 235 #define SHIM_CLKCTL 0x78 236 #define SHIM_CLKCTL_I2SFDCGB(x) BIT(20 + x) 237 #define SHIM_CLKCTL_I2SEFDCGB(x) BIT(18 + x) 238 239 #ifdef CONFIG_SOC_SERIES_INTEL_ACE 240 /** \brief Offset of MCLK Divider Control Register. */ 241 #define MN_MDIVCTRL 0x100 242 243 /** \brief Offset of MCLK Divider x Ratio Register. */ 244 #define MN_MDIVR(x) (0x180 + (x) * 0x4) 245 #else 246 #define MN_MDIVCTRL 0x0 247 #define MN_MDIVR(x) (0x80 + (x) * 0x4) 248 #endif 249 250 /** \brief Enables the output of MCLK Divider. */ 251 #define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x) 252 253 /** \brief Bits for setting MCLK source clock. */ 254 #define MCDSS(x) DAI_INTEL_SSP_SET_BITS(17, 16, x) 255 256 /** \brief Offset of BCLK x M/N Divider M Value Register. */ 257 #define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0) 258 259 /** \brief Offset of BCLK x M/N Divider N Value Register. */ 260 #define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4) 261 262 /** \brief Bits for setting M/N source clock. */ 263 #define MNDSS(x) DAI_INTEL_SSP_SET_BITS(21, 20, x) 264 265 /** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */ 266 #define MN_SOURCE_CLKS_MASK 0x3 267 268 #if CONFIG_INTEL_MN 269 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly. 270 * Even in the case of M/N, the actual clock source can be XTAL, 271 * Audio cardinal clock (24.576) or 96 MHz PLL. 272 * The MN block is not really the source of clocks, but rather 273 * an intermediate component. 274 * Input for source is shared by all outputs coming from that source 275 * and once it's in use, it can be adjusted only with dividers. 276 * In order to change input, the source should not be in use, that's why 277 * it's necessary to keep track of BCLKs sources to know when it's safe 278 * to change shared input clock. 279 */ 280 enum bclk_source { 281 MN_BCLK_SOURCE_NONE = 0, /**< port is not using any clock */ 282 MN_BCLK_SOURCE_MN, /**< port is using clock driven by M/N */ 283 MN_BCLK_SOURCE_XTAL, /**< port is using XTAL directly */ 284 }; 285 #endif 286 287 struct dai_intel_ssp_mn { 288 uint32_t base; 289 /**< keep track of which MCLKs are in use to know when it's safe to 290 * change shared clock 291 */ 292 int mclk_sources_ref[DAI_INTEL_SSP_NUM_MCLK]; 293 int mclk_rate[DAI_INTEL_SSP_NUM_MCLK]; 294 int mclk_source_clock; 295 296 #if CONFIG_INTEL_MN 297 enum bclk_source bclk_sources[(CONFIG_DAI_INTEL_SSP_NUM_BASE + 298 CONFIG_DAI_INTEL_SSP_NUM_EXT)]; 299 int bclk_source_mn_clock; 300 #endif 301 302 struct k_spinlock lock; /**< lock mechanism */ 303 }; 304 305 struct dai_intel_ssp_freq_table { 306 uint32_t freq; 307 uint32_t ticks_per_msec; 308 }; 309 310 struct dai_intel_ssp_plat_fifo_data { 311 uint32_t offset; 312 uint32_t width; 313 uint32_t depth; 314 uint32_t watermark; 315 uint32_t handshake; 316 }; 317 318 struct dai_intel_ssp_plat_data { 319 uint32_t base; 320 uint32_t ip_base; 321 uint32_t shim_base; 322 #ifdef CONFIG_SOC_INTEL_ACE20_LNL 323 uint32_t hdamlssp_base; 324 uint32_t i2svss_base; 325 #endif 326 int irq; 327 const char *irq_name; 328 uint32_t flags; 329 struct dai_intel_ssp_plat_fifo_data fifo[2]; 330 struct dai_intel_ssp_mn *mn_inst; 331 struct dai_intel_ssp_freq_table *ftable; 332 uint32_t *fsources; 333 }; 334 335 struct dai_intel_ssp_pdata { 336 uint32_t sscr0; 337 uint32_t sscr1; 338 uint32_t psp; 339 uint32_t state[2]; 340 uint32_t clk_active; 341 struct dai_config config; 342 struct dai_properties props; 343 struct dai_intel_ipc3_ssp_params params; 344 }; 345 346 struct dai_intel_ssp { 347 uint32_t index; /**< index */ 348 struct k_spinlock lock; /**< locking mechanism */ 349 int sref; /**< simple ref counter, guarded by lock */ 350 struct dai_intel_ssp_plat_data plat_data; 351 void *priv_data; 352 }; 353 354 #endif 355
