1 /* SPDX-License-Identifier: BSD-3-Clause
2 *
3 * Copyright(c) 2016 Intel Corporation. All rights reserved.
4 *
5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com>
6 */
7
8 #ifndef __SOF_DRIVERS_SSP_H__
9 #define __SOF_DRIVERS_SSP_H__
10
11 #include <rtos/bit.h>
12 #include <rtos/clk.h>
13 #include <sof/lib/dai.h>
14 #include <rtos/wait.h>
15 #include <sof/trace/trace.h>
16 #include <ipc/dai.h>
17 #include <ipc/dai-intel.h>
18 #include <user/trace.h>
19
20 #include <stdint.h>
21
22 #define SSP_CLOCK_XTAL_OSCILLATOR 0x0
23 #define SSP_CLOCK_AUDIO_CARDINAL 0x1
24 #define SSP_CLOCK_PLL_FIXED 0x2
25
26 extern const struct freq_table *ssp_freq;
27 extern const uint32_t *ssp_freq_sources;
28
29 /* SSP register offsets */
30 #define SSCR0 0x00
31 #define SSCR1 0x04
32 #define SSSR 0x08
33 #define SSITR 0x0C
34 #define SSDR 0x10
35 #define SSTO 0x28
36 #define SSPSP 0x2C
37 #define SSTSA 0x30
38 #define SSRSA 0x34
39 #define SSTSS 0x38
40 #define SSCR2 0x40
41
42 extern const struct dai_driver ssp_driver;
43
44 /* SSCR0 bits */
45 #define SSCR0_DSIZE(x) SET_BITS(3, 0, (x) - 1)
46 #define SSCR0_DSIZE_GET(x) (((x) & MASK(3, 0)) + 1)
47 #define SSCR0_FRF MASK(5, 4)
48 #define SSCR0_MOT SET_BITS(5, 4, 0)
49 #define SSCR0_TI SET_BITS(5, 4, 1)
50 #define SSCR0_NAT SET_BITS(5, 4, 2)
51 #define SSCR0_PSP SET_BITS(5, 4, 3)
52 #define SSCR0_ECS BIT(6)
53 #define SSCR0_SSE BIT(7)
54 #define SSCR0_SCR_MASK MASK(19, 8)
55 #define SSCR0_SCR(x) SET_BITS(19, 8, x)
56 #define SSCR0_EDSS BIT(20)
57 #define SSCR0_NCS BIT(21)
58 #define SSCR0_RIM BIT(22)
59 #define SSCR0_TIM BIT(23)
60 #define SSCR0_FRDC(x) SET_BITS(26, 24, (x) - 1)
61 #define SSCR0_FRDC_GET(x) ((((x) & MASK(26, 24)) >> 24) + 1)
62 #define SSCR0_ACS BIT(30)
63 #define SSCR0_MOD BIT(31)
64
65 /* SSCR1 bits */
66 #define SSCR1_RIE BIT(0)
67 #define SSCR1_TIE BIT(1)
68 #define SSCR1_LBM BIT(2)
69 #define SSCR1_SPO BIT(3)
70 #define SSCR1_SPH BIT(4)
71 #define SSCR1_MWDS BIT(5)
72 #define SSCR1_TFT_MASK MASK(9, 6)
73 #define SSCR1_TFT(x) SET_BITS(9, 6, (x) - 1)
74 #define SSCR1_RFT_MASK MASK(13, 10)
75 #define SSCR1_RFT(x) SET_BITS(13, 10, (x) - 1)
76 #define SSCR1_EFWR BIT(14)
77 #define SSCR1_STRF BIT(15)
78 #define SSCR1_IFS BIT(16)
79 #define SSCR1_PINTE BIT(18)
80 #define SSCR1_TINTE BIT(19)
81 #define SSCR1_RSRE BIT(20)
82 #define SSCR1_TSRE BIT(21)
83 #define SSCR1_TRAIL BIT(22)
84 #define SSCR1_RWOT BIT(23)
85 #define SSCR1_SFRMDIR BIT(24)
86 #define SSCR1_SCLKDIR BIT(25)
87 #define SSCR1_ECRB BIT(26)
88 #define SSCR1_ECRA BIT(27)
89 #define SSCR1_SCFR BIT(28)
90 #define SSCR1_EBCEI BIT(29)
91 #define SSCR1_TTE BIT(30)
92 #define SSCR1_TTELP BIT(31)
93
94 #if CONFIG_CAVS
95 #define SSCR2_TURM1 BIT(1)
96 #define SSCR2_PSPSRWFDFD BIT(3)
97 #define SSCR2_PSPSTWFDFD BIT(4)
98 #define SSCR2_SDFD BIT(14)
99 #define SSCR2_SDPM BIT(16)
100 #define SSCR2_LJDFD BIT(17)
101 #define SSCR2_MMRATF BIT(18)
102 #define SSCR2_SMTATF BIT(19)
103 #endif
104
105 /* SSR bits */
106 #define SSSR_TNF BIT(2)
107 #define SSSR_RNE BIT(3)
108 #define SSSR_BSY BIT(4)
109 #define SSSR_TFS BIT(5)
110 #define SSSR_RFS BIT(6)
111 #define SSSR_ROR BIT(7)
112 #define SSSR_TUR BIT(21)
113
114 /* SSPSP bits */
115 #define SSPSP_SCMODE(x) SET_BITS(1, 0, x)
116 #define SSPSP_SFRMP(x) SET_BIT(2, x)
117 #define SSPSP_ETDS BIT(3)
118 #define SSPSP_STRTDLY(x) SET_BITS(6, 4, x)
119 #define SSPSP_DMYSTRT(x) SET_BITS(8, 7, x)
120 #define SSPSP_SFRMDLY(x) SET_BITS(15, 9, x)
121 #define SSPSP_SFRMWDTH(x) SET_BITS(21, 16, x)
122 #define SSPSP_DMYSTOP(x) SET_BITS(24, 23, x)
123 #define SSPSP_DMYSTOP_BITS 2
124 #define SSPSP_DMYSTOP_MASK MASK(SSPSP_DMYSTOP_BITS - 1, 0)
125 #define SSPSP_FSRT BIT(25)
126 #define SSPSP_EDMYSTOP(x) SET_BITS(28, 26, x)
127
128 #define SSPSP2 0x44
129 #define SSPSP2_FEP_MASK 0xff
130
131 #if CONFIG_CAVS
132 #define SSCR3 0x48
133 #define SSIOC 0x4C
134
135 #define SSP_REG_MAX SSIOC
136 #endif
137
138 /* SSTSA bits */
139 #define SSTSA_SSTSA(x) SET_BITS(7, 0, x)
140 #define SSTSA_GET(x) ((x) & MASK(7, 0))
141 #define SSTSA_TXEN BIT(8)
142
143 /* SSRSA bits */
144 #define SSRSA_SSRSA(x) SET_BITS(7, 0, x)
145 #define SSRSA_GET(x) ((x) & MASK(7, 0))
146 #define SSRSA_RXEN BIT(8)
147
148 /* SSCR3 bits */
149 #define SSCR3_FRM_MST_EN BIT(0)
150 #define SSCR3_I2S_MODE_EN BIT(1)
151 #define SSCR3_I2S_FRM_POL(x) SET_BIT(2, x)
152 #define SSCR3_I2S_TX_SS_FIX_EN BIT(3)
153 #define SSCR3_I2S_RX_SS_FIX_EN BIT(4)
154 #define SSCR3_I2S_TX_EN BIT(9)
155 #define SSCR3_I2S_RX_EN BIT(10)
156 #define SSCR3_CLK_EDGE_SEL BIT(12)
157 #define SSCR3_STRETCH_TX BIT(14)
158 #define SSCR3_STRETCH_RX BIT(15)
159 #define SSCR3_MST_CLK_EN BIT(16)
160 #define SSCR3_SYN_FIX_EN BIT(17)
161
162 /* SSCR4 bits */
163 #define SSCR4_TOT_FRM_PRD(x) ((x) << 7)
164
165 /* SSCR5 bits */
166 #define SSCR5_FRM_ASRT_CLOCKS(x) (((x) - 1) << 1)
167 #define SSCR5_FRM_POLARITY(x) SET_BIT(0, x)
168
169 /* SFIFOTT bits */
170 #define SFIFOTT_TX(x) ((x) - 1)
171 #define SFIFOTT_RX(x) (((x) - 1) << 16)
172
173 /* SFIFOL bits */
174 #define SFIFOL_TFL(x) ((x) & 0xFFFF)
175 #define SFIFOL_RFL(x) ((x) >> 16)
176
177 #if CONFIG_CAVS
178 #define SSTSA_TSEN BIT(8)
179 #define SSRSA_RSEN BIT(8)
180
181 #define SSCR3_TFL_MASK MASK(5, 0)
182 #define SSCR3_RFL_MASK MASK(13, 8)
183 #define SSCR3_TFL_VAL(scr3_val) (((scr3_val) >> 0) & MASK(5, 0))
184 #define SSCR3_RFL_VAL(scr3_val) (((scr3_val) >> 8) & MASK(5, 0))
185 #define SSCR3_TX(x) SET_BITS(21, 16, (x) - 1)
186 #define SSCR3_RX(x) SET_BITS(29, 24, (x) - 1)
187
188 #define SSIOC_TXDPDEB BIT(1)
189 #define SSIOC_SFCR BIT(4)
190 #define SSIOC_SCOE BIT(5)
191 #endif
192
193 #if CONFIG_CAVS
194
195 #include <rtos/clk.h>
196
197 /* max possible index in ssp_freq array */
198 #define MAX_SSP_FREQ_INDEX (NUM_SSP_FREQ - 1)
199
200 #endif
201
202 /* For 8000 Hz rate one sample is transmitted within 125us */
203 #define SSP_MAX_SEND_TIME_PER_SAMPLE 125
204
205 /* SSP flush retry counts maximum */
206 #define SSP_RX_FLUSH_RETRY_MAX 16
207
208 #define ssp_irq(ssp) \
209 ssp->plat_data.irq
210
211 #define SSP_CLK_MCLK_ES_REQ BIT(0)
212 #define SSP_CLK_MCLK_ACTIVE BIT(1)
213 #define SSP_CLK_BCLK_ES_REQ BIT(2)
214 #define SSP_CLK_BCLK_ACTIVE BIT(3)
215 #define SSP_CLK_MCLK_AON_REQ BIT(4)
216
217 /* SSP private data */
218 struct ssp_pdata {
219 uint32_t sscr0;
220 uint32_t sscr1;
221 uint32_t psp;
222 uint32_t state[2]; /* SSP_STATE_ for each direction */
223 uint32_t clk_active;
224 struct sof_ipc_dai_config config;
225 struct sof_ipc_dai_ssp_params params;
226 };
227
ssp_write(struct dai * dai,uint32_t reg,uint32_t value)228 static inline void ssp_write(struct dai *dai, uint32_t reg, uint32_t value)
229 {
230 dai_write(dai, reg, value);
231 }
232
ssp_read(struct dai * dai,uint32_t reg)233 static inline uint32_t ssp_read(struct dai *dai, uint32_t reg)
234 {
235 return dai_read(dai, reg);
236 }
237
ssp_update_bits(struct dai * dai,uint32_t reg,uint32_t mask,uint32_t value)238 static inline void ssp_update_bits(struct dai *dai, uint32_t reg, uint32_t mask,
239 uint32_t value)
240 {
241 dai_update_bits(dai, reg, mask, value);
242 }
243
244 #endif /* __SOF_DRIVERS_SSP_H__ */
245
