1 /*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 /*
8 * This header is part of mspi_dw.c extracted only for clarity.
9 * It is not supposed to be included by any file other than mspi_dw.c.
10 */
11
12 /* CTRLR0 - Control Register 0 */
13 #define CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
14 #define CTRLR0_SPI_FRF_STANDARD 0UL
15 #define CTRLR0_SPI_FRF_DUAL 1UL
16 #define CTRLR0_SPI_FRF_QUAD 2UL
17 #define CTRLR0_SPI_FRF_OCTAL 3UL
18 #define CTRLR0_TMOD_MASK GENMASK(11, 10)
19 #define CTRLR0_TMOD_TX_RX 0UL
20 #define CTRLR0_TMOD_TX 1UL
21 #define CTRLR0_TMOD_RX 2UL
22 #define CTRLR0_TMOD_EEPROM 3UL
23 #define CTRLR0_SCPOL_BIT BIT(9)
24 #define CTRLR0_SCPH_BIT BIT(8)
25 #define CTRLR0_FRF_MASK GENMASK(7, 6)
26 #define CTRLR0_FRF_SPI 0UL
27 #define CTRLR0_FRF_SSP 1UL
28 #define CTRLR0_FRF_MICROWIRE 2UL
29 #define CTRLR0_DFS_MASK GENMASK(4, 0)
30
31 /* CTRLR1- Control Register 1 */
32 #define CTRLR1_NDF_MASK GENMASK(15, 0)
33
34 /* SSIENR - SSI Enable Register */
35 #define SSIENR_SSIC_EN_BIT BIT(0)
36
37 /* TXFTLR - Transmit FIFO Threshold Level */
38 #define TXFTLR_TXFTHR_MASK GENMASK(23, 16)
39 #define TXFTLR_TFT_MASK GENMASK(7, 0)
40
41 /* RXFTLR - Receive FIFO Threshold Level */
42 #define RXFTLR_RFT_MASK GENMASK(7, 0)
43
44 /* TXFLR - Transmit FIFO Level Register */
45 #define TXFLR_TXTFL_MASK GENMASK(7, 0)
46
47 /* RXFLR - Receive FIFO Level Register */
48 #define RXFLR_RXTFL_MASK GENMASK(7, 0)
49
50 /* SR - Status Register */
51 #define SR_BUSY_BIT BIT(0)
52
53 /* IMR - Interrupt Mask Register */
54 #define IMR_TXEIM_BIT BIT(0)
55 #define IMR_TXOIM_BIT BIT(1)
56 #define IMR_RXUIM_BIT BIT(2)
57 #define IMR_RXOIM_BIT BIT(3)
58 #define IMR_RXFIM_BIT BIT(4)
59 #define IMR_MSTIM_BIT BIT(5)
60
61 /* ISR - Interrupt Status Register */
62 #define ISR_TXEIS_BIT BIT(0)
63 #define ISR_TXOIS_BIT BIT(1)
64 #define ISR_RXUIS_BIT BIT(2)
65 #define ISR_RXOIS_BIT BIT(3)
66 #define ISR_RXFIS_BIT BIT(4)
67 #define ISR_MSTIS_BIT BIT(5)
68
69 /* SPI_CTRLR0 - SPI Control Register */
70 #define SPI_CTRLR0_CLK_STRETCH_EN_BIT BIT(30)
71 #define SPI_CTRLR0_XIP_PREFETCH_EN_BIT BIT(29)
72 #define SPI_CTRLR0_XIP_MBL_BIT BIT(26)
73 #define SPI_CTRLR0_SPI_RXDS_SIG_EN_BIT BIT(25)
74 #define SPI_CTRLR0_SPI_DM_EN_BIT BIT(24)
75 #define SPI_CTRLR0_RXDS_VL_EN_BIT BIT(23)
76 #define SPI_CTRLR0_SSIC_XIP_CONT_XFER_EN_BIT BIT(21)
77 #define SPI_CTRLR0_XIP_INST_EN_BIT BIT(20)
78 #define SPI_CTRLR0_XIP_DFS_HC_BIT BIT(19)
79 #define SPI_CTRLR0_SPI_RXDS_EN_BIT BIT(18)
80 #define SPI_CTRLR0_INST_DDR_EN_BIT BIT(17)
81 #define SPI_CTRLR0_SPI_DDR_EN_BIT BIT(16)
82 #define SPI_CTRLR0_WAIT_CYCLES_MASK GENMASK(15, 11)
83 #define SPI_CTRLR0_WAIT_CYCLES_MAX BIT_MASK(5)
84 #define SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
85 #define SPI_CTRLR0_INST_L0 0UL
86 #define SPI_CTRLR0_INST_L4 1UL
87 #define SPI_CTRLR0_INST_L8 2UL
88 #define SPI_CTRLR0_INST_L16 3UL
89 #define SPI_CTRLR0_XIP_MD_BIT_EN_BIT BIT(7)
90 #define SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
91 #define SPI_CTRLR0_TRANS_TYPE_MASK GENMASK(1, 0)
92 #define SPI_CTRLR0_TRANS_TYPE_TT0 0UL
93 #define SPI_CTRLR0_TRANS_TYPE_TT1 1UL
94 #define SPI_CTRLR0_TRANS_TYPE_TT2 2UL
95 #define SPI_CTRLR0_TRANS_TYPE_TT3 3UL
96
97 /* XIP_CTRL - XIP Control Register */
98 #define XIP_CTRL_XIP_PREFETCH_EN_BIT BIT(28)
99 #define XIP_CTRL_XIP_MBL_MASK GENMASK(27, 26)
100 #define XIP_CTRL_XIP_MBL_2 0UL
101 #define XIP_CTRL_XIP_MBL_4 1UL
102 #define XIP_CTRL_XIP_MBL_8 2UL
103 #define XIP_CTRL_XIP_MBL_16 3UL
104 #define XIP_CTRL_RXDS_SIG_EN_BIT BIT(25)
105 #define XIP_CTRL_XIP_HYBERBUS_EN_BIT BIT(24)
106 #define XIP_CTRL_CONT_XFER_EN_BIT BIT(23)
107 #define XIP_CTRL_INST_EN_BIT BIT(22)
108 #define XIP_CTRL_RXDS_EN_BIT BIT(21)
109 #define XIP_CTRL_INST_DDR_EN_BIT BIT(20)
110 #define XIP_CTRL_DDR_EN_BIT BIT(19)
111 #define XIP_CTRL_DFS_HC_BIT BIT(18)
112 #define XIP_CTRL_WAIT_CYCLES_MASK GENMASK(17, 13)
113 #define XIP_CTRL_WAIT_CYCLES_MAX BIT_MASK(5)
114 #define XIP_CTRL_MD_BITS_EN_BIT BIT(12)
115 #define XIP_CTRL_INST_L_MASK GENMASK(10, 9)
116 #define XIP_CTRL_INST_L0 0UL
117 #define XIP_CTRL_INST_L4 1UL
118 #define XIP_CTRL_INST_L8 2UL
119 #define XIP_CTRL_INST_L16 3UL
120 #define XIP_CTRL_ADDR_L_MASK GENMASK(7, 4)
121 #define XIP_CTRL_TRANS_TYPE_MASK GENMASK(3, 2)
122 #define XIP_CTRL_TRANS_TYPE_TT0 0UL
123 #define XIP_CTRL_TRANS_TYPE_TT1 1UL
124 #define XIP_CTRL_TRANS_TYPE_TT2 2UL
125 #define XIP_CTRL_FRF_MASK GENMASK(1, 0)
126 #define XIP_CTRL_FRF_DUAL 1UL
127 #define XIP_CTRL_FRF_QUAD 2UL
128 #define XIP_CTRL_FRF_OCTAL 3UL
129
130 /* XIP_CTRL - XIP Control Register */
131 #define XIP_CTRL_XIP_PREFETCH_EN_BIT BIT(28)
132 #define XIP_CTRL_XIP_MBL_MASK GENMASK(27, 26)
133 #define XIP_CTRL_XIP_MBL_2 0UL
134 #define XIP_CTRL_XIP_MBL_4 1UL
135 #define XIP_CTRL_XIP_MBL_8 2UL
136 #define XIP_CTRL_XIP_MBL_16 3UL
137 #define XIP_CTRL_XIP_HYBERBUS_EN_BIT BIT(24)
138 #define XIP_CTRL_CONT_XFER_EN_BIT BIT(23)
139 #define XIP_CTRL_INST_EN_BIT BIT(22)
140 #define XIP_CTRL_RXDS_EN_BIT BIT(21)
141 #define XIP_CTRL_INST_DDR_EN_BIT BIT(20)
142 #define XIP_CTRL_DDR_EN_BIT BIT(19)
143 #define XIP_CTRL_DFS_HC_BIT BIT(18)
144
145 /* XIP_WRITE_CTRL - XIP Write Control Register */
146 #define XIP_WRITE_CTRL_WAIT_CYCLES_MASK GENMASK(20, 16)
147 #define XIP_WRITE_CTRL_WAIT_CYCLES_MAX BIT_MASK(5)
148 #define XIP_WRITE_CTRL_RXDS_SIG_EN_BIT BIT(13)
149 #define XIP_WRITE_CTRL_HYBERBUS_EN_BIT BIT(12)
150 #define XIP_WRITE_CTRL_INST_DDR_EN_BIT BIT(11)
151 #define XIP_WRITE_CTRL_SPI_DDR_EN_BIT BIT(10)
152 #define XIP_WRITE_CTRL_INST_L_MASK GENMASK(9, 8)
153 #define XIP_WRITE_CTRL_INST_L0 0UL
154 #define XIP_WRITE_CTRL_INST_L4 1UL
155 #define XIP_WRITE_CTRL_INST_L8 2UL
156 #define XIP_WRITE_CTRL_INST_L16 3UL
157 #define XIP_WRITE_CTRL_ADDR_L_MASK GENMASK(7, 4)
158 #define XIP_WRITE_CTRL_TRANS_TYPE_MASK GENMASK(3, 2)
159 #define XIP_WRITE_CTRL_TRANS_TYPE_TT0 0UL
160 #define XIP_WRITE_CTRL_TRANS_TYPE_TT1 1UL
161 #define XIP_WRITE_CTRL_TRANS_TYPE_TT2 2UL
162 #define XIP_WRITE_CTRL_FRF_MASK GENMASK(1, 0)
163 #define XIP_WRITE_CTRL_FRF_DUAL 1UL
164 #define XIP_WRITE_CTRL_FRF_QUAD 2UL
165 #define XIP_WRITE_CTRL_FRF_OCTAL 3UL
166
167 /* Register access helpers. */
168 #define USES_AUX_REG(inst) + DT_INST_PROP(inst, aux_reg_enable)
169 #define AUX_REG_INSTANCES (0 DT_INST_FOREACH_STATUS_OKAY(USES_AUX_REG))
170 #define BASE_ADDR(dev) (mm_reg_t)DEVICE_MMIO_GET(dev)
171
172 #if AUX_REG_INSTANCES != 0
aux_reg_read(const struct device * dev,uint32_t off)173 static uint32_t aux_reg_read(const struct device *dev, uint32_t off)
174 {
175 return sys_in32(BASE_ADDR(dev) + off/4);
176 }
aux_reg_write(uint32_t data,const struct device * dev,uint32_t off)177 static void aux_reg_write(uint32_t data, const struct device *dev, uint32_t off)
178 {
179 sys_out32(data, BASE_ADDR(dev) + off/4);
180 }
181 #endif
182
183 #if AUX_REG_INSTANCES != DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)
reg_read(const struct device * dev,uint32_t off)184 static uint32_t reg_read(const struct device *dev, uint32_t off)
185 {
186 return sys_read32(BASE_ADDR(dev) + off);
187 }
reg_write(uint32_t data,const struct device * dev,uint32_t off)188 static void reg_write(uint32_t data, const struct device *dev, uint32_t off)
189 {
190 sys_write32(data, BASE_ADDR(dev) + off);
191 }
192 #endif
193
194 #if AUX_REG_INSTANCES == 0
195 /* If no instance uses aux-reg access. */
196 #define DECLARE_REG_ACCESS()
197 #define DEFINE_REG_ACCESS(inst)
198 #define DEFINE_MM_REG_RD(reg, off) \
199 static inline uint32_t read_##reg(const struct device *dev) \
200 { return reg_read(dev, off); }
201 #define DEFINE_MM_REG_WR(reg, off) \
202 static inline void write_##reg(const struct device *dev, uint32_t data) \
203 { reg_write(data, dev, off); }
204
205 #elif AUX_REG_INSTANCES == DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)
206 /* If all instances use aux-reg access. */
207 #define DECLARE_REG_ACCESS()
208 #define DEFINE_REG_ACCESS(inst)
209 #define DEFINE_MM_REG_RD(reg, off) \
210 static inline uint32_t read_##reg(const struct device *dev) \
211 { return aux_reg_read(dev, off); }
212 #define DEFINE_MM_REG_WR(reg, off) \
213 static inline void write_##reg(const struct device *dev, uint32_t data) \
214 { aux_reg_write(data, dev, off); }
215
216 #else
217 /* If register access varies by instance. */
218 #define DECLARE_REG_ACCESS() \
219 uint32_t (*read)(const struct device *dev, uint32_t off); \
220 void (*write)(uint32_t data, const struct device *dev, uint32_t off)
221 #define DEFINE_REG_ACCESS(inst) \
222 COND_CODE_1(DT_INST_PROP(inst, aux_reg_enable), \
223 (.read = aux_reg_read, \
224 .write = aux_reg_write,), \
225 (.read = reg_read, \
226 .write = reg_write,))
227 #define DEFINE_MM_REG_RD(reg, off) \
228 static inline uint32_t read_##reg(const struct device *dev) \
229 { \
230 const struct mspi_dw_config *dev_config = dev->config; \
231 return dev_config->read(dev, off); \
232 }
233 #define DEFINE_MM_REG_WR(reg, off) \
234 static inline void write_##reg(const struct device *dev, uint32_t data) \
235 { \
236 const struct mspi_dw_config *dev_config = dev->config; \
237 dev_config->write(data, dev, off); \
238 }
239 #endif
240
