1 /* 2 * Copyright (c) 2023 Intel Corporation 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _ISH_DMA_H_ 8 #define _ISH_DMA_H_ 9 10 #include <sedi_driver_common.h> 11 #include "pm_regs.h" 12 13 /* DMA return codes */ 14 #define DMA_RC_OK 0 /* Success */ 15 #define DMA_RC_TO 1 /* Time out */ 16 #define DMA_RC_HW 2 /* HW error (OCP) */ 17 18 /* DMA channels */ 19 #define PAGING_CHAN 0 20 #define KERNEL_CHAN 1 21 22 #define DST_IS_DRAM BIT(0) 23 #define SRC_IS_DRAM BIT(1) 24 #define NON_SNOOP BIT(2) 25 26 /* ISH5 and on */ 27 #define RS0 0x0 28 #define RS3 0x3 29 #define RS_SRC_OFFSET 3 30 #define RS_DST_OFFSET 5 31 32 #define PAGE_SIZE 4096 33 34 /** 35 * SRAM: ISH local static ram 36 * UMA: Protected system DRAM region dedicated for ISH 37 * HOST_DRAM: OS owned buffer in system DRAM 38 */ 39 enum dma_mode { 40 SRAM_TO_SRAM = 0, 41 SRAM_TO_UMA = DST_IS_DRAM | (RS3 << RS_DST_OFFSET), 42 UMA_TO_SRAM = SRC_IS_DRAM | (RS3 << RS_SRC_OFFSET), 43 HOST_DRAM_TO_SRAM = SRC_IS_DRAM | (RS0 << RS_SRC_OFFSET), 44 SRAM_TO_HOST_DRAM = DST_IS_DRAM | (RS0 << RS_DST_OFFSET) 45 }; 46 47 /* Disable DMA engine */ 48 void ish_dma_disable(void); 49 /* Initialize DMA engine */ 50 void ish_dma_init(void); 51 52 /** 53 * Main DMA transfer function 54 * 55 * @param chan DMA channel 56 * @param dst Destination address 57 * @param src Source address 58 * @param length Transfer size 59 * @param mode Transfer mode 60 * @return DMA_RC_OK, or non-zero if error. 61 */ 62 int ish_dma_copy(uint32_t chan, uint32_t dst, uint32_t src, uint32_t length, 63 enum dma_mode mode); 64 /** 65 * Set upper 32 bits address for DRAM 66 * 67 * @param chan DMA channel 68 * @param dst_msb Destination DRAM upper 32 bits address 69 * @param src_msb Source DRAM upper 32 bits address 70 */ 71 void ish_dma_set_msb(uint32_t chan, uint32_t dst_msb, uint32_t src_msb); 72 73 /** 74 * Wait for DMA transfer finish 75 * 76 * @param chan DMA channel 77 * @return DMA_RC_OK, or non-zero if error. 78 */ 79 int ish_wait_for_dma_done(uint32_t ch); 80 81 #endif 82
