1 /**************************************************************************//** 2 * @file sys_reg.h 3 * @version V1.00 4 * @brief SYS register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SYS_REG_H__ 10 #define __SYS_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- System Manger Controller -------------------------*/ 19 /** 20 @addtogroup SYS System Manger Controller(SYS) 21 Memory Mapped Structure for SYS Controller 22 @{ */ 23 24 typedef struct 25 { 26 27 28 /** 29 * @var SYS_T::PDID 30 * Offset: 0x00 Part Device Identification Number Register 31 * --------------------------------------------------------------------------------------------------- 32 * |Bits |Field |Descriptions 33 * | :----: | :----: | :---- | 34 * |[31:0] |PDID |Part Device Identification Number (Read Only) 35 * | | |This register reflects device part number code. 36 * | | |Software can read this register to identify which device is used. 37 * @var SYS_T::RSTSTS 38 * Offset: 0x04 System Reset Status Register 39 * --------------------------------------------------------------------------------------------------- 40 * |Bits |Field |Descriptions 41 * | :----: | :----: | :---- | 42 * |[0] |PORF |POR Reset Flag 43 * | | |The POR reset flag is set by the "Reset Signal" from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source. 44 * | | |0 = No reset from POR or CHIPRST. 45 * | | |1 = Power-on Reset (POR) or CHIPRST had issued the reset signal to reset the system. 46 * | | |Note: Write 1 to clear this bit to 0. 47 * |[1] |PINRF |nRESET Pin Reset Flag 48 * | | |The nRESET pin reset flag is set by the "Reset Signal" from the nRESET Pin to indicate the previous reset source. 49 * | | |0 = No reset from nRESET pin. 50 * | | |1 = Pin nRESET had issued the reset signal to reset the system. 51 * | | |Note: Write 1 to clear this bit to 0. 52 * |[2] |WDTRF |WDT Reset Flag 53 * | | |The WDT reset flag is set by the "Reset Signal" from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source. 54 * | | |0 = No reset from watchdog timer or window watchdog timer. 55 * | | |1 = The watchdog timer or window watchdog timer had issued the reset signal to reset the system. 56 * | | |Note1: Write 1 to clear this bit to 0. 57 * | | |Note2: Watchdog Timer register RSTF(WDT_CTL[2]) bit is set if the system has been reset by WDT time-out reset. 58 * | | |Window Watchdog Timer register WWDTRF(WWDT_STATUS[1]) bit is set if the system has been reset by WWDT time-out reset. 59 * |[3] |LVRF |LVR Reset Flag 60 * | | |The LVR reset flag is set by the "Reset Signal" from the Low Voltage Reset Controller to indicate the previous reset source. 61 * | | |0 = No reset from LVR. 62 * | | |1 = LVR controller had issued the reset signal to reset the system. 63 * | | |Note: Write 1 to clear this bit to 0. 64 * |[4] |BODRF |BOD Reset Flag 65 * | | |The BOD reset flag is set by the "Reset Signal" from the Brown-out Detector to indicate the previous reset source. 66 * | | |0 = No reset from BOD. 67 * | | |1 = The BOD had issued the reset signal to reset the system. 68 * | | |Note: Write 1 to clear this bit to 0. 69 * |[5] |SYSRF |System Reset Flag 70 * | | |The system reset flag is set by the "Reset Signal" from the Cortex-M23 Core to indicate the previous reset source. 71 * | | |0 = No reset from Cortex-M23. 72 * | | |1 = The Cortex-M23 had issued the reset signal to reset the system by writing 1 to the bit SYSRESETREQ(AIRCR[2], Application Interrupt and Reset Control Register, address = 0xE000ED0C) in system control registers of Cortex-M23 core. 73 * | | |Note: Write 1 to clear this bit to 0. 74 * |[7] |CPURF |CPU Reset Flag 75 * | | |The CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex-M23 Core and Flash Memory Controller (FMC). 76 * | | |0 = No reset from CPU. 77 * | | |1 = The Cortex-M23 Core and FMC are reset by software setting CPURST to 1. 78 * | | |Note: Write 1 to clear this bit to 0. 79 * |[8] |CPULKRF |CPU Lockup Reset Flag 80 * | | |The CPULK reset flag is set by hardware if Cortex-M23 lockup happened. 81 * | | |0 = No reset from CPU lockup happened. 82 * | | |1 = The Cortex-M23 lockup happened and chip is reset. 83 * | | |Note1: Write 1 to clear this bit to 0. 84 * | | |Note2: When CPU lockup happened under ICE is connected, This flag will set to 1 but chip will not reset. 85 * @var SYS_T::IPRST0 86 * Offset: 0x08 Peripheral Reset Control Register 0 87 * --------------------------------------------------------------------------------------------------- 88 * |Bits |Field |Descriptions 89 * | :----: | :----: | :---- | 90 * |[0] |CHIPRST |Chip One-shot Reset (Write Protect) 91 * | | |Setting this bit will reset the whole chip, including Processor core and all peripherals, and this bit will automatically return to 0 after the 2 clock cycles. 92 * | | |The CHIPRST is same as the POR reset, all the chip controllers is reset and the chip setting from flash are also reload. 93 * | | |0 = Chip normal operation. 94 * | | |1 = Chip one-shot reset. 95 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 96 * |[1] |CPURST |Processor Core One-shot Reset (Write Protect) 97 * | | |Setting this bit will only reset the processor core and Flash Memory Controller(FMC), and this bit will automatically return to 0 after the 2 clock cycles. 98 * | | |0 = Processor core normal operation. 99 * | | |1 = Processor core one-shot reset. 100 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 101 * |[2] |PDMA0RST |PDMA0 Controller Reset (Write Protect) 102 * | | |Setting this bit to 1 will generate a reset signal to the PDMA0 (always secure). 103 * | | |User needs to set this bit to 0 to release from reset state. 104 * | | |0 = PDMA0 controller normal operation. 105 * | | |1 = PDMA0 controller reset. 106 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 107 * |[3] |EBIRST |EBI Controller Reset (Write Protect) 108 * | | |Set this bit to 1 will generate a reset signal to the EBI 109 * | | |User needs to set this bit to 0 to release from the reset state. 110 * | | |0 = EBI controller normal operation. 111 * | | |1 = EBI controller reset. 112 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 113 * |[4] |USBHRST |USB Host Controller Reset (Write Protect) 114 * | | |Set this bit to 1 will generate a reset signal to the USB Host. 115 * | | |User needs to set this bit to 0 to release from the reset state. 116 * | | |0 = USB Host controller normal operation. 117 * | | |1 = USB Host controller reset. 118 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 119 * |[6] |SDH0RST |SDHOST0 Controller Reset (Write Protect) 120 * | | |Setting this bit to 1 will generate a reset signal to the SDHOST0 controller 121 * | | |User needs to set this bit to 0 to release from the reset state. 122 * | | |0 = SDHOST0 controller normal operation. 123 * | | |1 = SDHOST0 controller reset. 124 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 125 * |[7] |CRCRST |CRC Calculation Controller Reset (Write Protect) 126 * | | |Set this bit to 1 will generate a reset signal to the CRC calculation controller 127 * | | |User needs to set this bit to 0 to release from the reset state. 128 * | | |0 = CRC calculation controller normal operation. 129 * | | |1 = CRC calculation controller reset. 130 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 131 * |[12] |CRPTRST |CRYPTO Controller Reset (Write Protect) 132 * | | |Setting this bit to 1 will generate a reset signal to the CRYPTO controller. 133 * | | |User needs to set this bit to 0 to release from the reset state. 134 * | | |0 = CRYPTO controller normal operation. 135 * | | |1 = CRYPTO controller reset. 136 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 137 * |[29] |PDMA1RST |PDMA1 Controller Reset (Write Protect) 138 * | | |Setting this bit to 1 will generate a reset signal to the PDMA1. 139 * | | |User needs to set this bit to 0 to release from reset state. 140 * | | |0 = PDMA1 controller normal operation. 141 * | | |1 = PDMA1 controller reset. 142 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 143 * @var SYS_T::IPRST1 144 * Offset: 0x0C Peripheral Reset Control Register 1 145 * --------------------------------------------------------------------------------------------------- 146 * |Bits |Field |Descriptions 147 * | :----: | :----: | :---- | 148 * |[1] |GPIORST |GPIO Controller Reset 149 * | | |0 = GPIO controller normal operation. 150 * | | |1 = GPIO controller reset. 151 * |[2] |TMR0RST |Timer0 Controller Reset 152 * | | |0 = Timer0 controller normal operation. 153 * | | |1 = Timer0 controller reset. 154 * |[3] |TMR1RST |Timer1 Controller Reset 155 * | | |0 = Timer1 controller normal operation. 156 * | | |1 = Timer1 controller reset. 157 * |[4] |TMR2RST |Timer2 Controller Reset 158 * | | |0 = Timer2 controller normal operation. 159 * | | |1 = Timer2 controller reset. 160 * |[5] |TMR3RST |Timer3 Controller Reset 161 * | | |0 = Timer3 controller normal operation. 162 * | | |1 = Timer3 controller reset. 163 * |[7] |ACMP01RST |Analog Comparator 0/1 Controller Reset 164 * | | |0 = Analog Comparator 0/1 controller normal operation. 165 * | | |1 = Analog Comparator 0/1 controller reset. 166 * |[8] |I2C0RST |I2C0 Controller Reset 167 * | | |0 = I2C0 controller normal operation. 168 * | | |1 = I2C0 controller reset. 169 * |[9] |I2C1RST |I2C1 Controller Reset 170 * | | |0 = I2C1 controller normal operation. 171 * | | |1 = I2C1 controller reset. 172 * |[10] |I2C2RST |I2C2 Controller Reset 173 * | | |0 = I2C2 controller normal operation. 174 * | | |1 = I2C2 controller reset. 175 * |[12] |QSPI0RST |QSPI0 Controller Reset 176 * | | |0 = QSPI0 controller normal operation. 177 * | | |1 = QSPI0 controller reset. 178 * |[13] |SPI0RST |SPI0 Controller Reset 179 * | | |0 = SPI0 controller normal operation. 180 * | | |1 = SPI0 controller reset. 181 * |[14] |SPI1RST |SPI1 Controller Reset 182 * | | |0 = SPI1 controller normal operation. 183 * | | |1 = SPI1 controller reset. 184 * |[15] |SPI2RST |SPI2 Controller Reset 185 * | | |0 = SPI2 controller normal operation. 186 * | | |1 = SPI2 controller reset. 187 * |[16] |UART0RST |UART0 Controller Reset 188 * | | |0 = UART0 controller normal operation. 189 * | | |1 = UART0 controller reset. 190 * |[17] |UART1RST |UART1 Controller Reset 191 * | | |0 = UART1 controller normal operation. 192 * | | |1 = UART1 controller reset. 193 * |[18] |UART2RST |UART2 Controller Reset 194 * | | |0 = UART2 controller normal operation. 195 * | | |1 = UART2 controller reset. 196 * |[19] |UART3RST |UART3 Controller Reset 197 * | | |0 = UART3 controller normal operation. 198 * | | |1 = UART3 controller reset. 199 * |[20] |UART4RST |UART4 Controller Reset 200 * | | |0 = UART4 controller normal operation. 201 * | | |1 = UART4 controller reset. 202 * |[21] |UART5RST |UART5 Controller Reset 203 * | | |0 = UART5 controller normal operation. 204 * | | |1 = UART5 controller reset. 205 * |[24] |CAN0RST |CAN0 Controller Reset 206 * | | |0 = CAN0 controller normal operation. 207 * | | |1 = CAN0 controller reset. 208 * |[26] |OTGRST |OTG Controller Reset 209 * | | |0 = OTG controller normal operation. 210 * | | |1 = OTG controller reset. 211 * |[27] |USBDRST |USBD Controller Reset 212 * | | |0 = USBD controller normal operation. 213 * | | |1 = USBD controller reset. 214 * |[28] |EADCRST |EADC Controller Reset 215 * | | |0 = EADC controller normal operation. 216 * | | |1 = EADC controller reset. 217 * |[29] |I2S0RST |I2S0 Controller Reset 218 * | | |0 = I2S0 controller normal operation. 219 * | | |1 = I2S0 controller reset. 220 * |[31] |TRNGRST |TRNG Controller Reset 221 * | | |0 = TRNG controller normal operation. 222 * | | |1 = TRNG controller reset. 223 * @var SYS_T::IPRST2 224 * Offset: 0x10 Peripheral Reset Control Register 2 225 * --------------------------------------------------------------------------------------------------- 226 * |Bits |Field |Descriptions 227 * | :----: | :----: | :---- | 228 * |[0] |SC0RST |SC0 Controller Reset 229 * | | |0 = SC0 controller normal operation. 230 * | | |1 = SC0 controller reset. 231 * |[1] |SC1RST |SC1 Controller Reset 232 * | | |0 = SC1 controller normal operation. 233 * | | |1 = SC1 controller reset. 234 * |[2] |SC2RST |SC2 Controller Reset 235 * | | |0 = SC2 controller normal operation. 236 * | | |1 = SC2 controller reset. 237 * |[6] |SPI3RST |SPI3 Controller Reset 238 * | | |0 = SPI3 controller normal operation. 239 * | | |1 = SPI3 controller reset. 240 * |[8] |USCI0RST |USCI0 Controller Reset 241 * | | |0 = USCI0 controller normal operation. 242 * | | |1 = USCI0 controller reset. 243 * |[9] |USCI1RST |USCI1 Controller Reset 244 * | | |0 = USCI1 controller normal operation. 245 * | | |1 = USCI1 controller reset. 246 * |[12] |DACRST |DAC Controller Reset 247 * | | |0 = DAC controller normal operation. 248 * | | |1 = DAC controller reset. 249 * |[16] |EPWM0RST |EPWM0 Controller Reset 250 * | | |0 = EPWM0 controller normal operation. 251 * | | |1 = EPWM0 controller reset. 252 * |[17] |EPWM1RST |EPWM1 Controller Reset 253 * | | |0 = EPWM1 controller normal operation. 254 * | | |1 = EPWM1 controller reset. 255 * |[18] |BPWM0RST |BPWM0 Controller Reset 256 * | | |0 = BPWM0 controller normal operation. 257 * | | |1 = BPWM0 controller reset. 258 * |[19] |BPWM1RST |BPWM1 Controller Reset 259 * | | |0 = BPWM1 controller normal operation. 260 * | | |1 = BPWM1 controller reset. 261 * |[22] |QEI0RST |QEI0 Controller Reset 262 * | | |0 = QEI0 controller normal operation. 263 * | | |1 = QEI0 controller reset. 264 * |[23] |QEI1RST |QEI1 Controller Reset 265 * | | |0 = QEI1 controller normal operation. 266 * | | |1 = QEI1 controller reset. 267 * |[26] |ECAP0RST |ECAP0 Controller Reset 268 * | | |0 = ECAP0 controller normal operation. 269 * | | |1 = ECAP0 controller reset. 270 * |[27] |ECAP1RST |ECAP1 Controller Reset 271 * | | |0 = ECAP1 controller normal operation. 272 * | | |1 = ECAP1 controller reset. 273 * @var SYS_T::BODCTL 274 * Offset: 0x18 Brown-out Detector Control Register 275 * --------------------------------------------------------------------------------------------------- 276 * |Bits |Field |Descriptions 277 * | :----: | :----: | :---- | 278 * |[0] |BODEN |Brown-out Detector Enable Bit (Write Protect) 279 * | | |The default value is set by flash controller user configuration register CBODEN (CONFIG0 [23]). 280 * | | |0 = Brown-out Detector function Disabled. 281 * | | |1 = Brown-out Detector function Enabled. 282 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 283 * |[3] |BODRSTEN |Brown-out Reset Enable Bit (Write Protect) 284 * | | |The default value is set by flash controller user configuration register CBORST(CONFIG0[20]) bit . 285 * | | |0 = Brown-out INTERRUPT function Enabled. 286 * | | |1 = Brown-out RESET function Enabled. 287 * | | |Note1: 288 * | | |While the Brown-out Detector function is enabled (BODEN high) and BOD reset function is enabled (BODRSTEN high), BOD will assert a signal to reset chip when the detected voltage is lower than the threshold (BODOUT high). 289 * | | |While the BOD function is enabled (BODEN high) and BOD interrupt function is enabled (BODRSTEN low), BOD will assert an interrupt if AVDD high.than BODVL, BOD interrupt will keep till to the BODIF set to 0. 290 * | | |BOD interrupt can be blocked by disabling the NVIC BOD interrupt or disabling BOD function (set BODEN low). 291 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 292 * |[4] |BODIF |Brown-out Detector Interrupt Flag 293 * | | |0 = Brown-out Detector does not detect any voltage draft at VDD down through or up through the voltage of BODVL setting. 294 * | | |1 = When Brown-out Detector detects the VDD is dropped down through the voltage of BODVL setting or the VDD is raised up through the voltage of BODVL setting, this bit is set to 1 and the brown-out interrupt is requested if brown-out interrupt is enabled. 295 * | | |Note: Write 1 to clear this bit to 0. 296 * |[5] |BODLPM |Brown-out Detector Low Power Mode (Write Protect) 297 * | | |0 = BOD operate in normal mode (default). 298 * | | |1 = BOD Low Power mode Enabled. 299 * | | |Note1: The BOD consumes about 100uA in normal mode, the low power mode can reduce the current to about 1/10 but slow the BOD response. 300 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 301 * |[6] |BODOUT |Brown-out Detector Output Status 302 * | | |0 = Brown-out Detector output status is 0. 303 * | | |It means the detected voltage is higher than BODVL setting or BODEN is 0. 304 * | | |1 = Brown-out Detector output status is 1. 305 * | | |It means the detected voltage is lower than BODVL setting. 306 * | | |If the BODEN is 0, BOD function disabled , this bit always responds 0. 307 * |[7] |LVREN |Low Voltage Reset Enable Bit (Write Protect) 308 * | | |The LVR function resets the chip when the input power voltage is lower than LVR circuit setting. 309 * | | |LVR function is enabled by default. 310 * | | |0 = Low Voltage Reset function Disabled. 311 * | | |1 = Low Voltage Reset function Enabled. 312 * | | |Note1: After enabling the bit, the LVR function will be active with 200us delay for LVR output stable (default). 313 * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. 314 * |[10:8] |BODDGSEL |Brown-out Detector Output De-glitch Time Select (Write Protect) 315 * | | |000 = BOD output is sampled by LIRC clock. 316 * | | |001 = 4 system clock (HCLK). 317 * | | |010 = 8 system clock (HCLK). 318 * | | |011 = 16 system clock (HCLK). 319 * | | |100 = 32 system clock (HCLK). 320 * | | |101 = 64 system clock (HCLK). 321 * | | |110 = 128 system clock (HCLK). 322 * | | |111 = 256 system clock (HCLK). 323 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 324 * |[14:12] |LVRDGSEL |LVR Output De-glitch Time Select (Write Protect) 325 * | | |000 = Without de-glitch function. 326 * | | |001 = 4 system clock (HCLK). 327 * | | |010 = 8 system clock (HCLK). 328 * | | |011 = 16 system clock (HCLK). 329 * | | |100 = 32 system clock (HCLK). 330 * | | |101 = 64 system clock (HCLK). 331 * | | |110 = 128 system clock (HCLK). 332 * | | |111 = 256 system clock (HCLK). 333 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 334 * |[18:16] |BODVL |Brown-out Detector Threshold Voltage Selection (Write Protect) 335 * | | |The default value is set by flash controller user configuration register CBOV (CONFIG0 [23:21]). 336 * | | |000 = Brown-out Detector threshold voltage is 1.6V. 337 * | | |001 = Brown-out Detector threshold voltage is 1.8V. 338 * | | |010 = Brown-out Detector threshold voltage is 2.0V. 339 * | | |011 = Brown-out Detector threshold voltage is 2.2V. 340 * | | |100 = Brown-out Detector threshold voltage is 2.4V. 341 * | | |101 = Brown-out Detector threshold voltage is 2.6V. 342 * | | |110 = Brown-out Detector threshold voltage is 2.8V. 343 * | | |111 = Brown-out Detector threshold voltage is 3.0V. 344 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 345 * @var SYS_T::IVSCTL 346 * Offset: 0x1C Internal Voltage Source Control Register 347 * --------------------------------------------------------------------------------------------------- 348 * |Bits |Field |Descriptions 349 * | :----: | :----: | :---- | 350 * |[0] |VTEMPEN |Temperature Sensor Enable Bit 351 * | | |This bit is used to enable/disable temperature sensor function. 352 * | | |0 = Temperature sensor function Disabled (default). 353 * | | |1 = Temperature sensor function Enabled. 354 * | | |Note: After this bit is set to 1, the value of temperature sensor output 355 * | | |can be obtained through GPC.9. 356 * |[1] |VBATUGEN |VBAT Unity Gain Buffer Enable Bit 357 * | | |This bit is used to enable/disable VBAT unity gain buffer function. 358 * | | |0 = VBAT unity gain buffer function Disabled (default). 359 * | | |1 = VBAT unity gain buffer function Enabled. 360 * | | |Note: After this bit is set to 1, the value of VBAT unity gain buffer output voltage can be obtained from ADC conversion result. 361 * @var SYS_T::PORCTL0 362 * Offset: 0x24 Power-on Reset Controller Register 0 363 * --------------------------------------------------------------------------------------------------- 364 * |Bits |Field |Descriptions 365 * | :----: | :----: | :---- | 366 * |[15:0] |PORMASK |Power-on Reset Mask Enable Bit (Write Protect) 367 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. 368 * | | |User can mask internal POR signal to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 369 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 370 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 371 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 372 * @var SYS_T::VREFCTL 373 * Offset: 0x28 VREF Control Register 374 * --------------------------------------------------------------------------------------------------- 375 * |Bits |Field |Descriptions 376 * | :----: | :----: | :---- | 377 * |[4:0] |VREFCTL |VREF Control Bits (Write Protect) 378 * | | |00000 = VREF is from external pin. 379 * | | |00011 = VREF is internal 1.6V. 380 * | | |00111 = VREF is internal 2.0V. 381 * | | |01011 = VREF is internal 2.5V. 382 * | | |01111 = VREF is internal 3.0V. 383 * | | |Others = Reserved. 384 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 385 * |[5] |IBIASSEL |VREF Bias Current Selection (Write Protect) 386 * | | |0 = Bias current from MEGBIAS. 387 * | | |1 = Bias current from internal. 388 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 389 * |[7:6] |PRELOADSEL|Pre-load Timing Selection (Write Protect) 390 * | | |00 = pre-load time is 60us for 0.1uF Capacitor. 391 * | | |01 = pre-load time is 310us for 1uF Capacitor. 392 * | | |10 = pre-load time is 1270us for 4.7uF Capacitor. 393 * | | |11 = pre-load time is 2650us for 10uF Capacitor. 394 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 395 * @var SYS_T::USBPHY 396 * Offset: 0x2C USB PHY Control Register 397 * --------------------------------------------------------------------------------------------------- 398 * |Bits |Field |Descriptions 399 * | :----: | :----: | :---- | 400 * |[1:0] |USBROLE |USB Role Option (Write Protect) 401 * | | |These two bits are used to select the role of USB. 402 * | | |00 = Standard USB Device mode. 403 * | | |01 = Standard USB Host mode. 404 * | | |10 = ID dependent mode. 405 * | | |11 = On-The-Go device mode (default). 406 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 407 * |[2] |SBO |Note: This bit must always be kept 1. If set to 0, the result is unpredictable. 408 * |[8] |OTGPHYEN |USB OTG PHY Enable 409 * | | |This bit is used to enable/disable OTG PHY function. 410 * | | |0 = OTG PHY function Disabled (default). 411 * | | |1 = OTG PHY function Enabled. 412 * @var SYS_T::GPA_MFPL 413 * Offset: 0x30 GPIOA Low Byte Multiple Function Control Register 414 * --------------------------------------------------------------------------------------------------- 415 * |Bits |Field |Descriptions 416 * | :----: | :----: | :---- | 417 * |[3:0] |PA0MFP |PA.0 Multi-function Pin Selection 418 * |[7:4] |PA1MFP |PA.1 Multi-function Pin Selection 419 * |[11:8] |PA2MFP |PA.2 Multi-function Pin Selection 420 * |[15:12] |PA3MFP |PA.3 Multi-function Pin Selection 421 * |[19:16] |PA4MFP |PA.4 Multi-function Pin Selection 422 * |[23:20] |PA5MFP |PA.5 Multi-function Pin Selection 423 * |[27:24] |PA6MFP |PA.6 Multi-function Pin Selection 424 * |[31:28] |PA7MFP |PA.7 Multi-function Pin Selection 425 * @var SYS_T::GPA_MFPH 426 * Offset: 0x34 GPIOA High Byte Multiple Function Control Register 427 * --------------------------------------------------------------------------------------------------- 428 * |Bits |Field |Descriptions 429 * | :----: | :----: | :---- | 430 * |[3:0] |PA8MFP |PA.8 Multi-function Pin Selection 431 * |[7:4] |PA9MFP |PA.9 Multi-function Pin Selection 432 * |[11:8] |PA10MFP |PA.10 Multi-function Pin Selection 433 * |[15:12] |PA11MFP |PA.11 Multi-function Pin Selection 434 * |[19:16] |PA12MFP |PA.12 Multi-function Pin Selection 435 * |[23:20] |PA13MFP |PA.13 Multi-function Pin Selection 436 * |[27:24] |PA14MFP |PA.14 Multi-function Pin Selection 437 * |[31:28] |PA15MFP |PA.15 Multi-function Pin Selection 438 * @var SYS_T::GPB_MFPL 439 * Offset: 0x38 GPIOB Low Byte Multiple Function Control Register 440 * --------------------------------------------------------------------------------------------------- 441 * |Bits |Field |Descriptions 442 * | :----: | :----: | :---- | 443 * |[3:0] |PB0MFP |PB.0 Multi-function Pin Selection 444 * |[7:4] |PB1MFP |PB.1 Multi-function Pin Selection 445 * |[11:8] |PB2MFP |PB.2 Multi-function Pin Selection 446 * |[15:12] |PB3MFP |PB.3 Multi-function Pin Selection 447 * |[19:16] |PB4MFP |PB.4 Multi-function Pin Selection 448 * |[23:20] |PB5MFP |PB.5 Multi-function Pin Selection 449 * |[27:24] |PB6MFP |PB.6 Multi-function Pin Selection 450 * |[31:28] |PB7MFP |PB.7 Multi-function Pin Selection 451 * @var SYS_T::GPB_MFPH 452 * Offset: 0x3C GPIOB High Byte Multiple Function Control Register 453 * --------------------------------------------------------------------------------------------------- 454 * |Bits |Field |Descriptions 455 * | :----: | :----: | :---- | 456 * |[3:0] |PB8MFP |PB.8 Multi-function Pin Selection 457 * |[7:4] |PB9MFP |PB.9 Multi-function Pin Selection 458 * |[11:8] |PB10MFP |PB.10 Multi-function Pin Selection 459 * |[15:12] |PB11MFP |PB.11 Multi-function Pin Selection 460 * |[19:16] |PB12MFP |PB.12 Multi-function Pin Selection 461 * |[23:20] |PB13MFP |PB.13 Multi-function Pin Selection 462 * |[27:24] |PB14MFP |PB.14 Multi-function Pin Selection 463 * |[31:28] |PB15MFP |PB.15 Multi-function Pin Selection 464 * @var SYS_T::GPC_MFPL 465 * Offset: 0x40 GPIOC Low Byte Multiple Function Control Register 466 * --------------------------------------------------------------------------------------------------- 467 * |Bits |Field |Descriptions 468 * | :----: | :----: | :---- | 469 * |[3:0] |PC0MFP |PC.0 Multi-function Pin Selection 470 * |[7:4] |PC1MFP |PC.1 Multi-function Pin Selection 471 * |[11:8] |PC2MFP |PC.2 Multi-function Pin Selection 472 * |[15:12] |PC3MFP |PC.3 Multi-function Pin Selection 473 * |[19:16] |PC4MFP |PC.4 Multi-function Pin Selection 474 * |[23:20] |PC5MFP |PC.5 Multi-function Pin Selection 475 * |[27:24] |PC6MFP |PC.6 Multi-function Pin Selection 476 * |[31:28] |PC7MFP |PC.7 Multi-function Pin Selection 477 * @var SYS_T::GPC_MFPH 478 * Offset: 0x44 GPIOC High Byte Multiple Function Control Register 479 * --------------------------------------------------------------------------------------------------- 480 * |Bits |Field |Descriptions 481 * | :----: | :----: | :---- | 482 * |[3:0] |PC8MFP |PC.8 Multi-function Pin Selection 483 * |[7:4] |PC9MFP |PC.9 Multi-function Pin Selection 484 * |[11:8] |PC10MFP |PC.10 Multi-function Pin Selection 485 * |[15:12] |PC11MFP |PC.11 Multi-function Pin Selection 486 * |[19:16] |PC12MFP |PC.12 Multi-function Pin Selection 487 * |[23:20] |PC13MFP |PC.13 Multi-function Pin Selection 488 * @var SYS_T::GPD_MFPL 489 * Offset: 0x48 GPIOD Low Byte Multiple Function Control Register 490 * --------------------------------------------------------------------------------------------------- 491 * |Bits |Field |Descriptions 492 * | :----: | :----: | :---- | 493 * |[3:0] |PD0MFP |PD.0 Multi-function Pin Selection 494 * |[7:4] |PD1MFP |PD.1 Multi-function Pin Selection 495 * |[11:8] |PD2MFP |PD.2 Multi-function Pin Selection 496 * |[15:12] |PD3MFP |PD.3 Multi-function Pin Selection 497 * |[19:16] |PD4MFP |PD.4 Multi-function Pin Selection 498 * |[23:20] |PD5MFP |PD.5 Multi-function Pin Selection 499 * |[27:24] |PD6MFP |PD.6 Multi-function Pin Selection 500 * |[31:28] |PD7MFP |PD.7 Multi-function Pin Selection 501 * @var SYS_T::GPD_MFPH 502 * Offset: 0x4C GPIOD High Byte Multiple Function Control Register 503 * --------------------------------------------------------------------------------------------------- 504 * |Bits |Field |Descriptions 505 * | :----: | :----: | :---- | 506 * |[3:0] |PD8MFP |PD.8 Multi-function Pin Selection 507 * |[7:4] |PD9MFP |PD.9 Multi-function Pin Selection 508 * |[11:8] |PD10MFP |PD.10 Multi-function Pin Selection 509 * |[15:12] |PD11MFP |PD.11 Multi-function Pin Selection 510 * |[19:16] |PD12MFP |PD.12 Multi-function Pin Selection 511 * |[23:20] |PD13MFP |PD.13 Multi-function Pin Selection 512 * |[27:24] |PD14MFP |PD.14 Multi-function Pin Selection 513 * @var SYS_T::GPE_MFPL 514 * Offset: 0x50 GPIOE Low Byte Multiple Function Control Register 515 * --------------------------------------------------------------------------------------------------- 516 * |Bits |Field |Descriptions 517 * | :----: | :----: | :---- | 518 * |[3:0] |PE0MFP |PE.0 Multi-function Pin Selection 519 * |[7:4] |PE1MFP |PE.1 Multi-function Pin Selection 520 * |[11:8] |PE2MFP |PE.2 Multi-function Pin Selection 521 * |[15:12] |PE3MFP |PE.3 Multi-function Pin Selection 522 * |[19:16] |PE4MFP |PE.4 Multi-function Pin Selection 523 * |[23:20] |PE5MFP |PE.5 Multi-function Pin Selection 524 * |[27:24] |PE6MFP |PE.6 Multi-function Pin Selection 525 * |[31:28] |PE7MFP |PE.7 Multi-function Pin Selection 526 * @var SYS_T::GPE_MFPH 527 * Offset: 0x54 GPIOE High Byte Multiple Function Control Register 528 * --------------------------------------------------------------------------------------------------- 529 * |Bits |Field |Descriptions 530 * | :----: | :----: | :---- | 531 * |[3:0] |PE8MFP |PE.8 Multi-function Pin Selection 532 * |[7:4] |PE9MFP |PE.9 Multi-function Pin Selection 533 * |[11:8] |PE10MFP |PE.10 Multi-function Pin Selection 534 * |[15:12] |PE11MFP |PE.11 Multi-function Pin Selection 535 * |[19:16] |PE12MFP |PE.12 Multi-function Pin Selection 536 * |[23:20] |PE13MFP |PE.13 Multi-function Pin Selection 537 * |[27:24] |PE14MFP |PE.14 Multi-function Pin Selection 538 * |[31:28] |PE15MFP |PE.15 Multi-function Pin Selection 539 * @var SYS_T::GPF_MFPL 540 * Offset: 0x58 GPIOF Low Byte Multiple Function Control Register 541 * --------------------------------------------------------------------------------------------------- 542 * |Bits |Field |Descriptions 543 * | :----: | :----: | :---- | 544 * |[3:0] |PF0MFP |PF.0 Multi-function Pin Selection 545 * |[7:4] |PF1MFP |PF.1 Multi-function Pin Selection 546 * |[11:8] |PF2MFP |PF.2 Multi-function Pin Selection 547 * |[15:12] |PF3MFP |PF.3 Multi-function Pin Selection 548 * |[19:16] |PF4MFP |PF.4 Multi-function Pin Selection 549 * |[23:20] |PF5MFP |PF.5 Multi-function Pin Selection 550 * |[27:24] |PF6MFP |PF.6 Multi-function Pin Selection 551 * |[31:28] |PF7MFP |PF.7 Multi-function Pin Selection 552 * @var SYS_T::GPF_MFPH 553 * Offset: 0x5C GPIOF High Byte Multiple Function Control Register 554 * --------------------------------------------------------------------------------------------------- 555 * |Bits |Field |Descriptions 556 * | :----: | :----: | :---- | 557 * |[3:0] |PF8MFP |PF.8 Multi-function Pin Selection 558 * |[7:4] |PF9MFP |PF.9 Multi-function Pin Selection 559 * |[11:8] |PF10MFP |PF.10 Multi-function Pin Selection 560 * |[15:12] |PF11MFP |PF.11 Multi-function Pin Selection 561 * @var SYS_T::GPG_MFPL 562 * Offset: 0x60 GPIOG Low Byte Multiple Function Control Register 563 * --------------------------------------------------------------------------------------------------- 564 * |Bits |Field |Descriptions 565 * | :----: | :----: | :---- | 566 * |[11:8] |PG2MFP |PG.2 Multi-function Pin Selection 567 * |[15:12] |PG3MFP |PG.3 Multi-function Pin Selection 568 * |[19:16] |PG4MFP |PG.4 Multi-function Pin Selection 569 * @var SYS_T::GPG_MFPH 570 * Offset: 0x64 GPIOG High Byte Multiple Function Control Register 571 * --------------------------------------------------------------------------------------------------- 572 * |Bits |Field |Descriptions 573 * | :----: | :----: | :---- | 574 * |[7:4] |PG9MFP |PG.9 Multi-function Pin Selection 575 * |[11:8] |PG10MFP |PG.10 Multi-function Pin Selection 576 * |[15:12] |PG11MFP |PG.11 Multi-function Pin Selection 577 * |[19:16] |PG12MFP |PG.12 Multi-function Pin Selection 578 * |[23:20] |PG13MFP |PG.13 Multi-function Pin Selection 579 * |[27:24] |PG14MFP |PG.14 Multi-function Pin Selection 580 * |[31:28] |PG15MFP |PG.15 Multi-function Pin Selection 581 * @var SYS_T::GPH_MFPL 582 * Offset: 0x68 GPIOH Low Byte Multiple Function Control Register 583 * --------------------------------------------------------------------------------------------------- 584 * |Bits |Field |Descriptions 585 * | :----: | :----: | :---- | 586 * |[19:16] |PH4MFP |PH.4 Multi-function Pin Selection 587 * |[23:20] |PH5MFP |PH.5 Multi-function Pin Selection 588 * |[27:24] |PH6MFP |PH.6 Multi-function Pin Selection 589 * |[31:28] |PH7MFP |PH.7 Multi-function Pin Selection 590 * @var SYS_T::GPH_MFPH 591 * Offset: 0x6C GPIOH High Byte Multiple Function Control Register 592 * --------------------------------------------------------------------------------------------------- 593 * |Bits |Field |Descriptions 594 * | :----: | :----: | :---- | 595 * |[3:0] |PH8MFP |PH.8 Multi-function Pin Selection 596 * |[7:4] |PH9MFP |PH.9 Multi-function Pin Selection 597 * |[11:8] |PH10MFP |PH.10 Multi-function Pin Selection 598 * |[15:12] |PH11MFP |PH.11 Multi-function Pin Selection 599 * @var SYS_T::GPA_MFOS 600 * Offset: 0x80/0x84/0x88/0x8C/0x90/0x94/0x9C GPIOA-H Multiple Function Output Select Register 601 * --------------------------------------------------------------------------------------------------- 602 * |Bits |Field |Descriptions 603 * | :----: | :----: | :---- | 604 * |[n] |MFOSn |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select 605 * | | |This bit used to select multiple function pin output mode type for Px.n pin. 606 * | | |0 = Multiple function pin output mode type is Push-pull mode. 607 * | | |1 = Multiple function pin output mode type is Open-drain mode. 608 * | | |Note: 609 * | | |Max. n=15 for port A/B/E. 610 * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored. 611 * | | |Max. n=14 for port D. The PD.15 is ignored. 612 * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored. 613 * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored. 614 * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored. 615 * @var SYS_T::SRAMICTL 616 * Offset: 0xC0 System SRAM Interrupt Enable Control Register 617 * --------------------------------------------------------------------------------------------------- 618 * |Bits |Field |Descriptions 619 * | :----: | :----: | :---- | 620 * |[0] |PERRIEN |SRAM Parity Check Error Interrupt Enable Bit 621 * | | |0 = SRAM parity check error interrupt Disabled. 622 * | | |1 = SRAM parity check error interrupt Enabled. 623 * @var SYS_T::SRAMSTS 624 * Offset: 0xC4 System SRAM Parity Error Status Register 625 * --------------------------------------------------------------------------------------------------- 626 * |Bits |Field |Descriptions 627 * | :----: | :----: | :---- | 628 * |[0] |PERRIF |SRAM Parity Check Error Flag 629 * | | |This bit indicates the System SRAM parity error occurred. Write 1 to clear this to 0. 630 * | | |0 = No System SRAM parity error. 631 * | | |1 = System SRAM parity error occur. 632 * @var SYS_T::SRAMEADR 633 * Offset: 0xC8 System SRAM Parity Check Error Address Register 634 * --------------------------------------------------------------------------------------------------- 635 * |Bits |Field |Descriptions 636 * | :----: | :----: | :---- | 637 * |[31:0] |ERRADDR |System SRAM Parity Error Address 638 * | | |This register shows system SRAM parity error byte address. 639 * @var SYS_T::SRAMPCTL 640 * Offset: 0xDC System SRAM Power Mode Control Register 641 * --------------------------------------------------------------------------------------------------- 642 * |Bits |Field |Descriptions 643 * | :----: | :----: | :---- | 644 * |[3:0] |STACK |System SRAM Stack Position (Write Protect) 645 * | | |This field must configure the system SRAM Marco that first SRAM address accessed by CPU in power-on process. 646 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 647 * |[5:4] |RETCNT |SRAM Retention Count (Write Protect) 648 * | | |This field can configure SRAM macro retention time in unit of HIRC period. 649 * | | |00 = One HIRC period. 650 * | | |01 = Two HIRC periods. 651 * | | |10 = Three HIRC periods. 652 * | | |11 = Four HIRC periods. 653 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 654 * |[9:8] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect) 655 * | | |This field can control bank0 SRAM (32k) power mode in system power down mode for range 0x2000_0000 - 0x2000_1FFF. 656 * | | |00 = Normal mode. 657 * | | |01 = Retention mode. 658 * | | |10 = Power shut down mode. 659 * | | |11 = Reserved (Write Ignore). 660 * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD). 661 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 662 * |[11:10] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect) 663 * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2000_2000 - 0x2000_3FFF. 664 * | | |00 = Normal mode. 665 * | | |01 = Retention mode. 666 * | | |10 = Power shut down mode. 667 * | | |11 = Reserved (Write Ignore). 668 * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD). 669 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 670 * |[13:12] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect) 671 * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2004_0000 - 0x2000_5FFF. 672 * | | |00 = Normal mode. 673 * | | |01 = Retention mode. 674 * | | |10 = Power shut down mode. 675 * | | |11 = Reserved (Write Ignore). 676 * | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD). 677 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 678 * |[15:14] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect) 679 * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2006_0000 - 0x2000_7FFF. 680 * | | |00 = Normal mode. 681 * | | |01 = Retention mode. 682 * | | |10 = Power shut down mode. 683 * | | |11 = Reserved (Write Ignore). 684 * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD). 685 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 686 * |[17:16] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect) 687 * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_8000 - 0x2000_BFFF. 688 * | | |00 = Normal mode. 689 * | | |01 = Retention mode. 690 * | | |10 = Power shut down mode. 691 * | | |11 = Reserved (Write Ignore). 692 * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 693 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 694 * |[19:18] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect) 695 * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_C000 - 0x2000_FFFF. 696 * | | |00 = Normal mode. 697 * | | |01 = Retention mode. 698 * | | |10 = Power shut down mode. 699 * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 700 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 701 * |[21:20] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect) 702 * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_0000 - 0x2001_3FFF. 703 * | | |00 = Normal mode. 704 * | | |01 = Retention mode. 705 * | | |10 = Power shut down mode. 706 * | | |11 = Reserved (Write Ignore). 707 * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 708 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 709 * |[23:22] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect) 710 * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_4000 - 0x2001_7FFF 711 * | | |00 = Normal mode. 712 * | | |01 = Retention mode. 713 * | | |10 = Power shut down mode. 714 * | | |11 = Reserved (Write Ignore). 715 * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 716 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 717 * @var SYS_T::SRAMPPCT 718 * Offset: 0xE0 Peripheral SRAM Power Mode Control Register 719 * --------------------------------------------------------------------------------------------------- 720 * |Bits |Field |Descriptions 721 * | :----: | :----: | :---- | 722 * |[1:0] |CAN |CAN SRAM Power Mode Select (Write Protect) 723 * | | |This field can control CAN SRAM power mode for system enter power down mode. 724 * | | |00 = Normal mode. 725 * | | |01 = Retention mode. 726 * | | |10 = Power shut down mode. 727 * | | |11 = Reserved (Write Ignore).. 728 * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 729 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 730 * |[3:2] |USBD |USB Device SRAM Power Mode Select (Write Protect) 731 * | | |This field can control USB device SRAM power mode for system enter power down mode. 732 * | | |00 = Normal mode. 733 * | | |01 = Retention mode. 734 * | | |10 = Power shut down mode. 735 * | | |11 = Reserved (Write Ignore). 736 * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 737 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 738 * |[5:4] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect) 739 * | | |This field can control PDMA0 (always secure) SRAM power mode for system enter power down mode. 740 * | | |00 = Normal mode. 741 * | | |01 = Retention mode. 742 * | | |10 = Power shut down mode. 743 * | | |11 = Reserved (Write Ignore). 744 * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 745 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 746 * |[7:6] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect) 747 * | | |This field can control PDMA1 SRAM power mode for system enter power down mode. 748 * | | |00 = Normal mode. 749 * | | |01 = Retention mode. 750 * | | |10 = Power shut down mode. 751 * | | |11 = Reserved (Write Ignore). 752 * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 753 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 754 * |[9:8] |FMC |FMC SRAM Power Mode Select (Write Protect) 755 * | | |This field can control FMC cache SRAM power mode for system enter power down mode. 756 * | | |00 = Normal mode. 757 * | | |01 = Retention mode. 758 * | | |10 = Power shut down mode. 759 * | | |11 = Reserved (Write Ignore). 760 * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD). 761 * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. 762 * @var SYS_T::TCTL48M 763 * Offset: 0xE4 HIRC 48M Trim Control Register 764 * --------------------------------------------------------------------------------------------------- 765 * |Bits |Field |Descriptions 766 * | :----: | :----: | :---- | 767 * |[1:0] |FREQSEL |Trim Frequency Selection 768 * | | |This field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC48) auto trim. 769 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 770 * | | |00 = Disable HIRC auto trim function. 771 * | | |01 = Enable HIRC auto trim function and trim HIRC to 48 MHz. 772 * | | |10 = Reserved.. 773 * | | |11 = Reserved. 774 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 775 * | | |This field defines that trim value calculation is based on how many reference clocks. 776 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 777 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 778 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 779 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 780 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 781 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 782 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 783 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 784 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 785 * | | |00 = Trim retry count limitation is 64 loops. 786 * | | |01 = Trim retry count limitation is 128 loops. 787 * | | |10 = Trim retry count limitation is 256 loops. 788 * | | |11 = Trim retry count limitation is 512 loops. 789 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 790 * | | |0 = The trim operation is keep going if clock is inaccuracy. 791 * | | |1 = The trim operation is stopped if clock is inaccuracy. 792 * |[10] |REFCKSEL |Reference Clock Selection 793 * | | |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator. 794 * | | |1 = HIRC trim 48M reference clock is from internal USB synchronous mode. 795 * @var SYS_T::TIEN48M 796 * Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register 797 * --------------------------------------------------------------------------------------------------- 798 * |Bits |Field |Descriptions 799 * | :----: | :----: | :---- | 800 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 801 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL48M[1:0]). 802 * | | |If this bit is high and TFAILIF(SYS_TISTS48M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 803 * | | |0 = Disable TFAILIF(SYS_SYS_TISTS48M[1]) status to trigger an interrupt to CPU. 804 * | | |1 = Enable TFAILIF(SYS_SYS_TISTS48MM[1]) status to trigger an interrupt to CPU. 805 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 806 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 807 * | | |If this bit is set to1, and CLKERRIF(SYS_SYS_TISTS48M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 808 * | | |0 = Disable CLKERRIF(SYS_SYS_TISTS48M[2]) status to trigger an interrupt to CPU. 809 * | | |1 = Enable CLKERRIF(SYS_SYS_TISTS48M[2]) status to trigger an interrupt to CPU. 810 * @var SYS_T::TISTS48M 811 * Offset: 0xEC HIRC 48M Trim Interrupt Status Register 812 * --------------------------------------------------------------------------------------------------- 813 * |Bits |Field |Descriptions 814 * | :----: | :----: | :---- | 815 * |[0] |FREQLOCK |HIRC Frequency Lock Status 816 * | | |This bit indicates the HIRC frequency is locked. 817 * | | |This is a status bit and doesn't trigger any interrupt. 818 * | | |Write 1 to clear this to 0. 819 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled. 820 * | | |0 = The internal high-speed oscillator frequency doesn't lock at 48 MHz yet. 821 * | | |1 = The internal high-speed oscillator frequency locked at 48 MHz. 822 * |[1] |TFAILIF |Trim Failure Interrupt Status 823 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. 824 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL48M[1:0]) will be cleared to 00 by hardware automatically. 825 * | | |If this bit is set and TFAILIEN(SYS_TIEN48M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 826 * | | |Write 1 to clear this to 0. 827 * | | |0 = Trim value update limitation count does not reach. 828 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 829 * |[2] |CLKERRIF |Clock Error Interrupt Status 830 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 48MHz internal high speed RC oscillator (HIRC48) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 831 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL48M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL48M[8]) is set to 1. 832 * | | |If this bit is set and CLKEIEN(SYS_TIEN48M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 833 * | | |Write 1 to clear this to 0. 834 * | | |0 = Clock frequency is accuracy. 835 * | | |1 = Clock frequency is inaccuracy. 836 * @var SYS_T::TCTL12M 837 * Offset: 0xF0 HIRC 12M Trim Control Register 838 * --------------------------------------------------------------------------------------------------- 839 * |Bits |Field |Descriptions 840 * | :----: | :----: | :---- | 841 * |[1:0] |FREQSEL |Trim Frequency Selection 842 * | | |This field indicates the target frequency of 12 MHz internal high speed RC oscillator (HIRC) auto trim. 843 * | | |During auto trim operation, if clock error detected with CESTOPEN is set to 1 or trim retry limitation count reached, this field will be cleared to 00 automatically. 844 * | | |00 = Disable HIRC auto trim function. 845 * | | |01 = Enable HIRC auto trim function and trim HIRC to 12 MHz. 846 * | | |10 = Reserved.. 847 * | | |11 = Reserved. 848 * |[5:4] |LOOPSEL |Trim Calculation Loop Selection 849 * | | |This field defines that trim value calculation is based on how many reference clocks. 850 * | | |00 = Trim value calculation is based on average difference in 4 clocks of reference clock. 851 * | | |01 = Trim value calculation is based on average difference in 8 clocks of reference clock. 852 * | | |10 = Trim value calculation is based on average difference in 16 clocks of reference clock. 853 * | | |11 = Trim value calculation is based on average difference in 32 clocks of reference clock. 854 * | | |Note: For example, if LOOPSEL is set as 00, auto trim circuit will calculate trim value based on the average frequency difference in 4 clocks of reference clock. 855 * |[7:6] |RETRYCNT |Trim Value Update Limitation Count 856 * | | |This field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked. 857 * | | |Once the HIRC locked, the internal trim value update counter will be reset. 858 * | | |If the trim value update counter reached this limitation value and frequency of HIRC still doesn't lock, the auto trim operation will be disabled and FREQSEL will be cleared to 00. 859 * | | |00 = Trim retry count limitation is 64 loops. 860 * | | |01 = Trim retry count limitation is 128 loops. 861 * | | |10 = Trim retry count limitation is 256 loops. 862 * | | |11 = Trim retry count limitation is 512 loops. 863 * |[8] |CESTOPEN |Clock Error Stop Enable Bit 864 * | | |0 = The trim operation is keep going if clock is inaccuracy. 865 * | | |1 = The trim operation is stopped if clock is inaccuracy. 866 * |[10] |REFCKSEL |Reference Clock Selection 867 * | | |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator. 868 * | | |1 = HIRC trim reference clock is from internal USB synchronous mode. 869 * @var SYS_T::TIEN12M 870 * Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register 871 * --------------------------------------------------------------------------------------------------- 872 * |Bits |Field |Descriptions 873 * | :----: | :----: | :---- | 874 * |[1] |TFAILIEN |Trim Failure Interrupt Enable Bit 875 * | | |This bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_TCTL12M[1:0]). 876 * | | |If this bit is high and TFAILIF(SYS_TISTS12M[1]) is set during auto trim operation, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 877 * | | |0 = Disable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. 878 * | | |1 = Enable TFAILIF(SYS_TISTS12M[1]) status to trigger an interrupt to CPU. 879 * |[2] |CLKEIEN |Clock Error Interrupt Enable Bit 880 * | | |This bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation. 881 * | | |If this bit is set to1, and CLKERRIF(SYS_TISTS12M[2]) is set during auto trim operation, an interrupt will be triggered to notify the clock frequency is inaccuracy. 882 * | | |0 = Disable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. 883 * | | |1 = Enable CLKERRIF(SYS_TISTS12M[2]) status to trigger an interrupt to CPU. 884 * @var SYS_T::TISTS12M 885 * Offset: 0xF8 HIRC 12M Trim Interrupt Status Register 886 * --------------------------------------------------------------------------------------------------- 887 * |Bits |Field |Descriptions 888 * | :----: | :----: | :---- | 889 * |[0] |FREQLOCK |HIRC Frequency Lock Status 890 * | | |This bit indicates the HIRC frequency is locked. 891 * | | |This is a status bit and doesn't trigger any interrupt 892 * | | |Write 1 to clear this to 0 893 * | | |This bit will be set automatically, if the frequency is lock and the RC_TRIM is enabled.0 = The internal high-speed oscillator frequency doesn't lock at 12 MHz yet. 894 * | | |1 = The internal high-speed oscillator frequency locked at 12 MHz. 895 * |[1] |TFAILIF |Trim Failure Interrupt Status 896 * | | |This bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked. 897 * | | |Once this bit is set, the auto trim operation stopped and FREQSEL(SYS_TCTL12M[1:0]) will be cleared to 00 by hardware automatically. 898 * | | |If this bit is set and TFAILIEN(SYS_TIEN12M[1]) is high, an interrupt will be triggered to notify that HIRC trim value update limitation count was reached. 899 * | | |Write 1 to clear this to 0. 900 * | | |0 = Trim value update limitation count does not reach. 901 * | | |1 = Trim value update limitation count reached and HIRC frequency still not locked. 902 * |[2] |CLKERRIF |Clock Error Interrupt Status 903 * | | |When the frequency of 32.768 kHz external low speed crystal oscillator (LXT) or 12MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value, this bit will be set and to be an indicate that clock frequency is inaccuracy 904 * | | |Once this bit is set to 1, the auto trim operation stopped and FREQSEL(SYS_TICTL12M[1:0]) will be cleared to 00 by hardware automatically if CESTOPEN(SYS_TCTL12M[8]) is set to 1. 905 * | | |If this bit is set and CLKEIEN(SYS_TIEN12M[2]) is high, an interrupt will be triggered to notify the clock frequency is inaccuracy. 906 * | | |Write 1 to clear this to 0. 907 * | | |0 = Clock frequency is accuracy. 908 * | | |1 = Clock frequency is inaccuracy. 909 * @var SYS_T::REGLCTL 910 * Offset: 0x100 Register Lock Control Register 911 * --------------------------------------------------------------------------------------------------- 912 * |Bits |Field |Descriptions 913 * | :----: | :----: | :---- | 914 * |[7:0] |REGLCTL |Register Lock Control Code (Write Only) 915 * | | |Some registers have write-protection function 916 * | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field. 917 * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. 918 * |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only) 919 * | | |0 = Write-protection Enabled for writing protected registers. 920 * | | |Any write to the protected register is ignored. 921 * | | |1 = Write-protection Disabled for writing protected registers. 922 * @var SYS_T::PORCTL1 923 * Offset: 0x1EC Power-on Reset Controller Register 1 924 * --------------------------------------------------------------------------------------------------- 925 * |Bits |Field |Descriptions 926 * | :----: | :----: | :---- | 927 * |[15:0] |POROFF |Power-on Reset Enable Bit (Write Protect) 928 * | | |When powered on, the POR circuit generates a reset signal to reset the whole chip function, but noise on the power may cause the POR active again. 929 * | | |User can disable internal POR circuit to avoid unpredictable noise to cause chip reset by writing 0x5AA5 to this field. 930 * | | |The POR function will be active again when this field is set to another value or chip is reset by other reset source, including: 931 * | | |nRESET, Watchdog, LVR reset, BOD reset, ICE reset command and the software-chip reset function. 932 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 933 * @var SYS_T::PLCTL 934 * Offset: 0x1F8 Power Level Control Register 935 * --------------------------------------------------------------------------------------------------- 936 * |Bits |Field |Descriptions 937 * | :----: | :----: | :---- | 938 * |[1:0] |PLSEL |Power Level Select (Write Protect) 939 * | | |00 = Set to Power level 0 (PL0). 940 * | | |01 = Set to Power level 1 (PL1). 941 * | | |Others = Reserved. 942 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 943 * |[4] |MVRS |Main Voltage Regulator Type Select (Write Protect) 944 * | | |This bit filed sets main voltage regulator type. 945 * | | |After setting main voltage regulator type to DCDC (MVRS (SYS_PLCTL[4]) = 1) system will set main voltage regulator type change busy flag MVRCBUSY(SYS_PLSTS[1]), detect inductor connection and update inductor connection status LCONS (SYS_PLSTS[3]). 946 * | | |If inductor exist LCONS will be cleard and main viltage regulator type can switch to DCDC (CURMVRS (SYS_PLSTS[12])=1). 947 * | | |0 = Set main voltage regulator to LDO. 948 * | | |1 = Set main voltage regulator to DCDC. 949 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 950 * |[21:16] |LVSSTEP |LDO Voltage Scaling Step (Write Protect) 951 * | | |The LVSSTEP value is LDO voltage rising step. 952 * | | |LDO voltage scaling step = (LVSSTEP + 1) * 10mV. 953 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 954 * |[31:24] |LVSPRD |LDO Voltage Scaling Period (Write Protect) 955 * | | |The LVSPRD value is the period of each LDO voltage rising step. 956 * | | |LDO voltage scaling period = (LVSPRD + 1) * 1us. 957 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 958 * @var SYS_T::PLSTS 959 * Offset: 0x1FC Power Level Status Register 960 * --------------------------------------------------------------------------------------------------- 961 * |Bits |Field |Descriptions 962 * | :----: | :----: | :---- | 963 * |[0] |PLCBUSY |Power Level Change Busy Bit (Read Only) 964 * | | |This bit is set by hardware when power level is changing . After power level change is completed, this bit will be cleared automatically by hardware. 965 * | | |0 = Power level change is completed. 966 * | | |1 = Power level change is ongoing. 967 * |[1] |MVRCBUSY |Main Voltage Regulator Type Change Busy Bit (Read Only) 968 * | | |This bit is set by hardware when main voltage regulator type is changing. 969 * | | |After main voltage regulator type change is completed, this bit will be cleared automatically by hardware. 970 * | | |0 = Main voltage regulator type change is completed. 971 * | | |1 = Main voltage regulator type change is ongoing. 972 * |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect) 973 * | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors: 974 * | | |1.System change to DC-DC mode but LDO change voltage process not finish. 975 * | | |2.Detect inductor fail. 976 * | | |Read: 977 * | | |0 = No main voltage regulator type change error. 978 * | | |1 = Main voltage regulator type change to DCDC error occurred. 979 * | | |Write: 980 * | | |0 = No effect. 981 * | | |1 = Clears MVRCERR to 0. 982 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 983 * |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only) 984 * | | |0 = Inductor connect between Vsw and LDO_CAP pin. 985 * | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1. 986 * | | |0 = Inductor connect between Vsw and LDO_CAP pin. 987 * | | |1 = No Inductor connect between Vsw and LDO_CAP pin. 988 * | | |Note: This bit is 1 when main viltage regulator is LDO. 989 * |[4] |PDINVTRF |Power-down Mode Invalid Transition Flag (Write Protect) 990 * | | |This bit is set by hardware if the requested active DCDC mode to Power-down mode transition is invalid. 991 * | | |This transition request will be aborted by hardware. 992 * | | |The bit can be cleared by software. 993 * | | |Read: 994 * | | |0 = No Power-down mode invalid transition. 995 * | | |1 = Power-down mode invalid transition occurred. 996 * | | |Write: 997 * | | |0 = No effect. 998 * | | |1 = Clears this bit to 0. 999 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1000 * |[9:8] |PLSTATUS |Power Level Status (Read Only) 1001 * | | |This bit field reflect the current power level. 1002 * | | |00 = Power level is PL0. 1003 * | | |01 = Power level is PL1. 1004 * | | |Others = Reserved. 1005 * |[12] |CURMVR |Current Main Voltage Regulator Type (Read Only) 1006 * | | |This bit field reflects current main voltage regulator type. 1007 * | | |0 = Current main voltage regulator in active and Idle mode is LDO. 1008 * | | |1 = Current main voltage regulator in active mode and Idle is DCDC. 1009 * @var SYS_T::AHBMCTL 1010 * Offset: 0x400 AHB Bus Matrix Priority Control Register 1011 * --------------------------------------------------------------------------------------------------- 1012 * |Bits |Field |Descriptions 1013 * | :----: | :----: | :---- | 1014 * |[0] |INTACTEN |Highest AHB Bus Priority of Cortex-M23 Core Enable Bit (Write Protect) 1015 * | | |Enable Cortex-M23 core with highest AHB bus priority in AHB bus matrix. 1016 * | | |0 = Run robin mode. 1017 * | | |1 = Cortex-M23 CPU with highest bus priority when interrupt occurs. 1018 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1019 */ 1020 1021 __I uint32_t PDID; /*!< [0x0000] Part Device Identification Number Register */ 1022 __IO uint32_t RSTSTS; /*!< [0x0004] System Reset Status Register */ 1023 __IO uint32_t IPRST0; /*!< [0x0008] Peripheral Reset Control Register 0 */ 1024 __IO uint32_t IPRST1; /*!< [0x000c] Peripheral Reset Control Register 1 */ 1025 __IO uint32_t IPRST2; /*!< [0x0010] Peripheral Reset Control Register 2 */ 1026 __I uint32_t RESERVE0[1]; 1027 __IO uint32_t BODCTL; /*!< [0x0018] Brown-out Detector Control Register */ 1028 __IO uint32_t IVSCTL; /*!< [0x001c] Internal Voltage Source Control Register */ 1029 __I uint32_t RESERVE1[1]; 1030 __IO uint32_t PORCTL0; /*!< [0x0024] Power-on Reset Controller Register 0 */ 1031 __IO uint32_t VREFCTL; /*!< [0x0028] VREF Control Register */ 1032 __IO uint32_t USBPHY; /*!< [0x002C] USB PHY Control Register */ 1033 __IO uint32_t GPA_MFPL; /*!< [0x0030] GPIOA Low Byte Multiple Function Control Register */ 1034 __IO uint32_t GPA_MFPH; /*!< [0x0034] GPIOA High Byte Multiple Function Control Register */ 1035 __IO uint32_t GPB_MFPL; /*!< [0x0038] GPIOB Low Byte Multiple Function Control Register */ 1036 __IO uint32_t GPB_MFPH; /*!< [0x003c] GPIOB High Byte Multiple Function Control Register */ 1037 __IO uint32_t GPC_MFPL; /*!< [0x0040] GPIOC Low Byte Multiple Function Control Register */ 1038 __IO uint32_t GPC_MFPH; /*!< [0x0044] GPIOC High Byte Multiple Function Control Register */ 1039 __IO uint32_t GPD_MFPL; /*!< [0x0048] GPIOD Low Byte Multiple Function Control Register */ 1040 __IO uint32_t GPD_MFPH; /*!< [0x004c] GPIOD High Byte Multiple Function Control Register */ 1041 __IO uint32_t GPE_MFPL; /*!< [0x0050] GPIOE Low Byte Multiple Function Control Register */ 1042 __IO uint32_t GPE_MFPH; /*!< [0x0054] GPIOE High Byte Multiple Function Control Register */ 1043 __IO uint32_t GPF_MFPL; /*!< [0x0058] GPIOF Low Byte Multiple Function Control Register */ 1044 __IO uint32_t GPF_MFPH; /*!< [0x005C] GPIOF High Byte Multiple Function Control Register */ 1045 __IO uint32_t GPG_MFPL; /*!< [0x0060] GPIOG Low Byte Multiple Function Control Register */ 1046 __IO uint32_t GPG_MFPH; /*!< [0x0064] GPIOG High Byte Multiple Function Control Register */ 1047 __IO uint32_t GPH_MFPL; /*!< [0x0068] GPIOH Low Byte Multiple Function Control Register */ 1048 __IO uint32_t GPH_MFPH; /*!< [0x006C] GPIOH High Byte Multiple Function Control Register */ 1049 __I uint32_t RESERVE2[4]; 1050 __IO uint32_t GPA_MFOS; /*!< [0x0080] GPIOA Multiple Function Output Select Register */ 1051 __IO uint32_t GPB_MFOS; /*!< [0x0084] GPIOB Multiple Function Output Select Register */ 1052 __IO uint32_t GPC_MFOS; /*!< [0x0088] GPIOC Multiple Function Output Select Register */ 1053 __IO uint32_t GPD_MFOS; /*!< [0x008c] GPIOD Multiple Function Output Select Register */ 1054 __IO uint32_t GPE_MFOS; /*!< [0x0090] GPIOE Multiple Function Output Select Register */ 1055 __IO uint32_t GPF_MFOS; /*!< [0x0094] GPIOF Multiple Function Output Select Register */ 1056 __IO uint32_t GPG_MFOS; /*!< [0x0098] GPIOG Multiple Function Output Select Register */ 1057 __IO uint32_t GPH_MFOS; /*!< [0x009c] GPIOH Multiple Function Output Select Register */ 1058 __I uint32_t RESERVE3[8]; 1059 __IO uint32_t SRAMICTL; /*!< [0x00C0] System SRAM Interrupt Enable Control Register */ 1060 __IO uint32_t SRAMSTS; /*!< [0x00C4] System SRAM Parity Error Status Register */ 1061 __IO uint32_t SRAMEADR; /*!< [0x00C8] System SRAM Parity Check Error Address Register */ 1062 __IO uint32_t RESERVE4[4]; 1063 __IO uint32_t SRAMPCTL; /*!< [0x00DC] System SRAM Power Mode Control Register */ 1064 __IO uint32_t SRAMPPCT; /*!< [0x00E0] Peripheral SRAM Power Mode Control Register */ 1065 __IO uint32_t TCTL48M; /*!< [0x00E4] HIRC 48M Trim Control Register */ 1066 __IO uint32_t TIEN48M; /*!< [0x00E8] HIRC 48M Trim Interrupt Enable Register */ 1067 __IO uint32_t TISTS48M; /*!< [0x00EC] HIRC 48M Trim Interrupt Status Register */ 1068 __IO uint32_t TCTL12M; /*!< [0x00F0] HIRC 12M Trim Control Register */ 1069 __IO uint32_t TIEN12M; /*!< [0x00F4] HIRC 12M Trim Interrupt Enable Register */ 1070 __IO uint32_t TISTS12M; /*!< [0x00F8] HIRC 12M Trim Interrupt Status Register */ 1071 __I uint32_t RESERVE6[1]; 1072 __IO uint32_t REGLCTL; /*!< [0x0100] Register Lock Control Register */ 1073 __I uint32_t RESERVE7[58]; 1074 __IO uint32_t PORCTL1; /*!< [0x01EC] Power-on Reset Controller Register 1 */ 1075 __I uint32_t RESERVE8[2]; 1076 __IO uint32_t PLCTL; /*!< [0x01F8] Power Level Control Register */ 1077 __IO uint32_t PLSTS; /*!< [0x01FC] Power Level Status Register */ 1078 __I uint32_t RESERVE9[128]; 1079 __IO uint32_t AHBMCTL; /*!< [0x0400] AHB Bus Matrix Priority Control Register */ 1080 1081 1082 } SYS_T; 1083 1084 /** 1085 @addtogroup SYS_CONST SYS Bit Field Definition 1086 Constant Definitions for SYS Controller 1087 @{ */ 1088 1089 #define SYS_PDID_PDID_Pos (0) /*!< SYS_T::PDID: PDID Position */ 1090 #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) /*!< SYS_T::PDID: PDID Mask */ 1091 1092 #define SYS_RSTSTS_PORF_Pos (0) /*!< SYS_T::RSTSTS: PORF Position */ 1093 #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) /*!< SYS_T::RSTSTS: PORF Mask */ 1094 1095 #define SYS_RSTSTS_PINRF_Pos (1) /*!< SYS_T::RSTSTS: PINRF Position */ 1096 #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) /*!< SYS_T::RSTSTS: PINRF Mask */ 1097 1098 #define SYS_RSTSTS_WDTRF_Pos (2) /*!< SYS_T::RSTSTS: WDTRF Position */ 1099 #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) /*!< SYS_T::RSTSTS: WDTRF Mask */ 1100 1101 #define SYS_RSTSTS_LVRF_Pos (3) /*!< SYS_T::RSTSTS: LVRF Position */ 1102 #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) /*!< SYS_T::RSTSTS: LVRF Mask */ 1103 1104 #define SYS_RSTSTS_BODRF_Pos (4) /*!< SYS_T::RSTSTS: BODRF Position */ 1105 #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) /*!< SYS_T::RSTSTS: BODRF Mask */ 1106 1107 #define SYS_RSTSTS_SYSRF_Pos (5) /*!< SYS_T::RSTSTS: SYSRF Position */ 1108 #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) /*!< SYS_T::RSTSTS: SYSRF Mask */ 1109 1110 #define SYS_RSTSTS_CPURF_Pos (7) /*!< SYS_T::RSTSTS: CPURF Position */ 1111 #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) /*!< SYS_T::RSTSTS: CPURF Mask */ 1112 1113 #define SYS_RSTSTS_CPULKRF_Pos (8) /*!< SYS_T::RSTSTS: CPULKRF Position */ 1114 #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) /*!< SYS_T::RSTSTS: CPULKRF Mask */ 1115 1116 #define SYS_IPRST0_CHIPRST_Pos (0) /*!< SYS_T::IPRST0: CHIPRST Position */ 1117 #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) /*!< SYS_T::IPRST0: CHIPRST Mask */ 1118 1119 #define SYS_IPRST0_CPURST_Pos (1) /*!< SYS_T::IPRST0: CPURST Position */ 1120 #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) /*!< SYS_T::IPRST0: CPURST Mask */ 1121 1122 #define SYS_IPRST0_PDMA0RST_Pos (2) /*!< SYS_T::IPRST0: PDMA0RST Position */ 1123 #define SYS_IPRST0_PDMA0RST_Msk (0x1ul << SYS_IPRST0_PDMA0RST_Pos) /*!< SYS_T::IPRST0: PDMA0RST Mask */ 1124 1125 #define SYS_IPRST0_EBIRST_Pos (3) /*!< SYS_T::IPRST0: EBIRST Position */ 1126 #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) /*!< SYS_T::IPRST0: EBIRST Mask */ 1127 1128 #define SYS_IPRST0_USBHRST_Pos (4) /*!< SYS_T::IPRST0: USBHRST Position */ 1129 #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) /*!< SYS_T::IPRST0: USBHRST Mask */ 1130 1131 #define SYS_IPRST0_SDH0RST_Pos (6) /*!< SYS_T::IPRST0: SDH0RST Position */ 1132 #define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) /*!< SYS_T::IPRST0: SDH0RST Mask */ 1133 1134 #define SYS_IPRST0_CRCRST_Pos (7) /*!< SYS_T::IPRST0: CRCRST Position */ 1135 #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) /*!< SYS_T::IPRST0: CRCRST Mask */ 1136 1137 #define SYS_IPRST0_CRPTRST_Pos (12) /*!< SYS_T::IPRST0: CRPTRST Position */ 1138 #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) /*!< SYS_T::IPRST0: CRPTRST Mask */ 1139 1140 #define SYS_IPRST0_PDMA1RST_Pos (29) /*!< SYS_T::IPRST0: PDMA1RST Position */ 1141 #define SYS_IPRST0_PDMA1RST_Msk (0x1ul << SYS_IPRST0_PDMA1RST_Pos) /*!< SYS_T::IPRST0: PDMA1RST Mask */ 1142 1143 #define SYS_IPRST1_GPIORST_Pos (1) /*!< SYS_T::IPRST1: GPIORST Position */ 1144 #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) /*!< SYS_T::IPRST1: GPIORST Mask */ 1145 1146 #define SYS_IPRST1_TMR0RST_Pos (2) /*!< SYS_T::IPRST1: TMR0RST Position */ 1147 #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) /*!< SYS_T::IPRST1: TMR0RST Mask */ 1148 1149 #define SYS_IPRST1_TMR1RST_Pos (3) /*!< SYS_T::IPRST1: TMR1RST Position */ 1150 #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) /*!< SYS_T::IPRST1: TMR1RST Mask */ 1151 1152 #define SYS_IPRST1_TMR2RST_Pos (4) /*!< SYS_T::IPRST1: TMR2RST Position */ 1153 #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) /*!< SYS_T::IPRST1: TMR2RST Mask */ 1154 1155 #define SYS_IPRST1_TMR3RST_Pos (5) /*!< SYS_T::IPRST1: TMR3RST Position */ 1156 #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) /*!< SYS_T::IPRST1: TMR3RST Mask */ 1157 1158 #define SYS_IPRST1_ACMP01RST_Pos (7) /*!< SYS_T::IPRST1: ACMP01RST Position */ 1159 #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) /*!< SYS_T::IPRST1: ACMP01RST Mask */ 1160 1161 #define SYS_IPRST1_I2C0RST_Pos (8) /*!< SYS_T::IPRST1: I2C0RST Position */ 1162 #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) /*!< SYS_T::IPRST1: I2C0RST Mask */ 1163 1164 #define SYS_IPRST1_I2C1RST_Pos (9) /*!< SYS_T::IPRST1: I2C1RST Position */ 1165 #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) /*!< SYS_T::IPRST1: I2C1RST Mask */ 1166 1167 #define SYS_IPRST1_I2C2RST_Pos (10) /*!< SYS_T::IPRST1: I2C2RST Position */ 1168 #define SYS_IPRST1_I2C2RST_Msk (0x1ul << SYS_IPRST1_I2C2RST_Pos) /*!< SYS_T::IPRST1: I2C2RST Mask */ 1169 1170 #define SYS_IPRST1_QSPI0RST_Pos (12) /*!< SYS_T::IPRST1: QSPI0RST Position */ 1171 #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) /*!< SYS_T::IPRST1: QSPI0RST Mask */ 1172 1173 #define SYS_IPRST1_SPI0RST_Pos (13) /*!< SYS_T::IPRST1: SPI0RST Position */ 1174 #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) /*!< SYS_T::IPRST1: SPI0RST Mask */ 1175 1176 #define SYS_IPRST1_SPI1RST_Pos (14) /*!< SYS_T::IPRST1: SPI1RST Position */ 1177 #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) /*!< SYS_T::IPRST1: SPI1RST Mask */ 1178 1179 #define SYS_IPRST1_SPI2RST_Pos (15) /*!< SYS_T::IPRST1: SPI2RST Position */ 1180 #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) /*!< SYS_T::IPRST1: SPI2RST Mask */ 1181 1182 #define SYS_IPRST1_UART0RST_Pos (16) /*!< SYS_T::IPRST1: UART0RST Position */ 1183 #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) /*!< SYS_T::IPRST1: UART0RST Mask */ 1184 1185 #define SYS_IPRST1_UART1RST_Pos (17) /*!< SYS_T::IPRST1: UART1RST Position */ 1186 #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) /*!< SYS_T::IPRST1: UART1RST Mask */ 1187 1188 #define SYS_IPRST1_UART2RST_Pos (18) /*!< SYS_T::IPRST1: UART2RST Position */ 1189 #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) /*!< SYS_T::IPRST1: UART2RST Mask */ 1190 1191 #define SYS_IPRST1_UART3RST_Pos (19) /*!< SYS_T::IPRST1: UART3RST Position */ 1192 #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) /*!< SYS_T::IPRST1: UART3RST Mask */ 1193 1194 #define SYS_IPRST1_UART4RST_Pos (20) /*!< SYS_T::IPRST1: UART4RST Position */ 1195 #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) /*!< SYS_T::IPRST1: UART4RST Mask */ 1196 1197 #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ 1198 #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ 1199 1200 #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ 1201 #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ 1202 1203 #define SYS_IPRST1_OTGRST_Pos (26) /*!< SYS_T::IPRST1: OTGRST Position */ 1204 #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) /*!< SYS_T::IPRST1: OTGRST Mask */ 1205 1206 #define SYS_IPRST1_USBDRST_Pos (27) /*!< SYS_T::IPRST1: USBDRST Position */ 1207 #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) /*!< SYS_T::IPRST1: USBDRST Mask */ 1208 1209 #define SYS_IPRST1_EADCRST_Pos (28) /*!< SYS_T::IPRST1: EADCRST Position */ 1210 #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) /*!< SYS_T::IPRST1: EADCRST Mask */ 1211 1212 #define SYS_IPRST1_I2S0RST_Pos (29) /*!< SYS_T::IPRST1: I2S0RST Position */ 1213 #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) /*!< SYS_T::IPRST1: I2S0RST Mask */ 1214 1215 #define SYS_IPRST1_TRNGRST_Pos (31) /*!< SYS_T::IPRST1: TRNGRST Position */ 1216 #define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) /*!< SYS_T::IPRST1: TRNGRST Mask */ 1217 1218 #define SYS_IPRST2_SC0RST_Pos (0) /*!< SYS_T::IPRST2: SC0RST Position */ 1219 #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) /*!< SYS_T::IPRST2: SC0RST Mask */ 1220 1221 #define SYS_IPRST2_SC1RST_Pos (1) /*!< SYS_T::IPRST2: SC1RST Position */ 1222 #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) /*!< SYS_T::IPRST2: SC1RST Mask */ 1223 1224 #define SYS_IPRST2_SC2RST_Pos (2) /*!< SYS_T::IPRST2: SC2RST Position */ 1225 #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) /*!< SYS_T::IPRST2: SC2RST Mask */ 1226 1227 #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ 1228 #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ 1229 1230 #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ 1231 #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ 1232 1233 #define SYS_IPRST2_USCI1RST_Pos (9) /*!< SYS_T::IPRST2: USCI1RST Position */ 1234 #define SYS_IPRST2_USCI1RST_Msk (0x1ul << SYS_IPRST2_USCI1RST_Pos) /*!< SYS_T::IPRST2: USCI1RST Mask */ 1235 1236 #define SYS_IPRST2_DACRST_Pos (12) /*!< SYS_T::IPRST2: DACRST Position */ 1237 #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) /*!< SYS_T::IPRST2: DACRST Mask */ 1238 1239 #define SYS_IPRST2_EPWM0RST_Pos (16) /*!< SYS_T::IPRST2: EPWM0RST Position */ 1240 #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) /*!< SYS_T::IPRST2: EPWM0RST Mask */ 1241 1242 #define SYS_IPRST2_EPWM1RST_Pos (17) /*!< SYS_T::IPRST2: EPWM1RST Position */ 1243 #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) /*!< SYS_T::IPRST2: EPWM1RST Mask */ 1244 1245 #define SYS_IPRST2_BPWM0RST_Pos (18) /*!< SYS_T::IPRST2: BPWM0RST Position */ 1246 #define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) /*!< SYS_T::IPRST2: BPWM0RST Mask */ 1247 1248 #define SYS_IPRST2_BPWM1RST_Pos (19) /*!< SYS_T::IPRST2: BPWM1RST Position */ 1249 #define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) /*!< SYS_T::IPRST2: BPWM1RST Mask */ 1250 1251 #define SYS_IPRST2_QEI0RST_Pos (22) /*!< SYS_T::IPRST2: QEI0RST Position */ 1252 #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) /*!< SYS_T::IPRST2: QEI0RST Mask */ 1253 1254 #define SYS_IPRST2_QEI1RST_Pos (23) /*!< SYS_T::IPRST2: QEI1RST Position */ 1255 #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) /*!< SYS_T::IPRST2: QEI1RST Mask */ 1256 1257 #define SYS_IPRST2_ECAP0RST_Pos (26) /*!< SYS_T::IPRST2: ECAP0RST Position */ 1258 #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) /*!< SYS_T::IPRST2: ECAP0RST Mask */ 1259 1260 #define SYS_IPRST2_ECAP1RST_Pos (27) /*!< SYS_T::IPRST2: ECAP1RST Position */ 1261 #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) /*!< SYS_T::IPRST2: ECAP1RST Mask */ 1262 1263 #define SYS_BODCTL_BODEN_Pos (0) /*!< SYS_T::BODCTL: BODEN Position */ 1264 #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) /*!< SYS_T::BODCTL: BODEN Mask */ 1265 1266 #define SYS_BODCTL_BODRSTEN_Pos (3) /*!< SYS_T::BODCTL: BODRSTEN Position */ 1267 #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) /*!< SYS_T::BODCTL: BODRSTEN Mask */ 1268 1269 #define SYS_BODCTL_BODIF_Pos (4) /*!< SYS_T::BODCTL: BODIF Position */ 1270 #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) /*!< SYS_T::BODCTL: BODIF Mask */ 1271 1272 #define SYS_BODCTL_BODLPM_Pos (5) /*!< SYS_T::BODCTL: BODLPM Position */ 1273 #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) /*!< SYS_T::BODCTL: BODLPM Mask */ 1274 1275 #define SYS_BODCTL_BODOUT_Pos (6) /*!< SYS_T::BODCTL: BODOUT Position */ 1276 #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) /*!< SYS_T::BODCTL: BODOUT Mask */ 1277 1278 #define SYS_BODCTL_LVREN_Pos (7) /*!< SYS_T::BODCTL: LVREN Position */ 1279 #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) /*!< SYS_T::BODCTL: LVREN Mask */ 1280 1281 #define SYS_BODCTL_BODDGSEL_Pos (8) /*!< SYS_T::BODCTL: BODDGSEL Position */ 1282 #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) /*!< SYS_T::BODCTL: BODDGSEL Mask */ 1283 1284 #define SYS_BODCTL_LVRDGSEL_Pos (12) /*!< SYS_T::BODCTL: LVRDGSEL Position */ 1285 #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) /*!< SYS_T::BODCTL: LVRDGSEL Mask */ 1286 1287 #define SYS_BODCTL_BODVL_Pos (16) /*!< SYS_T::BODCTL: BODVL Position */ 1288 #define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) /*!< SYS_T::BODCTL: BODVL Mask */ 1289 1290 #define SYS_IVSCTL_VTEMPEN_Pos (0) /*!< SYS_T::IVSCTL: VTEMPEN Position */ 1291 #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) /*!< SYS_T::IVSCTL: VTEMPEN Mask */ 1292 1293 #define SYS_IVSCTL_VBATUGEN_Pos (1) /*!< SYS_T::IVSCTL: VBATUGEN Position */ 1294 #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) /*!< SYS_T::IVSCTL: VBATUGEN Mask */ 1295 1296 #define SYS_PORCTL0_PORMASK_Pos (0) /*!< SYS_T::PORCTL0: PORMASK Position */ 1297 #define SYS_PORCTL0_PORMASK_Msk (0xfffful << SYS_PORCTL0_PORMASK_Pos) /*!< SYS_T::PORCTL0: PORMASK Mask */ 1298 1299 #define SYS_VREFCTL_VREFCTL_Pos (0) /*!< SYS_T::VREFCTL: VREFCTL Position */ 1300 #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) /*!< SYS_T::VREFCTL: VREFCTL Mask */ 1301 1302 #define SYS_VREFCTL_IBIASSEL_Pos (5) /*!< SYS_T::VREFCTL: IBIASSEL Position */ 1303 #define SYS_VREFCTL_IBIASSEL_Msk (0x1ul << SYS_VREFCTL_IBIASSEL_Pos) /*!< SYS_T::VREFCTL: IBIASSEL Mask */ 1304 1305 #define SYS_VREFCTL_PRELOADSEL_Pos (6) /*!< SYS_T::VREFCTL: PRELOADSEL Position */ 1306 #define SYS_VREFCTL_PRELOADSEL_Msk (0x3ul << SYS_VREFCTL_PRELOADSEL_Pos) /*!< SYS_T::VREFCTL: PRELOADSEL Mask */ 1307 1308 #define SYS_USBPHY_USBROLE_Pos (0) /*!< SYS_T::USBPHY: USBROLE Position */ 1309 #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) /*!< SYS_T::USBPHY: USBROLE Mask */ 1310 1311 #define SYS_USBPHY_SBO_Pos (2) /*!< SYS_T::USBPHY: SBO Position */ 1312 #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) /*!< SYS_T::USBPHY: SBO Mask */ 1313 1314 #define SYS_USBPHY_OTGPHYEN_Pos (8) /*!< SYS_T::USBPHY: OTGPHYEN Position */ 1315 #define SYS_USBPHY_OTGPHYEN_Msk (0x1ul << SYS_USBPHY_OTGPHYEN_Pos) /*!< SYS_T::USBPHY: OTGPHYEN Mask */ 1316 1317 #define SYS_GPA_MFPL_PA0MFP_Pos (0) /*!< SYS_T::GPA_MFPL: PA0MFP Position */ 1318 #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) /*!< SYS_T::GPA_MFPL: PA0MFP Mask */ 1319 1320 #define SYS_GPA_MFPL_PA1MFP_Pos (4) /*!< SYS_T::GPA_MFPL: PA1MFP Position */ 1321 #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) /*!< SYS_T::GPA_MFPL: PA1MFP Mask */ 1322 1323 #define SYS_GPA_MFPL_PA2MFP_Pos (8) /*!< SYS_T::GPA_MFPL: PA2MFP Position */ 1324 #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) /*!< SYS_T::GPA_MFPL: PA2MFP Mask */ 1325 1326 #define SYS_GPA_MFPL_PA3MFP_Pos (12) /*!< SYS_T::GPA_MFPL: PA3MFP Position */ 1327 #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) /*!< SYS_T::GPA_MFPL: PA3MFP Mask */ 1328 1329 #define SYS_GPA_MFPL_PA4MFP_Pos (16) /*!< SYS_T::GPA_MFPL: PA4MFP Position */ 1330 #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) /*!< SYS_T::GPA_MFPL: PA4MFP Mask */ 1331 1332 #define SYS_GPA_MFPL_PA5MFP_Pos (20) /*!< SYS_T::GPA_MFPL: PA5MFP Position */ 1333 #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) /*!< SYS_T::GPA_MFPL: PA5MFP Mask */ 1334 1335 #define SYS_GPA_MFPL_PA6MFP_Pos (24) /*!< SYS_T::GPA_MFPL: PA6MFP Position */ 1336 #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) /*!< SYS_T::GPA_MFPL: PA6MFP Mask */ 1337 1338 #define SYS_GPA_MFPL_PA7MFP_Pos (28) /*!< SYS_T::GPA_MFPL: PA7MFP Position */ 1339 #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) /*!< SYS_T::GPA_MFPL: PA7MFP Mask */ 1340 1341 #define SYS_GPA_MFPH_PA8MFP_Pos (0) /*!< SYS_T::GPA_MFPH: PA8MFP Position */ 1342 #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) /*!< SYS_T::GPA_MFPH: PA8MFP Mask */ 1343 1344 #define SYS_GPA_MFPH_PA9MFP_Pos (4) /*!< SYS_T::GPA_MFPH: PA9MFP Position */ 1345 #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) /*!< SYS_T::GPA_MFPH: PA9MFP Mask */ 1346 1347 #define SYS_GPA_MFPH_PA10MFP_Pos (8) /*!< SYS_T::GPA_MFPH: PA10MFP Position */ 1348 #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) /*!< SYS_T::GPA_MFPH: PA10MFP Mask */ 1349 1350 #define SYS_GPA_MFPH_PA11MFP_Pos (12) /*!< SYS_T::GPA_MFPH: PA11MFP Position */ 1351 #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) /*!< SYS_T::GPA_MFPH: PA11MFP Mask */ 1352 1353 #define SYS_GPA_MFPH_PA12MFP_Pos (16) /*!< SYS_T::GPA_MFPH: PA12MFP Position */ 1354 #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) /*!< SYS_T::GPA_MFPH: PA12MFP Mask */ 1355 1356 #define SYS_GPA_MFPH_PA13MFP_Pos (20) /*!< SYS_T::GPA_MFPH: PA13MFP Position */ 1357 #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) /*!< SYS_T::GPA_MFPH: PA13MFP Mask */ 1358 1359 #define SYS_GPA_MFPH_PA14MFP_Pos (24) /*!< SYS_T::GPA_MFPH: PA14MFP Position */ 1360 #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) /*!< SYS_T::GPA_MFPH: PA14MFP Mask */ 1361 1362 #define SYS_GPA_MFPH_PA15MFP_Pos (28) /*!< SYS_T::GPA_MFPH: PA15MFP Position */ 1363 #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) /*!< SYS_T::GPA_MFPH: PA15MFP Mask */ 1364 1365 #define SYS_GPB_MFPL_PB0MFP_Pos (0) /*!< SYS_T::GPB_MFPL: PB0MFP Position */ 1366 #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) /*!< SYS_T::GPB_MFPL: PB0MFP Mask */ 1367 1368 #define SYS_GPB_MFPL_PB1MFP_Pos (4) /*!< SYS_T::GPB_MFPL: PB1MFP Position */ 1369 #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) /*!< SYS_T::GPB_MFPL: PB1MFP Mask */ 1370 1371 #define SYS_GPB_MFPL_PB2MFP_Pos (8) /*!< SYS_T::GPB_MFPL: PB2MFP Position */ 1372 #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) /*!< SYS_T::GPB_MFPL: PB2MFP Mask */ 1373 1374 #define SYS_GPB_MFPL_PB3MFP_Pos (12) /*!< SYS_T::GPB_MFPL: PB3MFP Position */ 1375 #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) /*!< SYS_T::GPB_MFPL: PB3MFP Mask */ 1376 1377 #define SYS_GPB_MFPL_PB4MFP_Pos (16) /*!< SYS_T::GPB_MFPL: PB4MFP Position */ 1378 #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) /*!< SYS_T::GPB_MFPL: PB4MFP Mask */ 1379 1380 #define SYS_GPB_MFPL_PB5MFP_Pos (20) /*!< SYS_T::GPB_MFPL: PB5MFP Position */ 1381 #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) /*!< SYS_T::GPB_MFPL: PB5MFP Mask */ 1382 1383 #define SYS_GPB_MFPL_PB6MFP_Pos (24) /*!< SYS_T::GPB_MFPL: PB6MFP Position */ 1384 #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) /*!< SYS_T::GPB_MFPL: PB6MFP Mask */ 1385 1386 #define SYS_GPB_MFPL_PB7MFP_Pos (28) /*!< SYS_T::GPB_MFPL: PB7MFP Position */ 1387 #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) /*!< SYS_T::GPB_MFPL: PB7MFP Mask */ 1388 1389 #define SYS_GPB_MFPH_PB8MFP_Pos (0) /*!< SYS_T::GPB_MFPH: PB8MFP Position */ 1390 #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) /*!< SYS_T::GPB_MFPH: PB8MFP Mask */ 1391 1392 #define SYS_GPB_MFPH_PB9MFP_Pos (4) /*!< SYS_T::GPB_MFPH: PB9MFP Position */ 1393 #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) /*!< SYS_T::GPB_MFPH: PB9MFP Mask */ 1394 1395 #define SYS_GPB_MFPH_PB10MFP_Pos (8) /*!< SYS_T::GPB_MFPH: PB10MFP Position */ 1396 #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) /*!< SYS_T::GPB_MFPH: PB10MFP Mask */ 1397 1398 #define SYS_GPB_MFPH_PB11MFP_Pos (12) /*!< SYS_T::GPB_MFPH: PB11MFP Position */ 1399 #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) /*!< SYS_T::GPB_MFPH: PB11MFP Mask */ 1400 1401 #define SYS_GPB_MFPH_PB12MFP_Pos (16) /*!< SYS_T::GPB_MFPH: PB12MFP Position */ 1402 #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) /*!< SYS_T::GPB_MFPH: PB12MFP Mask */ 1403 1404 #define SYS_GPB_MFPH_PB13MFP_Pos (20) /*!< SYS_T::GPB_MFPH: PB13MFP Position */ 1405 #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) /*!< SYS_T::GPB_MFPH: PB13MFP Mask */ 1406 1407 #define SYS_GPB_MFPH_PB14MFP_Pos (24) /*!< SYS_T::GPB_MFPH: PB14MFP Position */ 1408 #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) /*!< SYS_T::GPB_MFPH: PB14MFP Mask */ 1409 1410 #define SYS_GPB_MFPH_PB15MFP_Pos (28) /*!< SYS_T::GPB_MFPH: PB15MFP Position */ 1411 #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) /*!< SYS_T::GPB_MFPH: PB15MFP Mask */ 1412 1413 #define SYS_GPC_MFPL_PC0MFP_Pos (0) /*!< SYS_T::GPC_MFPL: PC0MFP Position */ 1414 #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) /*!< SYS_T::GPC_MFPL: PC0MFP Mask */ 1415 1416 #define SYS_GPC_MFPL_PC1MFP_Pos (4) /*!< SYS_T::GPC_MFPL: PC1MFP Position */ 1417 #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) /*!< SYS_T::GPC_MFPL: PC1MFP Mask */ 1418 1419 #define SYS_GPC_MFPL_PC2MFP_Pos (8) /*!< SYS_T::GPC_MFPL: PC2MFP Position */ 1420 #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) /*!< SYS_T::GPC_MFPL: PC2MFP Mask */ 1421 1422 #define SYS_GPC_MFPL_PC3MFP_Pos (12) /*!< SYS_T::GPC_MFPL: PC3MFP Position */ 1423 #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) /*!< SYS_T::GPC_MFPL: PC3MFP Mask */ 1424 1425 #define SYS_GPC_MFPL_PC4MFP_Pos (16) /*!< SYS_T::GPC_MFPL: PC4MFP Position */ 1426 #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) /*!< SYS_T::GPC_MFPL: PC4MFP Mask */ 1427 1428 #define SYS_GPC_MFPL_PC5MFP_Pos (20) /*!< SYS_T::GPC_MFPL: PC5MFP Position */ 1429 #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) /*!< SYS_T::GPC_MFPL: PC5MFP Mask */ 1430 1431 #define SYS_GPC_MFPL_PC6MFP_Pos (24) /*!< SYS_T::GPC_MFPL: PC6MFP Position */ 1432 #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) /*!< SYS_T::GPC_MFPL: PC6MFP Mask */ 1433 1434 #define SYS_GPC_MFPL_PC7MFP_Pos (28) /*!< SYS_T::GPC_MFPL: PC7MFP Position */ 1435 #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) /*!< SYS_T::GPC_MFPL: PC7MFP Mask */ 1436 1437 #define SYS_GPC_MFPH_PC8MFP_Pos (0) /*!< SYS_T::GPC_MFPH: PC8MFP Position */ 1438 #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) /*!< SYS_T::GPC_MFPH: PC8MFP Mask */ 1439 1440 #define SYS_GPC_MFPH_PC9MFP_Pos (4) /*!< SYS_T::GPC_MFPH: PC9MFP Position */ 1441 #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) /*!< SYS_T::GPC_MFPH: PC9MFP Mask */ 1442 1443 #define SYS_GPC_MFPH_PC10MFP_Pos (8) /*!< SYS_T::GPC_MFPH: PC10MFP Position */ 1444 #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) /*!< SYS_T::GPC_MFPH: PC10MFP Mask */ 1445 1446 #define SYS_GPC_MFPH_PC11MFP_Pos (12) /*!< SYS_T::GPC_MFPH: PC11MFP Position */ 1447 #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) /*!< SYS_T::GPC_MFPH: PC11MFP Mask */ 1448 1449 #define SYS_GPC_MFPH_PC12MFP_Pos (16) /*!< SYS_T::GPC_MFPH: PC12MFP Position */ 1450 #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) /*!< SYS_T::GPC_MFPH: PC12MFP Mask */ 1451 1452 #define SYS_GPC_MFPH_PC13MFP_Pos (20) /*!< SYS_T::GPC_MFPH: PC13MFP Position */ 1453 #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) /*!< SYS_T::GPC_MFPH: PC13MFP Mask */ 1454 1455 #define SYS_GPD_MFPL_PD0MFP_Pos (0) /*!< SYS_T::GPD_MFPL: PD0MFP Position */ 1456 #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) /*!< SYS_T::GPD_MFPL: PD0MFP Mask */ 1457 1458 #define SYS_GPD_MFPL_PD1MFP_Pos (4) /*!< SYS_T::GPD_MFPL: PD1MFP Position */ 1459 #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) /*!< SYS_T::GPD_MFPL: PD1MFP Mask */ 1460 1461 #define SYS_GPD_MFPL_PD2MFP_Pos (8) /*!< SYS_T::GPD_MFPL: PD2MFP Position */ 1462 #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) /*!< SYS_T::GPD_MFPL: PD2MFP Mask */ 1463 1464 #define SYS_GPD_MFPL_PD3MFP_Pos (12) /*!< SYS_T::GPD_MFPL: PD3MFP Position */ 1465 #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) /*!< SYS_T::GPD_MFPL: PD3MFP Mask */ 1466 1467 #define SYS_GPD_MFPL_PD4MFP_Pos (16) /*!< SYS_T::GPD_MFPL: PD4MFP Position */ 1468 #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) /*!< SYS_T::GPD_MFPL: PD4MFP Mask */ 1469 1470 #define SYS_GPD_MFPL_PD5MFP_Pos (20) /*!< SYS_T::GPD_MFPL: PD5MFP Position */ 1471 #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) /*!< SYS_T::GPD_MFPL: PD5MFP Mask */ 1472 1473 #define SYS_GPD_MFPL_PD6MFP_Pos (24) /*!< SYS_T::GPD_MFPL: PD6MFP Position */ 1474 #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) /*!< SYS_T::GPD_MFPL: PD6MFP Mask */ 1475 1476 #define SYS_GPD_MFPL_PD7MFP_Pos (28) /*!< SYS_T::GPD_MFPL: PD7MFP Position */ 1477 #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) /*!< SYS_T::GPD_MFPL: PD7MFP Mask */ 1478 1479 #define SYS_GPD_MFPH_PD8MFP_Pos (0) /*!< SYS_T::GPD_MFPH: PD8MFP Position */ 1480 #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) /*!< SYS_T::GPD_MFPH: PD8MFP Mask */ 1481 1482 #define SYS_GPD_MFPH_PD9MFP_Pos (4) /*!< SYS_T::GPD_MFPH: PD9MFP Position */ 1483 #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) /*!< SYS_T::GPD_MFPH: PD9MFP Mask */ 1484 1485 #define SYS_GPD_MFPH_PD10MFP_Pos (8) /*!< SYS_T::GPD_MFPH: PD10MFP Position */ 1486 #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) /*!< SYS_T::GPD_MFPH: PD10MFP Mask */ 1487 1488 #define SYS_GPD_MFPH_PD11MFP_Pos (12) /*!< SYS_T::GPD_MFPH: PD11MFP Position */ 1489 #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) /*!< SYS_T::GPD_MFPH: PD11MFP Mask */ 1490 1491 #define SYS_GPD_MFPH_PD12MFP_Pos (16) /*!< SYS_T::GPD_MFPH: PD12MFP Position */ 1492 #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) /*!< SYS_T::GPD_MFPH: PD12MFP Mask */ 1493 1494 #define SYS_GPD_MFPH_PD13MFP_Pos (20) /*!< SYS_T::GPD_MFPH: PD13MFP Position */ 1495 #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) /*!< SYS_T::GPD_MFPH: PD13MFP Mask */ 1496 1497 #define SYS_GPD_MFPH_PD14MFP_Pos (24) /*!< SYS_T::GPD_MFPH: PD14MFP Position */ 1498 #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) /*!< SYS_T::GPD_MFPH: PD14MFP Mask */ 1499 1500 #define SYS_GPE_MFPL_PE0MFP_Pos (0) /*!< SYS_T::GPE_MFPL: PE0MFP Position */ 1501 #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) /*!< SYS_T::GPE_MFPL: PE0MFP Mask */ 1502 1503 #define SYS_GPE_MFPL_PE1MFP_Pos (4) /*!< SYS_T::GPE_MFPL: PE1MFP Position */ 1504 #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) /*!< SYS_T::GPE_MFPL: PE1MFP Mask */ 1505 1506 #define SYS_GPE_MFPL_PE2MFP_Pos (8) /*!< SYS_T::GPE_MFPL: PE2MFP Position */ 1507 #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) /*!< SYS_T::GPE_MFPL: PE2MFP Mask */ 1508 1509 #define SYS_GPE_MFPL_PE3MFP_Pos (12) /*!< SYS_T::GPE_MFPL: PE3MFP Position */ 1510 #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) /*!< SYS_T::GPE_MFPL: PE3MFP Mask */ 1511 1512 #define SYS_GPE_MFPL_PE4MFP_Pos (16) /*!< SYS_T::GPE_MFPL: PE4MFP Position */ 1513 #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) /*!< SYS_T::GPE_MFPL: PE4MFP Mask */ 1514 1515 #define SYS_GPE_MFPL_PE5MFP_Pos (20) /*!< SYS_T::GPE_MFPL: PE5MFP Position */ 1516 #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) /*!< SYS_T::GPE_MFPL: PE5MFP Mask */ 1517 1518 #define SYS_GPE_MFPL_PE6MFP_Pos (24) /*!< SYS_T::GPE_MFPL: PE6MFP Position */ 1519 #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) /*!< SYS_T::GPE_MFPL: PE6MFP Mask */ 1520 1521 #define SYS_GPE_MFPL_PE7MFP_Pos (28) /*!< SYS_T::GPE_MFPL: PE7MFP Position */ 1522 #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) /*!< SYS_T::GPE_MFPL: PE7MFP Mask */ 1523 1524 #define SYS_GPE_MFPH_PE8MFP_Pos (0) /*!< SYS_T::GPE_MFPH: PE8MFP Position */ 1525 #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) /*!< SYS_T::GPE_MFPH: PE8MFP Mask */ 1526 1527 #define SYS_GPE_MFPH_PE9MFP_Pos (4) /*!< SYS_T::GPE_MFPH: PE9MFP Position */ 1528 #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) /*!< SYS_T::GPE_MFPH: PE9MFP Mask */ 1529 1530 #define SYS_GPE_MFPH_PE10MFP_Pos (8) /*!< SYS_T::GPE_MFPH: PE10MFP Position */ 1531 #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) /*!< SYS_T::GPE_MFPH: PE10MFP Mask */ 1532 1533 #define SYS_GPE_MFPH_PE11MFP_Pos (12) /*!< SYS_T::GPE_MFPH: PE11MFP Position */ 1534 #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) /*!< SYS_T::GPE_MFPH: PE11MFP Mask */ 1535 1536 #define SYS_GPE_MFPH_PE12MFP_Pos (16) /*!< SYS_T::GPE_MFPH: PE12MFP Position */ 1537 #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) /*!< SYS_T::GPE_MFPH: PE12MFP Mask */ 1538 1539 #define SYS_GPE_MFPH_PE13MFP_Pos (20) /*!< SYS_T::GPE_MFPH: PE13MFP Position */ 1540 #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) /*!< SYS_T::GPE_MFPH: PE13MFP Mask */ 1541 1542 #define SYS_GPE_MFPH_PE14MFP_Pos (24) /*!< SYS_T::GPE_MFPH: PE14MFP Position */ 1543 #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) /*!< SYS_T::GPE_MFPH: PE14MFP Mask */ 1544 1545 #define SYS_GPE_MFPH_PE15MFP_Pos (28) /*!< SYS_T::GPE_MFPH: PE15MFP Position */ 1546 #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) /*!< SYS_T::GPE_MFPH: PE15MFP Mask */ 1547 1548 #define SYS_GPF_MFPL_PF0MFP_Pos (0) /*!< SYS_T::GPF_MFPL: PF0MFP Position */ 1549 #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) /*!< SYS_T::GPF_MFPL: PF0MFP Mask */ 1550 1551 #define SYS_GPF_MFPL_PF1MFP_Pos (4) /*!< SYS_T::GPF_MFPL: PF1MFP Position */ 1552 #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) /*!< SYS_T::GPF_MFPL: PF1MFP Mask */ 1553 1554 #define SYS_GPF_MFPL_PF2MFP_Pos (8) /*!< SYS_T::GPF_MFPL: PF2MFP Position */ 1555 #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) /*!< SYS_T::GPF_MFPL: PF2MFP Mask */ 1556 1557 #define SYS_GPF_MFPL_PF3MFP_Pos (12) /*!< SYS_T::GPF_MFPL: PF3MFP Position */ 1558 #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) /*!< SYS_T::GPF_MFPL: PF3MFP Mask */ 1559 1560 #define SYS_GPF_MFPL_PF4MFP_Pos (16) /*!< SYS_T::GPF_MFPL: PF4MFP Position */ 1561 #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) /*!< SYS_T::GPF_MFPL: PF4MFP Mask */ 1562 1563 #define SYS_GPF_MFPL_PF5MFP_Pos (20) /*!< SYS_T::GPF_MFPL: PF5MFP Position */ 1564 #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) /*!< SYS_T::GPF_MFPL: PF5MFP Mask */ 1565 1566 #define SYS_GPF_MFPL_PF6MFP_Pos (24) /*!< SYS_T::GPF_MFPL: PF6MFP Position */ 1567 #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) /*!< SYS_T::GPF_MFPL: PF6MFP Mask */ 1568 1569 #define SYS_GPF_MFPL_PF7MFP_Pos (28) /*!< SYS_T::GPF_MFPL: PF7MFP Position */ 1570 #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) /*!< SYS_T::GPF_MFPL: PF7MFP Mask */ 1571 1572 #define SYS_GPF_MFPH_PF8MFP_Pos (0) /*!< SYS_T::GPF_MFPH: PF8MFP Position */ 1573 #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) /*!< SYS_T::GPF_MFPH: PF8MFP Mask */ 1574 1575 #define SYS_GPF_MFPH_PF9MFP_Pos (4) /*!< SYS_T::GPF_MFPH: PF9MFP Position */ 1576 #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) /*!< SYS_T::GPF_MFPH: PF9MFP Mask */ 1577 1578 #define SYS_GPF_MFPH_PF10MFP_Pos (8) /*!< SYS_T::GPF_MFPH: PF10MFP Position */ 1579 #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) /*!< SYS_T::GPF_MFPH: PF10MFP Mask */ 1580 1581 #define SYS_GPF_MFPH_PF11MFP_Pos (12) /*!< SYS_T::GPF_MFPH: PF11MFP Position */ 1582 #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) /*!< SYS_T::GPF_MFPH: PF11MFP Mask */ 1583 1584 #define SYS_GPG_MFPL_PG2MFP_Pos (8) /*!< SYS_T::GPG_MFPL: PG2MFP Position */ 1585 #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) /*!< SYS_T::GPG_MFPL: PG2MFP Mask */ 1586 1587 #define SYS_GPG_MFPL_PG3MFP_Pos (12) /*!< SYS_T::GPG_MFPL: PG3MFP Position */ 1588 #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) /*!< SYS_T::GPG_MFPL: PG3MFP Mask */ 1589 1590 #define SYS_GPG_MFPL_PG4MFP_Pos (16) /*!< SYS_T::GPG_MFPL: PG4MFP Position */ 1591 #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) /*!< SYS_T::GPG_MFPL: PG4MFP Mask */ 1592 1593 #define SYS_GPG_MFPH_PG9MFP_Pos (4) /*!< SYS_T::GPG_MFPH: PG9MFP Position */ 1594 #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) /*!< SYS_T::GPG_MFPH: PG9MFP Mask */ 1595 1596 #define SYS_GPG_MFPH_PG10MFP_Pos (8) /*!< SYS_T::GPG_MFPH: PG10MFP Position */ 1597 #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) /*!< SYS_T::GPG_MFPH: PG10MFP Mask */ 1598 1599 #define SYS_GPG_MFPH_PG11MFP_Pos (12) /*!< SYS_T::GPG_MFPH: PG11MFP Position */ 1600 #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) /*!< SYS_T::GPG_MFPH: PG11MFP Mask */ 1601 1602 #define SYS_GPG_MFPH_PG12MFP_Pos (16) /*!< SYS_T::GPG_MFPH: PG12MFP Position */ 1603 #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) /*!< SYS_T::GPG_MFPH: PG12MFP Mask */ 1604 1605 #define SYS_GPG_MFPH_PG13MFP_Pos (20) /*!< SYS_T::GPG_MFPH: PG13MFP Position */ 1606 #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) /*!< SYS_T::GPG_MFPH: PG13MFP Mask */ 1607 1608 #define SYS_GPG_MFPH_PG14MFP_Pos (24) /*!< SYS_T::GPG_MFPH: PG14MFP Position */ 1609 #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) /*!< SYS_T::GPG_MFPH: PG14MFP Mask */ 1610 1611 #define SYS_GPG_MFPH_PG15MFP_Pos (28) /*!< SYS_T::GPG_MFPH: PG15MFP Position */ 1612 #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) /*!< SYS_T::GPG_MFPH: PG15MFP Mask */ 1613 1614 #define SYS_GPH_MFPL_PH4MFP_Pos (16) /*!< SYS_T::GPH_MFPL: PH4MFP Position */ 1615 #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) /*!< SYS_T::GPH_MFPL: PH4MFP Mask */ 1616 1617 #define SYS_GPH_MFPL_PH5MFP_Pos (20) /*!< SYS_T::GPH_MFPL: PH5MFP Position */ 1618 #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) /*!< SYS_T::GPH_MFPL: PH5MFP Mask */ 1619 1620 #define SYS_GPH_MFPL_PH6MFP_Pos (24) /*!< SYS_T::GPH_MFPL: PH6MFP Position */ 1621 #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) /*!< SYS_T::GPH_MFPL: PH6MFP Mask */ 1622 1623 #define SYS_GPH_MFPL_PH7MFP_Pos (28) /*!< SYS_T::GPH_MFPL: PH7MFP Position */ 1624 #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) /*!< SYS_T::GPH_MFPL: PH7MFP Mask */ 1625 1626 #define SYS_GPH_MFPH_PH8MFP_Pos (0) /*!< SYS_T::GPH_MFPH: PH8MFP Position */ 1627 #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) /*!< SYS_T::GPH_MFPH: PH8MFP Mask */ 1628 1629 #define SYS_GPH_MFPH_PH9MFP_Pos (4) /*!< SYS_T::GPH_MFPH: PH9MFP Position */ 1630 #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) /*!< SYS_T::GPH_MFPH: PH9MFP Mask */ 1631 1632 #define SYS_GPH_MFPH_PH10MFP_Pos (8) /*!< SYS_T::GPH_MFPH: PH10MFP Position */ 1633 #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) /*!< SYS_T::GPH_MFPH: PH10MFP Mask */ 1634 1635 #define SYS_GPH_MFPH_PH11MFP_Pos (12) /*!< SYS_T::GPH_MFPH: PH11MFP Position */ 1636 #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) /*!< SYS_T::GPH_MFPH: PH11MFP Mask */ 1637 1638 #define SYS_GPA_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPA_MFOS: MFOS0 Position */ 1639 #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) /*!< SYS_T::GPA_MFOS: MFOS0 Mask */ 1640 1641 #define SYS_GPA_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPA_MFOS: MFOS1 Position */ 1642 #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) /*!< SYS_T::GPA_MFOS: MFOS1 Mask */ 1643 1644 #define SYS_GPA_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPA_MFOS: MFOS2 Position */ 1645 #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) /*!< SYS_T::GPA_MFOS: MFOS2 Mask */ 1646 1647 #define SYS_GPA_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPA_MFOS: MFOS3 Position */ 1648 #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) /*!< SYS_T::GPA_MFOS: MFOS3 Mask */ 1649 1650 #define SYS_GPA_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPA_MFOS: MFOS4 Position */ 1651 #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) /*!< SYS_T::GPA_MFOS: MFOS4 Mask */ 1652 1653 #define SYS_GPA_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPA_MFOS: MFOS5 Position */ 1654 #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) /*!< SYS_T::GPA_MFOS: MFOS5 Mask */ 1655 1656 #define SYS_GPA_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPA_MFOS: MFOS6 Position */ 1657 #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) /*!< SYS_T::GPA_MFOS: MFOS6 Mask */ 1658 1659 #define SYS_GPA_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPA_MFOS: MFOS7 Position */ 1660 #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) /*!< SYS_T::GPA_MFOS: MFOS7 Mask */ 1661 1662 #define SYS_GPA_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPA_MFOS: MFOS8 Position */ 1663 #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) /*!< SYS_T::GPA_MFOS: MFOS8 Mask */ 1664 1665 #define SYS_GPA_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPA_MFOS: MFOS9 Position */ 1666 #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) /*!< SYS_T::GPA_MFOS: MFOS9 Mask */ 1667 1668 #define SYS_GPA_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPA_MFOS: MFOS10 Position */ 1669 #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) /*!< SYS_T::GPA_MFOS: MFOS10 Mask */ 1670 1671 #define SYS_GPA_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPA_MFOS: MFOS11 Position */ 1672 #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) /*!< SYS_T::GPA_MFOS: MFOS11 Mask */ 1673 1674 #define SYS_GPA_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPA_MFOS: MFOS12 Position */ 1675 #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) /*!< SYS_T::GPA_MFOS: MFOS12 Mask */ 1676 1677 #define SYS_GPA_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPA_MFOS: MFOS13 Position */ 1678 #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) /*!< SYS_T::GPA_MFOS: MFOS13 Mask */ 1679 1680 #define SYS_GPA_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPA_MFOS: MFOS14 Position */ 1681 #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) /*!< SYS_T::GPA_MFOS: MFOS14 Mask */ 1682 1683 #define SYS_GPA_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPA_MFOS: MFOS15 Position */ 1684 #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) /*!< SYS_T::GPA_MFOS: MFOS15 Mask */ 1685 1686 #define SYS_GPB_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPB_MFOS: MFOS0 Position */ 1687 #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) /*!< SYS_T::GPB_MFOS: MFOS0 Mask */ 1688 1689 #define SYS_GPB_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPB_MFOS: MFOS1 Position */ 1690 #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) /*!< SYS_T::GPB_MFOS: MFOS1 Mask */ 1691 1692 #define SYS_GPB_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPB_MFOS: MFOS2 Position */ 1693 #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) /*!< SYS_T::GPB_MFOS: MFOS2 Mask */ 1694 1695 #define SYS_GPB_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPB_MFOS: MFOS3 Position */ 1696 #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) /*!< SYS_T::GPB_MFOS: MFOS3 Mask */ 1697 1698 #define SYS_GPB_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPB_MFOS: MFOS4 Position */ 1699 #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) /*!< SYS_T::GPB_MFOS: MFOS4 Mask */ 1700 1701 #define SYS_GPB_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPB_MFOS: MFOS5 Position */ 1702 #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) /*!< SYS_T::GPB_MFOS: MFOS5 Mask */ 1703 1704 #define SYS_GPB_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPB_MFOS: MFOS6 Position */ 1705 #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) /*!< SYS_T::GPB_MFOS: MFOS6 Mask */ 1706 1707 #define SYS_GPB_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPB_MFOS: MFOS7 Position */ 1708 #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) /*!< SYS_T::GPB_MFOS: MFOS7 Mask */ 1709 1710 #define SYS_GPB_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPB_MFOS: MFOS8 Position */ 1711 #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) /*!< SYS_T::GPB_MFOS: MFOS8 Mask */ 1712 1713 #define SYS_GPB_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPB_MFOS: MFOS9 Position */ 1714 #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) /*!< SYS_T::GPB_MFOS: MFOS9 Mask */ 1715 1716 #define SYS_GPB_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPB_MFOS: MFOS10 Position */ 1717 #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) /*!< SYS_T::GPB_MFOS: MFOS10 Mask */ 1718 1719 #define SYS_GPB_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPB_MFOS: MFOS11 Position */ 1720 #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) /*!< SYS_T::GPB_MFOS: MFOS11 Mask */ 1721 1722 #define SYS_GPB_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPB_MFOS: MFOS12 Position */ 1723 #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) /*!< SYS_T::GPB_MFOS: MFOS12 Mask */ 1724 1725 #define SYS_GPB_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPB_MFOS: MFOS13 Position */ 1726 #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) /*!< SYS_T::GPB_MFOS: MFOS13 Mask */ 1727 1728 #define SYS_GPB_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPB_MFOS: MFOS14 Position */ 1729 #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) /*!< SYS_T::GPB_MFOS: MFOS14 Mask */ 1730 1731 #define SYS_GPB_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPB_MFOS: MFOS15 Position */ 1732 #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) /*!< SYS_T::GPB_MFOS: MFOS15 Mask */ 1733 1734 #define SYS_GPC_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPC_MFOS: MFOS0 Position */ 1735 #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) /*!< SYS_T::GPC_MFOS: MFOS0 Mask */ 1736 1737 #define SYS_GPC_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPC_MFOS: MFOS1 Position */ 1738 #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) /*!< SYS_T::GPC_MFOS: MFOS1 Mask */ 1739 1740 #define SYS_GPC_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPC_MFOS: MFOS2 Position */ 1741 #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) /*!< SYS_T::GPC_MFOS: MFOS2 Mask */ 1742 1743 #define SYS_GPC_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPC_MFOS: MFOS3 Position */ 1744 #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) /*!< SYS_T::GPC_MFOS: MFOS3 Mask */ 1745 1746 #define SYS_GPC_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPC_MFOS: MFOS4 Position */ 1747 #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) /*!< SYS_T::GPC_MFOS: MFOS4 Mask */ 1748 1749 #define SYS_GPC_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPC_MFOS: MFOS5 Position */ 1750 #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) /*!< SYS_T::GPC_MFOS: MFOS5 Mask */ 1751 1752 #define SYS_GPC_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPC_MFOS: MFOS6 Position */ 1753 #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) /*!< SYS_T::GPC_MFOS: MFOS6 Mask */ 1754 1755 #define SYS_GPC_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPC_MFOS: MFOS7 Position */ 1756 #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) /*!< SYS_T::GPC_MFOS: MFOS7 Mask */ 1757 1758 #define SYS_GPC_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPC_MFOS: MFOS8 Position */ 1759 #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) /*!< SYS_T::GPC_MFOS: MFOS8 Mask */ 1760 1761 #define SYS_GPC_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPC_MFOS: MFOS9 Position */ 1762 #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) /*!< SYS_T::GPC_MFOS: MFOS9 Mask */ 1763 1764 #define SYS_GPC_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPC_MFOS: MFOS10 Position */ 1765 #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) /*!< SYS_T::GPC_MFOS: MFOS10 Mask */ 1766 1767 #define SYS_GPC_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPC_MFOS: MFOS11 Position */ 1768 #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) /*!< SYS_T::GPC_MFOS: MFOS11 Mask */ 1769 1770 #define SYS_GPC_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPC_MFOS: MFOS12 Position */ 1771 #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) /*!< SYS_T::GPC_MFOS: MFOS12 Mask */ 1772 1773 #define SYS_GPC_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPC_MFOS: MFOS13 Position */ 1774 #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) /*!< SYS_T::GPC_MFOS: MFOS13 Mask */ 1775 1776 #define SYS_GPD_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPD_MFOS: MFOS0 Position */ 1777 #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) /*!< SYS_T::GPD_MFOS: MFOS0 Mask */ 1778 1779 #define SYS_GPD_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPD_MFOS: MFOS1 Position */ 1780 #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) /*!< SYS_T::GPD_MFOS: MFOS1 Mask */ 1781 1782 #define SYS_GPD_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPD_MFOS: MFOS2 Position */ 1783 #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) /*!< SYS_T::GPD_MFOS: MFOS2 Mask */ 1784 1785 #define SYS_GPD_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPD_MFOS: MFOS3 Position */ 1786 #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) /*!< SYS_T::GPD_MFOS: MFOS3 Mask */ 1787 1788 #define SYS_GPD_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPD_MFOS: MFOS4 Position */ 1789 #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) /*!< SYS_T::GPD_MFOS: MFOS4 Mask */ 1790 1791 #define SYS_GPD_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPD_MFOS: MFOS5 Position */ 1792 #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) /*!< SYS_T::GPD_MFOS: MFOS5 Mask */ 1793 1794 #define SYS_GPD_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPD_MFOS: MFOS6 Position */ 1795 #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) /*!< SYS_T::GPD_MFOS: MFOS6 Mask */ 1796 1797 #define SYS_GPD_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPD_MFOS: MFOS7 Position */ 1798 #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) /*!< SYS_T::GPD_MFOS: MFOS7 Mask */ 1799 1800 #define SYS_GPD_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPD_MFOS: MFOS8 Position */ 1801 #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) /*!< SYS_T::GPD_MFOS: MFOS8 Mask */ 1802 1803 #define SYS_GPD_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPD_MFOS: MFOS9 Position */ 1804 #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) /*!< SYS_T::GPD_MFOS: MFOS9 Mask */ 1805 1806 #define SYS_GPD_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPD_MFOS: MFOS10 Position */ 1807 #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) /*!< SYS_T::GPD_MFOS: MFOS10 Mask */ 1808 1809 #define SYS_GPD_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPD_MFOS: MFOS11 Position */ 1810 #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) /*!< SYS_T::GPD_MFOS: MFOS11 Mask */ 1811 1812 #define SYS_GPD_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPD_MFOS: MFOS12 Position */ 1813 #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) /*!< SYS_T::GPD_MFOS: MFOS12 Mask */ 1814 1815 #define SYS_GPD_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPD_MFOS: MFOS13 Position */ 1816 #define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) /*!< SYS_T::GPD_MFOS: MFOS13 Mask */ 1817 1818 #define SYS_GPD_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPD_MFOS: MFOS14 Position */ 1819 #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) /*!< SYS_T::GPD_MFOS: MFOS14 Mask */ 1820 1821 #define SYS_GPE_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPE_MFOS: MFOS0 Position */ 1822 #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) /*!< SYS_T::GPE_MFOS: MFOS0 Mask */ 1823 1824 #define SYS_GPE_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPE_MFOS: MFOS1 Position */ 1825 #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) /*!< SYS_T::GPE_MFOS: MFOS1 Mask */ 1826 1827 #define SYS_GPE_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPE_MFOS: MFOS2 Position */ 1828 #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) /*!< SYS_T::GPE_MFOS: MFOS2 Mask */ 1829 1830 #define SYS_GPE_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPE_MFOS: MFOS3 Position */ 1831 #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) /*!< SYS_T::GPE_MFOS: MFOS3 Mask */ 1832 1833 #define SYS_GPE_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPE_MFOS: MFOS4 Position */ 1834 #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) /*!< SYS_T::GPE_MFOS: MFOS4 Mask */ 1835 1836 #define SYS_GPE_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPE_MFOS: MFOS5 Position */ 1837 #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) /*!< SYS_T::GPE_MFOS: MFOS5 Mask */ 1838 1839 #define SYS_GPE_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPE_MFOS: MFOS6 Position */ 1840 #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) /*!< SYS_T::GPE_MFOS: MFOS6 Mask */ 1841 1842 #define SYS_GPE_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPE_MFOS: MFOS7 Position */ 1843 #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) /*!< SYS_T::GPE_MFOS: MFOS7 Mask */ 1844 1845 #define SYS_GPE_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPE_MFOS: MFOS8 Position */ 1846 #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) /*!< SYS_T::GPE_MFOS: MFOS8 Mask */ 1847 1848 #define SYS_GPE_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPE_MFOS: MFOS9 Position */ 1849 #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) /*!< SYS_T::GPE_MFOS: MFOS9 Mask */ 1850 1851 #define SYS_GPE_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPE_MFOS: MFOS10 Position */ 1852 #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) /*!< SYS_T::GPE_MFOS: MFOS10 Mask */ 1853 1854 #define SYS_GPE_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPE_MFOS: MFOS11 Position */ 1855 #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) /*!< SYS_T::GPE_MFOS: MFOS11 Mask */ 1856 1857 #define SYS_GPE_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPE_MFOS: MFOS12 Position */ 1858 #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) /*!< SYS_T::GPE_MFOS: MFOS12 Mask */ 1859 1860 #define SYS_GPE_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPE_MFOS: MFOS13 Position */ 1861 #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) /*!< SYS_T::GPE_MFOS: MFOS13 Mask */ 1862 1863 #define SYS_GPE_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPE_MFOS: MFOS14 Position */ 1864 #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) /*!< SYS_T::GPE_MFOS: MFOS14 Mask */ 1865 1866 #define SYS_GPE_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPE_MFOS: MFOS15 Position */ 1867 #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) /*!< SYS_T::GPE_MFOS: MFOS15 Mask */ 1868 1869 #define SYS_GPF_MFOS_MFOS0_Pos (0) /*!< SYS_T::GPF_MFOS: MFOS0 Position */ 1870 #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) /*!< SYS_T::GPF_MFOS: MFOS0 Mask */ 1871 1872 #define SYS_GPF_MFOS_MFOS1_Pos (1) /*!< SYS_T::GPF_MFOS: MFOS1 Position */ 1873 #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) /*!< SYS_T::GPF_MFOS: MFOS1 Mask */ 1874 1875 #define SYS_GPF_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPF_MFOS: MFOS2 Position */ 1876 #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) /*!< SYS_T::GPF_MFOS: MFOS2 Mask */ 1877 1878 #define SYS_GPF_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPF_MFOS: MFOS3 Position */ 1879 #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) /*!< SYS_T::GPF_MFOS: MFOS3 Mask */ 1880 1881 #define SYS_GPF_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPF_MFOS: MFOS4 Position */ 1882 #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) /*!< SYS_T::GPF_MFOS: MFOS4 Mask */ 1883 1884 #define SYS_GPF_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPF_MFOS: MFOS5 Position */ 1885 #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) /*!< SYS_T::GPF_MFOS: MFOS5 Mask */ 1886 1887 #define SYS_GPF_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPF_MFOS: MFOS6 Position */ 1888 #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) /*!< SYS_T::GPF_MFOS: MFOS6 Mask */ 1889 1890 #define SYS_GPF_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPF_MFOS: MFOS7 Position */ 1891 #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) /*!< SYS_T::GPF_MFOS: MFOS7 Mask */ 1892 1893 #define SYS_GPF_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPF_MFOS: MFOS8 Position */ 1894 #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) /*!< SYS_T::GPF_MFOS: MFOS8 Mask */ 1895 1896 #define SYS_GPF_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPF_MFOS: MFOS9 Position */ 1897 #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) /*!< SYS_T::GPF_MFOS: MFOS9 Mask */ 1898 1899 #define SYS_GPF_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPF_MFOS: MFOS10 Position */ 1900 #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) /*!< SYS_T::GPF_MFOS: MFOS10 Mask */ 1901 1902 #define SYS_GPF_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPF_MFOS: MFOS11 Position */ 1903 #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) /*!< SYS_T::GPF_MFOS: MFOS11 Mask */ 1904 1905 #define SYS_GPG_MFOS_MFOS2_Pos (2) /*!< SYS_T::GPG_MFOS: MFOS2 Position */ 1906 #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) /*!< SYS_T::GPG_MFOS: MFOS2 Mask */ 1907 1908 #define SYS_GPG_MFOS_MFOS3_Pos (3) /*!< SYS_T::GPG_MFOS: MFOS3 Position */ 1909 #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) /*!< SYS_T::GPG_MFOS: MFOS3 Mask */ 1910 1911 #define SYS_GPG_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPG_MFOS: MFOS4 Position */ 1912 #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) /*!< SYS_T::GPG_MFOS: MFOS4 Mask */ 1913 1914 #define SYS_GPG_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPG_MFOS: MFOS9 Position */ 1915 #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) /*!< SYS_T::GPG_MFOS: MFOS9 Mask */ 1916 1917 #define SYS_GPG_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPG_MFOS: MFOS10 Position */ 1918 #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) /*!< SYS_T::GPG_MFOS: MFOS10 Mask */ 1919 1920 #define SYS_GPG_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPG_MFOS: MFOS11 Position */ 1921 #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) /*!< SYS_T::GPG_MFOS: MFOS11 Mask */ 1922 1923 #define SYS_GPG_MFOS_MFOS12_Pos (12) /*!< SYS_T::GPG_MFOS: MFOS12 Position */ 1924 #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) /*!< SYS_T::GPG_MFOS: MFOS12 Mask */ 1925 1926 #define SYS_GPG_MFOS_MFOS13_Pos (13) /*!< SYS_T::GPG_MFOS: MFOS13 Position */ 1927 #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) /*!< SYS_T::GPG_MFOS: MFOS13 Mask */ 1928 1929 #define SYS_GPG_MFOS_MFOS14_Pos (14) /*!< SYS_T::GPG_MFOS: MFOS14 Position */ 1930 #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) /*!< SYS_T::GPG_MFOS: MFOS14 Mask */ 1931 1932 #define SYS_GPG_MFOS_MFOS15_Pos (15) /*!< SYS_T::GPG_MFOS: MFOS15 Position */ 1933 #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) /*!< SYS_T::GPG_MFOS: MFOS15 Mask */ 1934 1935 #define SYS_GPH_MFOS_MFOS4_Pos (4) /*!< SYS_T::GPH_MFOS: MFOS4 Position */ 1936 #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) /*!< SYS_T::GPH_MFOS: MFOS4 Mask */ 1937 1938 #define SYS_GPH_MFOS_MFOS5_Pos (5) /*!< SYS_T::GPH_MFOS: MFOS5 Position */ 1939 #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) /*!< SYS_T::GPH_MFOS: MFOS5 Mask */ 1940 1941 #define SYS_GPH_MFOS_MFOS6_Pos (6) /*!< SYS_T::GPH_MFOS: MFOS6 Position */ 1942 #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) /*!< SYS_T::GPH_MFOS: MFOS6 Mask */ 1943 1944 #define SYS_GPH_MFOS_MFOS7_Pos (7) /*!< SYS_T::GPH_MFOS: MFOS7 Position */ 1945 #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) /*!< SYS_T::GPH_MFOS: MFOS7 Mask */ 1946 1947 #define SYS_GPH_MFOS_MFOS8_Pos (8) /*!< SYS_T::GPH_MFOS: MFOS8 Position */ 1948 #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) /*!< SYS_T::GPH_MFOS: MFOS8 Mask */ 1949 1950 #define SYS_GPH_MFOS_MFOS9_Pos (9) /*!< SYS_T::GPH_MFOS: MFOS9 Position */ 1951 #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) /*!< SYS_T::GPH_MFOS: MFOS9 Mask */ 1952 1953 #define SYS_GPH_MFOS_MFOS10_Pos (10) /*!< SYS_T::GPH_MFOS: MFOS10 Position */ 1954 #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) /*!< SYS_T::GPH_MFOS: MFOS10 Mask */ 1955 1956 #define SYS_GPH_MFOS_MFOS11_Pos (11) /*!< SYS_T::GPH_MFOS: MFOS11 Position */ 1957 #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) /*!< SYS_T::GPH_MFOS: MFOS11 Mask */ 1958 1959 #define SYS_SRAMICTL_PERRIEN_Pos (0) /*!< SYS_T::SRAMICTL: PERRIEN Position */ 1960 #define SYS_SRAMICTL_PERRIEN_Msk (0x1ul << SYS_SRAMICTL_PERRIEN_Pos) /*!< SYS_T::SRAMICTL: PERRIEN Mask */ 1961 1962 #define SYS_SRAMSTS_PERRIF_Pos (0) /*!< SYS_T::SRAMSTS: PERRIF Position */ 1963 #define SYS_SRAMSTS_PERRIF_Msk (0x1ul << SYS_SRAMSTS_PERRIF_Pos) /*!< SYS_T::SRAMSTS: PERRIF Mask */ 1964 1965 #define SYS_SRAMEADR_ERRADDR_Pos (0) /*!< SYS_T::SRAMEADR: ERRADDR Position */ 1966 #define SYS_SRAMEADR_ERRADDR_Msk (0xfffffffful << SYS_SRAMEADR_ERRADDR_Pos) /*!< SYS_T::SRAMEADR: ERRADDR Mask */ 1967 1968 #define SYS_SRAMPCTL_STACK_Pos (0) /*!< SYS_T::SRAMPCTL: STACK Position */ 1969 #define SYS_SRAMPCTL_STACK_Msk (0xful << SYS_SRAMPCTL_STACK_Pos) /*!< SYS_T::SRAMPCTL: STACK Mask */ 1970 1971 #define SYS_SRAMPCTL_RETCNT_Pos (4) /*!< SYS_T::SRAMPCTL: RETCNT Position */ 1972 #define SYS_SRAMPCTL_RETCNT_Msk (0x3ul << SYS_SRAMPCTL_RETCNT_Pos) /*!< SYS_T::SRAMPCTL: RETCNT Mask */ 1973 1974 #define SYS_SRAMPCTL_SRAM0PM0_Pos (8) /*!< SYS_T::SRAMPCTL: SRAM0PM0 Position */ 1975 #define SYS_SRAMPCTL_SRAM0PM0_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM0_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM0 Mask */ 1976 1977 #define SYS_SRAMPCTL_SRAM0PM1_Pos (10) /*!< SYS_T::SRAMPCTL: SRAM0PM1 Position */ 1978 #define SYS_SRAMPCTL_SRAM0PM1_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM1_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM1 Mask */ 1979 1980 #define SYS_SRAMPCTL_SRAM0PM2_Pos (12) /*!< SYS_T::SRAMPCTL: SRAM0PM2 Position */ 1981 #define SYS_SRAMPCTL_SRAM0PM2_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM2_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM2 Mask */ 1982 1983 #define SYS_SRAMPCTL_SRAM0PM3_Pos (14) /*!< SYS_T::SRAMPCTL: SRAM0PM3 Position */ 1984 #define SYS_SRAMPCTL_SRAM0PM3_Msk (0x3ul << SYS_SRAMPCTL_SRAM0PM3_Pos) /*!< SYS_T::SRAMPCTL: SRAM0PM3 Mask */ 1985 1986 #define SYS_SRAMPCTL_SRAM1PM0_Pos (16) /*!< SYS_T::SRAMPCTL: SRAM1PM0 Position */ 1987 #define SYS_SRAMPCTL_SRAM1PM0_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM0_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM0 Mask */ 1988 1989 #define SYS_SRAMPCTL_SRAM1PM1_Pos (18) /*!< SYS_T::SRAMPCTL: SRAM1PM1 Position */ 1990 #define SYS_SRAMPCTL_SRAM1PM1_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM1_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM1 Mask */ 1991 1992 #define SYS_SRAMPCTL_SRAM1PM2_Pos (20) /*!< SYS_T::SRAMPCTL: SRAM1PM2 Position */ 1993 #define SYS_SRAMPCTL_SRAM1PM2_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM2_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM2 Mask */ 1994 1995 #define SYS_SRAMPCTL_SRAM1PM3_Pos (22) /*!< SYS_T::SRAMPCTL: SRAM1PM3 Position */ 1996 #define SYS_SRAMPCTL_SRAM1PM3_Msk (0x3ul << SYS_SRAMPCTL_SRAM1PM3_Pos) /*!< SYS_T::SRAMPCTL: SRAM1PM3 Mask */ 1997 1998 #define SYS_SRAMPPCT_CAN_Pos (0) /*!< SYS_T::SRAMPPCT: CAN Position */ 1999 #define SYS_SRAMPPCT_CAN_Msk (0x3ul << SYS_SRAMPPCT_CAN_Pos) /*!< SYS_T::SRAMPPCT: CAN Mask */ 2000 2001 #define SYS_SRAMPPCT_USBD_Pos (2) /*!< SYS_T::SRAMPPCT: USBD Position */ 2002 #define SYS_SRAMPPCT_USBD_Msk (0x3ul << SYS_SRAMPPCT_USBD_Pos) /*!< SYS_T::SRAMPPCT: USBD Mask */ 2003 2004 #define SYS_SRAMPPCT_PDMA0_Pos (4) /*!< SYS_T::SRAMPPCT: PDMA0 Position */ 2005 #define SYS_SRAMPPCT_PDMA0_Msk (0x3ul << SYS_SRAMPPCT_PDMA0_Pos) /*!< SYS_T::SRAMPPCT: PDMA0 Mask */ 2006 2007 #define SYS_SRAMPPCT_PDMA1_Pos (6) /*!< SYS_T::SRAMPPCT: PDMA1 Position */ 2008 #define SYS_SRAMPPCT_PDMA1_Msk (0x3ul << SYS_SRAMPPCT_PDMA1_Pos) /*!< SYS_T::SRAMPPCT: PDMA1 Mask */ 2009 2010 #define SYS_SRAMPPCT_FMC_Pos (8) /*!< SYS_T::SRAMPPCT: FMC Position */ 2011 #define SYS_SRAMPPCT_FMC_Msk (0x3ul << SYS_SRAMPPCT_FMC_Pos) /*!< SYS_T::SRAMPPCT: FMC Mask */ 2012 2013 #define SYS_TCTL48M_FREQSEL_Pos (0) /*!< SYS_T::TCTL48M: FREQSEL Position */ 2014 #define SYS_TCTL48M_FREQSEL_Msk (0x3ul << SYS_TCTL48M_FREQSEL_Pos) /*!< SYS_T::TCTL48M: FREQSEL Mask */ 2015 2016 #define SYS_TCTL48M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL48M: LOOPSEL Position */ 2017 #define SYS_TCTL48M_LOOPSEL_Msk (0x3ul << SYS_TCTL48M_LOOPSEL_Pos) /*!< SYS_T::TCTL48M: LOOPSEL Mask */ 2018 2019 #define SYS_TCTL48M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL48M: RETRYCNT Position */ 2020 #define SYS_TCTL48M_RETRYCNT_Msk (0x3ul << SYS_TCTL48M_RETRYCNT_Pos) /*!< SYS_T::TCTL48M: RETRYCNT Mask */ 2021 2022 #define SYS_TCTL48M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL48M: CESTOPEN Position */ 2023 #define SYS_TCTL48M_CESTOPEN_Msk (0x1ul << SYS_TCTL48M_CESTOPEN_Pos) /*!< SYS_T::TCTL48M: CESTOPEN Mask */ 2024 2025 #define SYS_TCTL48M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL48M: REFCKSEL Position */ 2026 #define SYS_TCTL48M_REFCKSEL_Msk (0x1ul << SYS_TCTL48M_REFCKSEL_Pos) /*!< SYS_T::TCTL48M: REFCKSEL Mask */ 2027 2028 #define SYS_TIEN48M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN48M: TFAILIEN Position */ 2029 #define SYS_TIEN48M_TFAILIEN_Msk (0x1ul << SYS_TIEN48M_TFAILIEN_Pos) /*!< SYS_T::TIEN48M: TFAILIEN Mask */ 2030 2031 #define SYS_TIEN48M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN48M: CLKEIEN Position */ 2032 #define SYS_TIEN48M_CLKEIEN_Msk (0x1ul << SYS_TIEN48M_CLKEIEN_Pos) /*!< SYS_T::TIEN48M: CLKEIEN Mask */ 2033 2034 #define SYS_TISTS48M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS48M: FREQLOCK Position */ 2035 #define SYS_TISTS48M_FREQLOCK_Msk (0x1ul << SYS_TISTS48M_FREQLOCK_Pos) /*!< SYS_T::TISTS48M: FREQLOCK Mask */ 2036 2037 #define SYS_TISTS48M_TFAILIF_Pos (1) /*!< SYS_T::TISTS48M: TFAILIF Position */ 2038 #define SYS_TISTS48M_TFAILIF_Msk (0x1ul << SYS_TISTS48M_TFAILIF_Pos) /*!< SYS_T::TISTS48M: TFAILIF Mask */ 2039 2040 #define SYS_TISTS48M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS48M: CLKERRIF Position */ 2041 #define SYS_TISTS48M_CLKERRIF_Msk (0x1ul << SYS_TISTS48M_CLKERRIF_Pos) /*!< SYS_T::TISTS48M: CLKERRIF Mask */ 2042 2043 #define SYS_TCTL12M_FREQSEL_Pos (0) /*!< SYS_T::TCTL12M: FREQSEL Position */ 2044 #define SYS_TCTL12M_FREQSEL_Msk (0x3ul << SYS_TCTL12M_FREQSEL_Pos) /*!< SYS_T::TCTL12M: FREQSEL Mask */ 2045 2046 #define SYS_TCTL12M_LOOPSEL_Pos (4) /*!< SYS_T::TCTL12M: LOOPSEL Position */ 2047 #define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */ 2048 2049 #define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */ 2050 #define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12M_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */ 2051 2052 #define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */ 2053 #define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */ 2054 2055 #define SYS_TCTL12M_REFCKSEL_Pos (10) /*!< SYS_T::TCTL12M: REFCKSEL Position */ 2056 #define SYS_TCTL12M_REFCKSEL_Msk (0x1ul << SYS_TCTL12M_REFCKSEL_Pos) /*!< SYS_T::TCTL12M: REFCKSEL Mask */ 2057 2058 #define SYS_TIEN12M_TFAILIEN_Pos (1) /*!< SYS_T::TIEN12M: TFAILIEN Position */ 2059 #define SYS_TIEN12M_TFAILIEN_Msk (0x1ul << SYS_TIEN12M_TFAILIEN_Pos) /*!< SYS_T::TIEN12M: TFAILIEN Mask */ 2060 2061 #define SYS_TIEN12M_CLKEIEN_Pos (2) /*!< SYS_T::TIEN12M: CLKEIEN Position */ 2062 #define SYS_TIEN12M_CLKEIEN_Msk (0x1ul << SYS_TIEN12M_CLKEIEN_Pos) /*!< SYS_T::TIEN12M: CLKEIEN Mask */ 2063 2064 #define SYS_TISTS12M_FREQLOCK_Pos (0) /*!< SYS_T::TISTS12M: FREQLOCK Position */ 2065 #define SYS_TISTS12M_FREQLOCK_Msk (0x1ul << SYS_TISTS12M_FREQLOCK_Pos) /*!< SYS_T::TISTS12M: FREQLOCK Mask */ 2066 2067 #define SYS_TISTS12M_TFAILIF_Pos (1) /*!< SYS_T::TISTS12M: TFAILIF Position */ 2068 #define SYS_TISTS12M_TFAILIF_Msk (0x1ul << SYS_TISTS12M_TFAILIF_Pos) /*!< SYS_T::TISTS12M: TFAILIF Mask */ 2069 2070 #define SYS_TISTS12M_CLKERRIF_Pos (2) /*!< SYS_T::TISTS12M: CLKERRIF Position */ 2071 #define SYS_TISTS12M_CLKERRIF_Msk (0x1ul << SYS_TISTS12M_CLKERRIF_Pos) /*!< SYS_T::TISTS12M: CLKERRIF Mask */ 2072 2073 #define SYS_REGLCTL_REGLCTL_Pos (0) /*!< SYS_T::REGLCTL: REGLCTL Position */ 2074 #define SYS_REGLCTL_REGLCTL_Msk (0xfful << SYS_REGLCTL_REGLCTL_Pos) /*!< SYS_T::REGLCTL: REGLCTL Mask */ 2075 2076 #define SYS_PORCTL1_POROFF_Pos (0) /*!< SYS_T::PORCTL1: POROFF Position */ 2077 #define SYS_PORCTL1_POROFF_Msk (0xfffful << SYS_PORCTL1_POROFF_Pos) /*!< SYS_T::PORCTL1: POROFF Mask */ 2078 2079 #define SYS_PLCTL_PLSEL_Pos (0) /*!< SYS_T::PLCTL: PLSEL Position */ 2080 #define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) /*!< SYS_T::PLCTL: PLSEL Mask */ 2081 2082 #define SYS_PLCTL_MVRS_Pos (4) /*!< SYS_T::PLCTL: MVRS Position */ 2083 #define SYS_PLCTL_MVRS_Msk (0x1ul << SYS_PLCTL_MVRS_Pos) /*!< SYS_T::PLCTL: MVRS Mask */ 2084 2085 #define SYS_PLCTL_LVSSTP_Pos (16) /*!< SYS_T::PLCTL: LVSSTP Position */ 2086 #define SYS_PLCTL_LVSSTP_Msk (0x3ful << SYS_PLCTL_LVSSTP_Pos) /*!< SYS_T::PLCTL: LVSSTP Mask */ 2087 2088 #define SYS_PLCTL_LVSPRD_Pos (24) /*!< SYS_T::PLCTL: LVSPRD Position */ 2089 #define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) /*!< SYS_T::PLCTL: LVSPRD Mask */ 2090 2091 #define SYS_PLSTS_PLCBUSY_Pos (0) /*!< SYS_T::PLSTS: PLCBUSY Position */ 2092 #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) /*!< SYS_T::PLSTS: PLCBUSY Mask */ 2093 2094 #define SYS_PLSTS_MVRCBUSY_Pos (1) /*!< SYS_T::PLSTS: MVRCBUSY Position */ 2095 #define SYS_PLSTS_MVRCBUSY_Msk (0x1ul << SYS_PLSTS_MVRCBUSY_Pos) /*!< SYS_T::PLSTS: MVRCBUSY Mask */ 2096 2097 #define SYS_PLSTS_MVRCERR_Pos (2) /*!< SYS_T::PLSTS: MVRCERR Position */ 2098 #define SYS_PLSTS_MVRCERR_Msk (0x1ul << SYS_PLSTS_MVRCERR_Pos) /*!< SYS_T::PLSTS: MVRCERR Mask */ 2099 2100 #define SYS_PLSTS_LCONS_Pos (3) /*!< SYS_T::PLSTS: LCONS Position */ 2101 #define SYS_PLSTS_LCONS_Msk (0x1ul << SYS_PLSTS_LCONS_Pos) /*!< SYS_T::PLSTS: LCONS Mask */ 2102 2103 #define SYS_PLSTS_PDINVTRF_Pos (4) /*!< SYS_T::PLSTS: PDINVTRF Position */ 2104 #define SYS_PLSTS_PDINVTRF_Msk (0x1ul << SYS_PLSTS_PDINVTRF_Pos) /*!< SYS_T::PLSTS: PDINVTRF Mask */ 2105 2106 #define SYS_PLSTS_PLSTATUS_Pos (8) /*!< SYS_T::PLSTS: PLSTATUS Position */ 2107 #define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) /*!< SYS_T::PLSTS: PLSTATUS Mask */ 2108 2109 #define SYS_PLSTS_CURMVR_Pos (12) /*!< SYS_T::PLSTS: CURMVR Position */ 2110 #define SYS_PLSTS_CURMVR_Msk (0x1ul << SYS_PLSTS_CURMVR_Pos) /*!< SYS_T::PLSTS: CURMVR Mask */ 2111 2112 #define SYS_AHBMCTL_INTACTEN_Pos (0) /*!< SYS_T::AHBMCTL: INTACTEN Position */ 2113 #define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) /*!< SYS_T::AHBMCTL: INTACTEN Mask */ 2114 2115 2116 /**@}*/ /* SYS_CONST */ 2117 typedef struct 2118 { 2119 2120 /** 2121 * @var SYS_INT_T::NMIEN 2122 * Offset: 0x00 NMI Source Interrupt Enable Register 2123 * --------------------------------------------------------------------------------------------------- 2124 * |Bits |Field |Descriptions 2125 * | :----: | :----: | :---- | 2126 * |[0] |BODOUT |BOD NMI Source Enable (Write Protect) 2127 * | | |0 = BOD NMI source Disabled. 2128 * | | |1 = BOD NMI source Enabled. 2129 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2130 * |[1] |IRCINT |IRC TRIM NMI Source Enable (Write Protect) 2131 * | | |0 = IRC TRIM NMI source Disabled. 2132 * | | |1 = IRC TRIM NMI source Enabled. 2133 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2134 * |[2] |PWRWUINT |Power-down Mode Wake-up NMI Source Enable (Write Protect) 2135 * | | |0 = Power-down mode wake-up NMI source Disabled. 2136 * | | |1 = Power-down mode wake-up NMI source Enabled. 2137 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2138 * |[3] |SRAMPERR |SRAM Parity Check Error NMI Source Enable (Write Protect) 2139 * | | |0 = SRAM parity check error NMI source Disabled. 2140 * | | |1 = SRAM parity check error NMI source Enabled. 2141 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2142 * |[4] |CLKFAIL |Clock Fail Detected NMI Source Enable (Write Protect) 2143 * | | |0 = Clock fail detected interrupt NMI source Disabled. 2144 * | | |1 = Clock fail detected interrupt NMI source Enabled. 2145 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2146 * |[6] |RTCINT |RTC NMI Source Enable (Write Protect) 2147 * | | |0 = RTC NMI source Disabled. 2148 * | | |1 = RTC NMI source Enabled. 2149 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2150 * |[7] |TAMPERINT |Tamper Interrupt NMI Source Enable (Write Protect) 2151 * | | |0 = Backup register tamper detected interrupt NMI source Disabled. 2152 * | | |1 = Backup register tamper detected interrupt NMI source Enabled. 2153 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2154 * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin NMI Source Enable (Write Protect) 2155 * | | |0 = External interrupt from PA.6, or PB.5 pin NMI source Disabled. 2156 * | | |1 = External interrupt from PA.6, or PB.5 pin NMI source Enabled. 2157 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2158 * |[9] |EINT1 |External Interrupt From PA.7 or PB.4 Pin NMI Source Enable (Write Protect) 2159 * | | |0 = External interrupt from PA.7 or PB.4 pin NMI source Disabled. 2160 * | | |1 = External interrupt from PA.7 or P4.4 pin NMI source Enabled. 2161 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2162 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin NMI Source Enable (Write Protect) 2163 * | | |0 = External interrupt from PB.3 or PC.6 pin NMI source Disabled. 2164 * | | |1 = External interrupt from PB.3 or PC.6 pin NMI source Enabled. 2165 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2166 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin NMI Source Enable (Write Protect) 2167 * | | |0 = External interrupt from PB.2 or PC.7pin NMI source Disabled. 2168 * | | |1 = External interrupt from PB.2 or PC.7 pin NMI source Enabled. 2169 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2170 * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin NMI Source Enable (Write Protect) 2171 * | | |0 = External interrupt from PA.8 or PB.6 pin NMI source Disabled. 2172 * | | |1 = External interrupt from PA.8 or PB.6 pin NMI source Enabled. 2173 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2174 * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin NMI Source Enable (Write Protect) 2175 * | | |0 = External interrupt from PB.7 or PD.12 pin NMI source Disabled. 2176 * | | |1 = External interrupt from PB.7 or PD.12 pin NMI source Enabled. 2177 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2178 * |[14] |UART0INT |UART0 NMI Source Enable (Write Protect) 2179 * | | |0 = UART0 NMI source Disabled. 2180 * | | |1 = UART0 NMI source Enabled. 2181 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2182 * |[15] |UART1INT |UART1 NMI Source Enable (Write Protect) 2183 * | | |0 = UART1 NMI source Disabled. 2184 * | | |1 = UART1 NMI source Enabled. 2185 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2186 * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin NMI Source Enable (Write Protect) 2187 * | | |0 = External interrupt from PB.8 or PD.11 pin NMI source Disabled. 2188 * | | |1 = External interrupt from PB.8 or PD.11 pin NMI source Enabled. 2189 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2190 * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin NMI Source Enable (Write Protect) 2191 * | | |0 = External interrupt from PB.9 or PD.10 pin NMI source Disabled. 2192 * | | |1 = External interrupt from PB.9 or PD.10 pin NMI source Enabled. 2193 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 2194 * @var SYS_INT_T::NMISTS 2195 * Offset: 0x04 NMI source interrupt Status Register 2196 * --------------------------------------------------------------------------------------------------- 2197 * |Bits |Field |Descriptions 2198 * | :----: | :----: | :---- | 2199 * |[0] |BODOUT |BOD Interrupt Flag (Read Only) 2200 * | | |0 = BOD interrupt is de-asserted. 2201 * | | |1 = BOD interrupt is asserted. 2202 * |[1] |IRCINT |IRC TRIM Interrupt Flag (Read Only) 2203 * | | |0 = HIRC TRIM interrupt is de-asserted. 2204 * | | |1 = HIRC TRIM interrupt is asserted. 2205 * |[2] |PWRWUINT |Power-down Mode Wake-up Interrupt Flag (Read Only) 2206 * | | |0 = Power-down mode wake-up interrupt is de-asserted. 2207 * | | |1 = Power-down mode wake-up interrupt is asserted. 2208 * |[3] |SRAMPERR |SRAM Parity Check Error Interrupt Flag (Read Only) 2209 * | | |0 = SRAM parity check error interrupt is de-asserted. 2210 * | | |1 = SRAM parity check error interrupt is asserted. 2211 * |[4] |CLKFAIL |Clock Fail Detected Interrupt Flag (Read Only) 2212 * | | |0 = Clock fail detected interrupt is de-asserted. 2213 * | | |1 = Clock fail detected interrupt is asserted. 2214 * |[6] |RTCINT |RTC Interrupt Flag (Read Only) 2215 * | | |0 = RTC interrupt is de-asserted. 2216 * | | |1 = RTC interrupt is asserted. 2217 * |[7] |TAMPERINT |Tamper Interrupt Flag (Read Only) 2218 * | | |0 = Backup register tamper detected interrupt is de-asserted. 2219 * | | |1 = Backup register tamper detected interrupt is asserted. 2220 * |[8] |EINT0 |External Interrupt From PA.6, or PB.5 Pin Interrupt Flag (Read Only) 2221 * | | |0 = External Interrupt from PA.6, or PB.5 interrupt is deasserted. 2222 * | | |1 = External Interrupt from PA.6, or PB.5 interrupt is asserted. 2223 * |[9] |EINT1 |External Interrupt From PA.7, or PB.4 Pin Interrupt Flag (Read Only) 2224 * | | |0 = External Interrupt from PA.7, or PB.4 interrupt is deasserted. 2225 * | | |1 = External Interrupt from PA.7, or PB.4 interrupt is asserted. 2226 * |[10] |EINT2 |External Interrupt From PB.3 or PC.6 Pin Interrupt Flag (Read Only) 2227 * | | |0 = External Interrupt from PB.3 or PC.6 interrupt is deasserted. 2228 * | | |1 = External Interrupt from PB.3 or PC.6 interrupt is asserted. 2229 * |[11] |EINT3 |External Interrupt From PB.2 or PC.7 Pin Interrupt Flag (Read Only) 2230 * | | |0 = External Interrupt from PB.2 or PC.7 interrupt is deasserted. 2231 * | | |1 = External Interrupt from PB.2 or PC.7 interrupt is asserted. 2232 * |[12] |EINT4 |External Interrupt From PA.8 or PB.6 Pin Interrupt Flag (Read Only) 2233 * | | |0 = External Interrupt from PA.8 or PB.6 interrupt is deasserted. 2234 * | | |1 = External Interrupt from PA.8 or PB.6 interrupt is asserted. 2235 * |[13] |EINT5 |External Interrupt From PB.7 or PD.12 Pin Interrupt Flag (Read Only) 2236 * | | |0 = External Interrupt from PB.7 or PD.12 interrupt is deasserted. 2237 * | | |1 = External Interrupt from PB.7 or PD.12 interrupt is asserted. 2238 * |[14] |UART0INT |UART0 Interrupt Flag (Read Only) 2239 * | | |0 = UART1 interrupt is de-asserted. 2240 * | | |1 = UART1 interrupt is asserted. 2241 * |[15] |UART1INT |UART1 Interrupt Flag (Read Only) 2242 * | | |0 = UART1 interrupt is de-asserted. 2243 * | | |1 = UART1 interrupt is asserted. 2244 * |[16] |EINT6 |External Interrupt From PB.8 or PD.11 Pin Interrupt Flag (Read Only) 2245 * | | |0 = External Interrupt from PB.8 or PD.11 interrupt is deasserted. 2246 * | | |1 = External Interrupt from PB.8 or PD.11 interrupt is asserted. 2247 * |[17] |EINT7 |External Interrupt From PB.9 or PD.10 Pin Interrupt Flag (Read Only) 2248 * | | |0 = External Interrupt from PB.9 or PD.10 interrupt is deasserted. 2249 * | | |1 = External Interrupt from PB.9 or PD.10 interrupt is asserted. 2250 */ 2251 2252 __IO uint32_t NMIEN; /* Offset: 0x00 NMI Source Interrupt Enable Register */ 2253 __I uint32_t NMISTS; /* Offset: 0x04 NMI source interrupt Status Register */ 2254 2255 } SYS_INT_T; 2256 /** 2257 @addtogroup INT_CONST INT Bit Field Definition 2258 Constant Definitions for INT Controller 2259 @{ */ 2260 2261 #define SYS_NMIEN_BODOUT_Pos (0) /*!< SYS_INT_T::NMIEN: BODOUT Position */ 2262 #define SYS_NMIEN_BODOUT_Msk (0x1ul << SYS_NMIEN_BODOUT_Pos ) /*!< SYS_INT_T::NMIEN: BODOUT Mask */ 2263 2264 #define SYS_NMIEN_IRCINT_Pos (1) /*!< SYS_INT_T::NMIEN: IRCINT Position */ 2265 #define SYS_NMIEN_IRCINT_Msk (0x1ul << SYS_NMIEN_IRCINT_Pos ) /*!< SYS_INT_T::NMIEN: IRCINT Mask */ 2266 2267 #define SYS_NMIEN_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMIEN: PWRWUINT Position */ 2268 #define SYS_NMIEN_PWRWUINT_Msk (0x1ul << SYS_NMIEN_PWRWUINT_Pos ) /*!< SYS_INT_T::NMIEN: PWRWUINT Mask */ 2269 2270 #define SYS_NMIEN_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMIEN: SRAMPERR Position */ 2271 #define SYS_NMIEN_SRAMPERR_Msk (0x1ul << SYS_NMIEN_SRAMPERR_Pos ) /*!< SYS_INT_T::NMIEN: SRAMPERR Mask */ 2272 2273 #define SYS_NMIEN_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMIEN: CLKFAIL Position */ 2274 #define SYS_NMIEN_CLKFAIL_Msk (0x1ul << SYS_NMIEN_CLKFAIL_Pos ) /*!< SYS_INT_T::NMIEN: CLKFAIL Mask */ 2275 2276 #define SYS_NMIEN_RTCINT_Pos (6) /*!< SYS_INT_T::NMIEN: RTCINT Position */ 2277 #define SYS_NMIEN_RTCINT_Msk (0x1ul << SYS_NMIEN_RTCINT_Pos ) /*!< SYS_INT_T::NMIEN: RTCINT Mask */ 2278 2279 #define SYS_NMIEN_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMIEN: TAMPERINT Position */ 2280 #define SYS_NMIEN_TAMPERINT_Msk (0x1ul << SYS_NMIEN_TAMPERINT_Pos ) /*!< SYS_INT_T::NMIEN: TAMPERINT Mask */ 2281 2282 #define SYS_NMIEN_EINT0_Pos (8) /*!< SYS_INT_T::NMIEN: EINT0 Position */ 2283 #define SYS_NMIEN_EINT0_Msk (0x1ul << SYS_NMIEN_EINT0_Pos ) /*!< SYS_INT_T::NMIEN: EINT0 Mask */ 2284 2285 #define SYS_NMIEN_EINT1_Pos (9) /*!< SYS_INT_T::NMIEN: EINT1 Position */ 2286 #define SYS_NMIEN_EINT1_Msk (0x1ul << SYS_NMIEN_EINT1_Pos ) /*!< SYS_INT_T::NMIEN: EINT1 Mask */ 2287 2288 #define SYS_NMIEN_EINT2_Pos (10) /*!< SYS_INT_T::NMIEN: EINT2 Position */ 2289 #define SYS_NMIEN_EINT2_Msk (0x1ul << SYS_NMIEN_EINT2_Pos ) /*!< SYS_INT_T::NMIEN: EINT2 Mask */ 2290 2291 #define SYS_NMIEN_EINT3_Pos (11) /*!< SYS_INT_T::NMIEN: EINT3 Position */ 2292 #define SYS_NMIEN_EINT3_Msk (0x1ul << SYS_NMIEN_EINT3_Pos ) /*!< SYS_INT_T::NMIEN: EINT3 Mask */ 2293 2294 #define SYS_NMIEN_EINT4_Pos (12) /*!< SYS_INT_T::NMIEN: EINT4 Position */ 2295 #define SYS_NMIEN_EINT4_Msk (0x1ul << SYS_NMIEN_EINT4_Pos ) /*!< SYS_INT_T::NMIEN: EINT4 Mask */ 2296 2297 #define SYS_NMIEN_EINT5_Pos (13) /*!< SYS_INT_T::NMIEN: EINT5 Position */ 2298 #define SYS_NMIEN_EINT5_Msk (0x1ul << SYS_NMIEN_EINT5_Pos ) /*!< SYS_INT_T::NMIEN: EINT5 Mask */ 2299 2300 #define SYS_NMIEN_UART0INT_Pos (14) /*!< SYS_INT_T::NMIEN: UART0INT Position */ 2301 #define SYS_NMIEN_UART0INT_Msk (0x1ul << SYS_NMIEN_UART0INT_Pos ) /*!< SYS_INT_T::NMIEN: UART0INT Mask */ 2302 2303 #define SYS_NMIEN_UART1INT_Pos (15) /*!< SYS_INT_T::NMIEN: UART1INT Position */ 2304 #define SYS_NMIEN_UART1INT_Msk (0x1ul << SYS_NMIEN_UART1INT_Pos ) /*!< SYS_INT_T::NMIEN: UART1INT Mask */ 2305 2306 #define SYS_NMIEN_EINT6_Pos (16) /*!< SYS_INT_T::NMIEN: EINT6 Position */ 2307 #define SYS_NMIEN_EINT6_Msk (0x1ul << SYS_NMIEN_EINT6_Pos ) /*!< SYS_INT_T::NMIEN: EINT6 Mask */ 2308 2309 #define SYS_NMIEN_EINT7_Pos (17) /*!< SYS_INT_T::NMIEN: EINT7 Position */ 2310 #define SYS_NMIEN_EINT7_Msk (0x1ul << SYS_NMIEN_EINT7_Pos ) /*!< SYS_INT_T::NMIEN: EINT7 Mask */ 2311 2312 #define SYS_NMISTS_BODOUT_Pos (0) /*!< SYS_INT_T::NMISTS: BODOUT Position */ 2313 #define SYS_NMISTS_BODOUT_Msk (0x1ul << SYS_NMISTS_BODOUT_Pos ) /*!< SYS_INT_T::NMISTS: BODOUT Mask */ 2314 2315 #define SYS_NMISTS_IRCINT_Pos (1) /*!< SYS_INT_T::NMISTS: IRCINT Position */ 2316 #define SYS_NMISTS_IRCINT_Msk (0x1ul << SYS_NMISTS_IRCINT_Pos ) /*!< SYS_INT_T::NMISTS: IRCINT Mask */ 2317 2318 #define SYS_NMISTS_PWRWUINT_Pos (2) /*!< SYS_INT_T::NMISTS: PWRWUINT Position */ 2319 #define SYS_NMISTS_PWRWUINT_Msk (0x1ul << SYS_NMISTS_PWRWUINT_Pos ) /*!< SYS_INT_T::NMISTS: PWRWUINT Mask */ 2320 2321 #define SYS_NMISTS_SRAMPERR_Pos (3) /*!< SYS_INT_T::NMISTS: SRAMPERR Position */ 2322 #define SYS_NMISTS_SRAMPERR_Msk (0x1ul << SYS_NMISTS_SRAMPERR_Pos ) /*!< SYS_INT_T::NMISTS: SRAMPERR Mask */ 2323 2324 #define SYS_NMISTS_CLKFAIL_Pos (4) /*!< SYS_INT_T::NMISTS: CLKFAIL Position */ 2325 #define SYS_NMISTS_CLKFAIL_Msk (0x1ul << SYS_NMISTS_CLKFAIL_Pos ) /*!< SYS_INT_T::NMISTS: CLKFAIL Mask */ 2326 2327 #define SYS_NMISTS_RTCINT_Pos (6) /*!< SYS_INT_T::NMISTS: RTCINT Position */ 2328 #define SYS_NMISTS_RTCINT_Msk (0x1ul << SYS_NMISTS_RTCINT_Pos ) /*!< SYS_INT_T::NMISTS: RTCINT Mask */ 2329 2330 #define SYS_NMISTS_TAMPERINT_Pos (7) /*!< SYS_INT_T::NMISTS: TAMPERINT Position */ 2331 #define SYS_NMISTS_TAMPERINT_Msk (0x1ul << SYS_NMISTS_TAMPERINT_Pos ) /*!< SYS_INT_T::NMISTS: TAMPERINT Mask */ 2332 2333 #define SYS_NMISTS_EINT0_Pos (8) /*!< SYS_INT_T::NMISTS: EINT0 Position */ 2334 #define SYS_NMISTS_EINT0_Msk (0x1ul << SYS_NMISTS_EINT0_Pos ) /*!< SYS_INT_T::NMISTS: EINT0 Mask */ 2335 2336 #define SYS_NMISTS_EINT1_Pos (9) /*!< SYS_INT_T::NMISTS: EINT1 Position */ 2337 #define SYS_NMISTS_EINT1_Msk (0x1ul << SYS_NMISTS_EINT1_Pos ) /*!< SYS_INT_T::NMISTS: EINT1 Mask */ 2338 2339 #define SYS_NMISTS_EINT2_Pos (10) /*!< SYS_INT_T::NMISTS: EINT2 Position */ 2340 #define SYS_NMISTS_EINT2_Msk (0x1ul << SYS_NMISTS_EINT2_Pos ) /*!< SYS_INT_T::NMISTS: EINT2 Mask */ 2341 2342 #define SYS_NMISTS_EINT3_Pos (11) /*!< SYS_INT_T::NMISTS: EINT3 Position */ 2343 #define SYS_NMISTS_EINT3_Msk (0x1ul << SYS_NMISTS_EINT3_Pos ) /*!< SYS_INT_T::NMISTS: EINT3 Mask */ 2344 2345 #define SYS_NMISTS_EINT4_Pos (12) /*!< SYS_INT_T::NMISTS: EINT4 Position */ 2346 #define SYS_NMISTS_EINT4_Msk (0x1ul << SYS_NMISTS_EINT4_Pos ) /*!< SYS_INT_T::NMISTS: EINT4 Mask */ 2347 2348 #define SYS_NMISTS_EINT5_Pos (13) /*!< SYS_INT_T::NMISTS: EINT5 Position */ 2349 #define SYS_NMISTS_EINT5_Msk (0x1ul << SYS_NMISTS_EINT5_Pos ) /*!< SYS_INT_T::NMISTS: EINT5 Mask */ 2350 2351 #define SYS_NMISTS_UART0INT_Pos (14) /*!< SYS_INT_T::NMISTS: UART0_INT Position */ 2352 #define SYS_NMISTS_UART0INT_Msk (0x1ul << SYS_NMISTS_UART0INT_Pos ) /*!< SYS_INT_T::NMISTS: UART0_INT Mask */ 2353 2354 #define SYS_NMISTS_UART1INT_Pos (15) /*!< SYS_INT_T::NMISTS: UART1_INT Position */ 2355 #define SYS_NMISTS_UART1INT_Msk (0x1ul << SYS_NMISTS_UART1INT_Pos ) /*!< SYS_INT_T::NMISTS: UART1_INT Mask */ 2356 2357 #define SYS_NMISTS_EINT6_Pos (16) /*!< SYS_INT_T::NMISTS: EINT6 Position */ 2358 #define SYS_NMISTS_EINT6_Msk (0x1ul << SYS_NMISTS_EINT6_Pos ) /*!< SYS_INT_T::NMISTS: EINT6 Mask */ 2359 2360 #define SYS_NMISTS_EINT7_Pos (17) /*!< SYS_INT_T::NMISTS: EINT7 Position */ 2361 #define SYS_NMISTS_EINT7_Msk (0x1ul << SYS_NMISTS_EINT7_Pos ) /*!< SYS_INT_T::NMISTS: EINT7 Mask */ 2362 2363 2364 /**@}*/ /* INT_CONST */ 2365 /**@}*/ /* end of SYS register group */ 2366 /**@}*/ /* end of REGISTER group */ 2367 2368 2369 #endif /* __SYS_REG_H__ */ 2370
