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Searched defs:SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK (Results 1 – 2 of 2) sorted by relevance

/hal_openisa-latest/vega_sdk_riscv/devices/RV32M1/
DRV32M1_ri5cy.h19095 #define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK (0xC00U) macro
DRV32M1_zero_riscy.h19923 #define SPM_DCDCSC_DCDC_VBAT_DIV_CTRL_MASK (0xC00U) macro