1 // Copyright 2010-2019 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #include "esp_err.h" 18 #include "freertos/FreeRTOS.h" 19 //for spi_bus_initialization funcions. to be back-compatible 20 #include "driver/spi_common.h" 21 22 /** SPI master clock is divided by 80MHz apb clock. Below defines are example frequencies, and are accurate. Be free to specify a random frequency, it will be rounded to closest frequency (to macros below if above 8MHz). 23 * 8MHz 24 */ 25 #define SPI_MASTER_FREQ_8M (APB_CLK_FREQ/10) 26 #define SPI_MASTER_FREQ_9M (APB_CLK_FREQ/9) ///< 8.89MHz 27 #define SPI_MASTER_FREQ_10M (APB_CLK_FREQ/8) ///< 10MHz 28 #define SPI_MASTER_FREQ_11M (APB_CLK_FREQ/7) ///< 11.43MHz 29 #define SPI_MASTER_FREQ_13M (APB_CLK_FREQ/6) ///< 13.33MHz 30 #define SPI_MASTER_FREQ_16M (APB_CLK_FREQ/5) ///< 16MHz 31 #define SPI_MASTER_FREQ_20M (APB_CLK_FREQ/4) ///< 20MHz 32 #define SPI_MASTER_FREQ_26M (APB_CLK_FREQ/3) ///< 26.67MHz 33 #define SPI_MASTER_FREQ_40M (APB_CLK_FREQ/2) ///< 40MHz 34 #define SPI_MASTER_FREQ_80M (APB_CLK_FREQ/1) ///< 80MHz 35 #ifdef __cplusplus 36 extern "C" 37 { 38 #endif 39 40 #define SPI_DEVICE_TXBIT_LSBFIRST (1<<0) ///< Transmit command/address/data LSB first instead of the default MSB first 41 #define SPI_DEVICE_RXBIT_LSBFIRST (1<<1) ///< Receive data LSB first instead of the default MSB first 42 #define SPI_DEVICE_BIT_LSBFIRST (SPI_DEVICE_TXBIT_LSBFIRST|SPI_DEVICE_RXBIT_LSBFIRST) ///< Transmit and receive LSB first 43 #define SPI_DEVICE_3WIRE (1<<2) ///< Use MOSI (=spid) for both sending and receiving data 44 #define SPI_DEVICE_POSITIVE_CS (1<<3) ///< Make CS positive during a transaction instead of negative 45 #define SPI_DEVICE_HALFDUPLEX (1<<4) ///< Transmit data before receiving it, instead of simultaneously 46 #define SPI_DEVICE_CLK_AS_CS (1<<5) ///< Output clock on CS line if CS is active 47 /** There are timing issue when reading at high frequency (the frequency is related to whether iomux pins are used, valid time after slave sees the clock). 48 * - In half-duplex mode, the driver automatically inserts dummy bits before reading phase to fix the timing issue. Set this flag to disable this feature. 49 * - In full-duplex mode, however, the hardware cannot use dummy bits, so there is no way to prevent data being read from getting corrupted. 50 * Set this flag to confirm that you're going to work with output only, or read without dummy bits at your own risk. 51 */ 52 #define SPI_DEVICE_NO_DUMMY (1<<6) 53 #define SPI_DEVICE_DDRCLK (1<<7) 54 55 56 typedef struct spi_transaction_t spi_transaction_t; 57 typedef void(*transaction_cb_t)(spi_transaction_t *trans); 58 59 /** 60 * @brief This is a configuration for a SPI slave device that is connected to one of the SPI buses. 61 */ 62 typedef struct { 63 uint8_t command_bits; ///< Default amount of bits in command phase (0-16), used when ``SPI_TRANS_VARIABLE_CMD`` is not used, otherwise ignored. 64 uint8_t address_bits; ///< Default amount of bits in address phase (0-64), used when ``SPI_TRANS_VARIABLE_ADDR`` is not used, otherwise ignored. 65 uint8_t dummy_bits; ///< Amount of dummy bits to insert between address and data phase 66 uint8_t mode; /**< SPI mode, representing a pair of (CPOL, CPHA) configuration: 67 - 0: (0, 0) 68 - 1: (0, 1) 69 - 2: (1, 0) 70 - 3: (1, 1) 71 */ 72 uint16_t duty_cycle_pos; ///< Duty cycle of positive clock, in 1/256th increments (128 = 50%/50% duty). Setting this to 0 (=not setting it) is equivalent to setting this to 128. 73 uint16_t cs_ena_pretrans; ///< Amount of SPI bit-cycles the cs should be activated before the transmission (0-16). This only works on half-duplex transactions. 74 uint8_t cs_ena_posttrans; ///< Amount of SPI bit-cycles the cs should stay active after the transmission (0-16) 75 int clock_speed_hz; ///< Clock speed, divisors of 80MHz, in Hz. See ``SPI_MASTER_FREQ_*``. 76 int input_delay_ns; /**< Maximum data valid time of slave. The time required between SCLK and MISO 77 valid, including the possible clock delay from slave to master. The driver uses this value to give an extra 78 delay before the MISO is ready on the line. Leave at 0 unless you know you need a delay. For better timing 79 performance at high frequency (over 8MHz), it's suggest to have the right value. 80 */ 81 int spics_io_num; ///< CS GPIO pin for this device, or -1 if not used 82 uint32_t flags; ///< Bitwise OR of SPI_DEVICE_* flags 83 int queue_size; ///< Transaction queue size. This sets how many transactions can be 'in the air' (queued using spi_device_queue_trans but not yet finished using spi_device_get_trans_result) at the same time 84 transaction_cb_t pre_cb; /**< Callback to be called before a transmission is started. 85 * 86 * This callback is called within interrupt 87 * context should be in IRAM for best 88 * performance, see "Transferring Speed" 89 * section in the SPI Master documentation for 90 * full details. If not, the callback may crash 91 * during flash operation when the driver is 92 * initialized with ESP_INTR_FLAG_IRAM. 93 */ 94 transaction_cb_t post_cb; /**< Callback to be called after a transmission has completed. 95 * 96 * This callback is called within interrupt 97 * context should be in IRAM for best 98 * performance, see "Transferring Speed" 99 * section in the SPI Master documentation for 100 * full details. If not, the callback may crash 101 * during flash operation when the driver is 102 * initialized with ESP_INTR_FLAG_IRAM. 103 */ 104 } spi_device_interface_config_t; 105 106 107 #define SPI_TRANS_MODE_DIO (1<<0) ///< Transmit/receive data in 2-bit mode 108 #define SPI_TRANS_MODE_QIO (1<<1) ///< Transmit/receive data in 4-bit mode 109 #define SPI_TRANS_USE_RXDATA (1<<2) ///< Receive into rx_data member of spi_transaction_t instead into memory at rx_buffer. 110 #define SPI_TRANS_USE_TXDATA (1<<3) ///< Transmit tx_data member of spi_transaction_t instead of data at tx_buffer. Do not set tx_buffer when using this. 111 #define SPI_TRANS_MODE_DIOQIO_ADDR (1<<4) ///< Also transmit address in mode selected by SPI_MODE_DIO/SPI_MODE_QIO 112 #define SPI_TRANS_VARIABLE_CMD (1<<5) ///< Use the ``command_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``. 113 #define SPI_TRANS_VARIABLE_ADDR (1<<6) ///< Use the ``address_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``. 114 #define SPI_TRANS_VARIABLE_DUMMY (1<<7) ///< Use the ``dummy_bits`` in ``spi_transaction_ext_t`` rather than default value in ``spi_device_interface_config_t``. 115 #define SPI_TRANS_SET_CD (1<<7) ///< Set the CD pin 116 117 /** 118 * This structure describes one SPI transaction. The descriptor should not be modified until the transaction finishes. 119 */ 120 struct spi_transaction_t { 121 uint32_t flags; ///< Bitwise OR of SPI_TRANS_* flags 122 uint16_t cmd; /**< Command data, of which the length is set in the ``command_bits`` of spi_device_interface_config_t. 123 * 124 * <b>NOTE: this field, used to be "command" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF 3.0.</b> 125 * 126 * Example: write 0x0123 and command_bits=12 to send command 0x12, 0x3_ (in previous version, you may have to write 0x3_12). 127 */ 128 uint64_t addr; /**< Address data, of which the length is set in the ``address_bits`` of spi_device_interface_config_t. 129 * 130 * <b>NOTE: this field, used to be "address" in ESP-IDF 2.1 and before, is re-written to be used in a new way in ESP-IDF3.0.</b> 131 * 132 * Example: write 0x123400 and address_bits=24 to send address of 0x12, 0x34, 0x00 (in previous version, you may have to write 0x12340000). 133 */ 134 size_t length; ///< Total data length, in bits 135 size_t rxlength; ///< Total data length received, should be not greater than ``length`` in full-duplex mode (0 defaults this to the value of ``length``). 136 void *user; ///< User-defined variable. Can be used to store eg transaction ID. 137 union { 138 const void *tx_buffer; ///< Pointer to transmit buffer, or NULL for no MOSI phase 139 uint8_t tx_data[4]; ///< If SPI_TRANS_USE_TXDATA is set, data set here is sent directly from this variable. 140 }; 141 union { 142 void *rx_buffer; ///< Pointer to receive buffer, or NULL for no MISO phase. Written by 4 bytes-unit if DMA is used. 143 uint8_t rx_data[4]; ///< If SPI_TRANS_USE_RXDATA is set, data is received directly to this variable 144 }; 145 } ; //the rx data should start from a 32-bit aligned address to get around dma issue. 146 147 /** 148 * This struct is for SPI transactions which may change their address and command length. 149 * Please do set the flags in base to ``SPI_TRANS_VARIABLE_CMD_ADR`` to use the bit length here. 150 */ 151 typedef struct { 152 struct spi_transaction_t base; ///< Transaction data, so that pointer to spi_transaction_t can be converted into spi_transaction_ext_t 153 uint8_t command_bits; ///< The command length in this transaction, in bits. 154 uint8_t address_bits; ///< The address length in this transaction, in bits. 155 uint8_t dummy_bits; ///< The dummy length in this transaction, in bits. 156 } spi_transaction_ext_t ; 157 158 159 typedef struct spi_device_t* spi_device_handle_t; ///< Handle for a device on a SPI bus 160 /** 161 * @brief Allocate a device on a SPI bus 162 * 163 * This initializes the internal structures for a device, plus allocates a CS pin on the indicated SPI master 164 * peripheral and routes it to the indicated GPIO. All SPI master devices have three CS pins and can thus control 165 * up to three devices. 166 * 167 * @note While in general, speeds up to 80MHz on the dedicated SPI pins and 40MHz on GPIO-matrix-routed pins are 168 * supported, full-duplex transfers routed over the GPIO matrix only support speeds up to 26MHz. 169 * 170 * @param host_id SPI peripheral to allocate device on 171 * @param dev_config SPI interface protocol config for the device 172 * @param handle Pointer to variable to hold the device handle 173 * @return 174 * - ESP_ERR_INVALID_ARG if parameter is invalid 175 * - ESP_ERR_NOT_FOUND if host doesn't have any free CS slots 176 * - ESP_ERR_NO_MEM if out of memory 177 * - ESP_OK on success 178 */ 179 esp_err_t spi_bus_add_device(spi_host_device_t host_id, const spi_device_interface_config_t *dev_config, spi_device_handle_t *handle); 180 181 182 /** 183 * @brief Remove a device from the SPI bus 184 * 185 * @param handle Device handle to free 186 * @return 187 * - ESP_ERR_INVALID_ARG if parameter is invalid 188 * - ESP_ERR_INVALID_STATE if device already is freed 189 * - ESP_OK on success 190 */ 191 esp_err_t spi_bus_remove_device(spi_device_handle_t handle); 192 193 194 /** 195 * @brief Queue a SPI transaction for interrupt transaction execution. Get the result by ``spi_device_get_trans_result``. 196 * 197 * @note Normally a device cannot start (queue) polling and interrupt 198 * transactions simultaneously. 199 * 200 * @param handle Device handle obtained using spi_host_add_dev 201 * @param trans_desc Description of transaction to execute 202 * @param ticks_to_wait Ticks to wait until there's room in the queue; use portMAX_DELAY to 203 * never time out. 204 * @return 205 * - ESP_ERR_INVALID_ARG if parameter is invalid 206 * - ESP_ERR_TIMEOUT if there was no room in the queue before ticks_to_wait expired 207 * - ESP_ERR_NO_MEM if allocating DMA-capable temporary buffer failed 208 * - ESP_ERR_INVALID_STATE if previous transactions are not finished 209 * - ESP_OK on success 210 */ 211 esp_err_t spi_device_queue_trans(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait); 212 213 214 /** 215 * @brief Get the result of a SPI transaction queued earlier by ``spi_device_queue_trans``. 216 * 217 * This routine will wait until a transaction to the given device 218 * succesfully completed. It will then return the description of the 219 * completed transaction so software can inspect the result and e.g. free the memory or 220 * re-use the buffers. 221 * 222 * @param handle Device handle obtained using spi_host_add_dev 223 * @param trans_desc Pointer to variable able to contain a pointer to the description of the transaction 224 that is executed. The descriptor should not be modified until the descriptor is returned by 225 spi_device_get_trans_result. 226 * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time 227 out. 228 * @return 229 * - ESP_ERR_INVALID_ARG if parameter is invalid 230 * - ESP_ERR_TIMEOUT if there was no completed transaction before ticks_to_wait expired 231 * - ESP_OK on success 232 */ 233 esp_err_t spi_device_get_trans_result(spi_device_handle_t handle, spi_transaction_t **trans_desc, TickType_t ticks_to_wait); 234 235 236 /** 237 * @brief Send a SPI transaction, wait for it to complete, and return the result 238 * 239 * This function is the equivalent of calling spi_device_queue_trans() followed by spi_device_get_trans_result(). 240 * Do not use this when there is still a transaction separately queued (started) from spi_device_queue_trans() or polling_start/transmit that hasn't been finalized. 241 * 242 * @note This function is not thread safe when multiple tasks access the same SPI device. 243 * Normally a device cannot start (queue) polling and interrupt 244 * transactions simutanuously. 245 * 246 * @param handle Device handle obtained using spi_host_add_dev 247 * @param trans_desc Description of transaction to execute 248 * @return 249 * - ESP_ERR_INVALID_ARG if parameter is invalid 250 * - ESP_OK on success 251 */ 252 esp_err_t spi_device_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc); 253 254 255 /** 256 * @brief Immediately start a polling transaction. 257 * 258 * @note Normally a device cannot start (queue) polling and interrupt 259 * transactions simutanuously. Moreover, a device cannot start a new polling 260 * transaction if another polling transaction is not finished. 261 * 262 * @param handle Device handle obtained using spi_host_add_dev 263 * @param trans_desc Description of transaction to execute 264 * @param ticks_to_wait Ticks to wait until there's room in the queue; 265 * currently only portMAX_DELAY is supported. 266 * 267 * @return 268 * - ESP_ERR_INVALID_ARG if parameter is invalid 269 * - ESP_ERR_TIMEOUT if the device cannot get control of the bus before ``ticks_to_wait`` expired 270 * - ESP_ERR_NO_MEM if allocating DMA-capable temporary buffer failed 271 * - ESP_ERR_INVALID_STATE if previous transactions are not finished 272 * - ESP_OK on success 273 */ 274 esp_err_t spi_device_polling_start(spi_device_handle_t handle, spi_transaction_t *trans_desc, TickType_t ticks_to_wait); 275 276 277 /** 278 * @brief Poll until the polling transaction ends. 279 * 280 * This routine will not return until the transaction to the given device has 281 * succesfully completed. The task is not blocked, but actively busy-spins for 282 * the transaction to be completed. 283 * 284 * @param handle Device handle obtained using spi_host_add_dev 285 * @param ticks_to_wait Ticks to wait until there's a returned item; use portMAX_DELAY to never time 286 out. 287 * @return 288 * - ESP_ERR_INVALID_ARG if parameter is invalid 289 * - ESP_ERR_TIMEOUT if the transaction cannot finish before ticks_to_wait expired 290 * - ESP_OK on success 291 */ 292 esp_err_t spi_device_polling_end(spi_device_handle_t handle, TickType_t ticks_to_wait); 293 294 295 /** 296 * @brief Send a polling transaction, wait for it to complete, and return the result 297 * 298 * This function is the equivalent of calling spi_device_polling_start() followed by spi_device_polling_end(). 299 * Do not use this when there is still a transaction that hasn't been finalized. 300 * 301 * @note This function is not thread safe when multiple tasks access the same SPI device. 302 * Normally a device cannot start (queue) polling and interrupt 303 * transactions simutanuously. 304 * 305 * @param handle Device handle obtained using spi_host_add_dev 306 * @param trans_desc Description of transaction to execute 307 * @return 308 * - ESP_ERR_INVALID_ARG if parameter is invalid 309 * - ESP_OK on success 310 */ 311 esp_err_t spi_device_polling_transmit(spi_device_handle_t handle, spi_transaction_t *trans_desc); 312 313 314 /** 315 * @brief Occupy the SPI bus for a device to do continuous transactions. 316 * 317 * Transactions to all other devices will be put off until ``spi_device_release_bus`` is called. 318 * 319 * @note The function will wait until all the existing transactions have been sent. 320 * 321 * @param device The device to occupy the bus. 322 * @param wait Time to wait before the the bus is occupied by the device. Currently MUST set to portMAX_DELAY. 323 * 324 * @return 325 * - ESP_ERR_INVALID_ARG : ``wait`` is not set to portMAX_DELAY. 326 * - ESP_OK : Success. 327 */ 328 esp_err_t spi_device_acquire_bus(spi_device_handle_t device, TickType_t wait); 329 330 /** 331 * @brief Release the SPI bus occupied by the device. All other devices can start sending transactions. 332 * 333 * @param dev The device to release the bus. 334 */ 335 void spi_device_release_bus(spi_device_handle_t dev); 336 337 338 /** 339 * @brief Calculate the working frequency that is most close to desired frequency, and also the register value. 340 * 341 * @param fapb The frequency of apb clock, should be ``APB_CLK_FREQ``. 342 * @param hz Desired working frequency 343 * @param duty_cycle Duty cycle of the spi clock 344 * @param reg_o Output of value to be set in clock register, or NULL if not needed. 345 * 346 * @deprecated The app shouldn't care about the register. Call ``spi_get_actual_clock`` instead. 347 * 348 * @return Actual working frequency that most fit. 349 */ 350 int spi_cal_clock(int fapb, int hz, int duty_cycle, uint32_t* reg_o) __attribute__((deprecated)); 351 352 /** 353 * @brief Calculate the working frequency that is most close to desired frequency. 354 * 355 * @param fapb The frequency of apb clock, should be ``APB_CLK_FREQ``. 356 * @param hz Desired working frequency 357 * @param duty_cycle Duty cycle of the spi clock 358 * 359 * @return Actual working frequency that most fit. 360 */ 361 int spi_get_actual_clock(int fapb, int hz, int duty_cycle); 362 363 /** 364 * @brief Calculate the timing settings of specified frequency and settings. 365 * 366 * @param gpio_is_used True if using GPIO matrix, or False if iomux pins are used. 367 * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid. 368 * @param eff_clk Effective clock frequency (in Hz) from spi_cal_clock. 369 * @param dummy_o Address of dummy bits used output. Set to NULL if not needed. 370 * @param cycles_remain_o Address of cycles remaining (after dummy bits are used) output. 371 * - -1 If too many cycles remaining, suggest to compensate half a clock. 372 * - 0 If no remaining cycles or dummy bits are not used. 373 * - positive value: cycles suggest to compensate. 374 * 375 * @note If **dummy_o* is not zero, it means dummy bits should be applied in half duplex mode, and full duplex mode may not work. 376 */ 377 void spi_get_timing(bool gpio_is_used, int input_delay_ns, int eff_clk, int* dummy_o, int* cycles_remain_o); 378 379 /** 380 * @brief Get the frequency limit of current configurations. 381 * SPI master working at this limit is OK, while above the limit, full duplex mode and DMA will not work, 382 * and dummy bits will be aplied in the half duplex mode. 383 * 384 * @param gpio_is_used True if using GPIO matrix, or False if native pins are used. 385 * @param input_delay_ns Input delay from SCLK launch edge to MISO data valid. 386 * @return Frequency limit of current configurations. 387 */ 388 int spi_get_freq_limit(bool gpio_is_used, int input_delay_ns); 389 390 #ifdef __cplusplus 391 } 392 #endif 393
