1 /******************************************************************************
2  *
3  * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
4  * Analog Devices, Inc.),
5  * Copyright (C) 2023-2024 Analog Devices, Inc.
6  *
7  * Licensed under the Apache License, Version 2.0 (the "License");
8  * you may not use this file except in compliance with the License.
9  * You may obtain a copy of the License at
10  *
11  *     http://www.apache.org/licenses/LICENSE-2.0
12  *
13  * Unless required by applicable law or agreed to in writing, software
14  * distributed under the License is distributed on an "AS IS" BASIS,
15  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16  * See the License for the specific language governing permissions and
17  * limitations under the License.
18  *
19  ******************************************************************************/
20 
21 #ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA1_H_
22 #define LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA1_H_
23 
24 #include <stdio.h>
25 #include <stddef.h>
26 #include <stdint.h>
27 #include "mxc_device.h"
28 #include "mxc_assert.h"
29 #include "mxc_lock.h"
30 #include "mxc_sys.h"
31 #include "mxc_delay.h"
32 #include "spi_regs.h"
33 #include "spi_reva_regs.h"
34 #include "spi.h"
35 #include "dma.h"
36 
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40 
41 typedef enum {
42     SPI_REVA_WIDTH_3WIRE,
43     SPI_REVA_WIDTH_STANDARD,
44     SPI_REVA_WIDTH_DUAL,
45     SPI_REVA_WIDTH_QUAD,
46 } mxc_spi_reva_width_t;
47 
48 typedef enum {
49     SPI_REVA_MODE_0,
50     SPI_REVA_MODE_1,
51     SPI_REVA_MODE_2,
52     SPI_REVA_MODE_3,
53 } mxc_spi_reva_mode_t;
54 
55 typedef struct _mxc_spi_reva_req_t mxc_spi_reva_req_t;
56 
57 struct _mxc_spi_reva_req_t {
58     mxc_spi_reva_regs_t *spi;
59     int ssIdx;
60     int ssDeassert;
61     uint8_t *txData;
62     uint8_t *rxData;
63     uint32_t txLen;
64     uint32_t rxLen;
65     uint32_t txCnt;
66     uint32_t rxCnt;
67     spi_complete_cb_t completeCB;
68 };
69 
70 int MXC_SPI_RevA1_Init(mxc_spi_reva_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves,
71                        unsigned ssPolarity, unsigned int hz);
72 int MXC_SPI_RevA1_Shutdown(mxc_spi_reva_regs_t *spi);
73 int MXC_SPI_RevA1_ReadyForSleep(mxc_spi_reva_regs_t *spi);
74 int MXC_SPI_RevA1_SetFrequency(mxc_spi_reva_regs_t *spi, unsigned int hz);
75 unsigned int MXC_SPI_RevA1_GetFrequency(mxc_spi_reva_regs_t *spi);
76 int MXC_SPI_RevA1_SetDataSize(mxc_spi_reva_regs_t *spi, int dataSize);
77 int MXC_SPI_RevA1_GetDataSize(mxc_spi_reva_regs_t *spi);
78 int MXC_SPI_RevA1_SetMTMode(mxc_spi_reva_regs_t *spi, int mtMode);
79 int MXC_SPI_RevA1_GetMTMode(mxc_spi_reva_regs_t *spi);
80 int MXC_SPI_RevA1_SetSlave(mxc_spi_reva_regs_t *spi, int ssIdx);
81 int MXC_SPI_RevA1_GetSlave(mxc_spi_reva_regs_t *spi);
82 int MXC_SPI_RevA1_SetWidth(mxc_spi_reva_regs_t *spi, mxc_spi_reva_width_t spiWidth);
83 mxc_spi_reva_width_t MXC_SPI_RevA1_GetWidth(mxc_spi_reva_regs_t *spi);
84 int MXC_SPI_RevA1_SetMode(mxc_spi_reva_regs_t *spi, mxc_spi_reva_mode_t spiMode);
85 mxc_spi_reva_mode_t MXC_SPI_RevA1_GetMode(mxc_spi_reva_regs_t *spi);
86 int MXC_SPI_RevA1_StartTransmission(mxc_spi_reva_regs_t *spi);
87 int MXC_SPI_RevA1_GetActive(mxc_spi_reva_regs_t *spi);
88 int MXC_SPI_RevA1_AbortTransmission(mxc_spi_reva_regs_t *spi);
89 unsigned int MXC_SPI_RevA1_ReadRXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes,
90                                       unsigned int len);
91 unsigned int MXC_SPI_RevA1_WriteTXFIFO(mxc_spi_reva_regs_t *spi, unsigned char *bytes,
92                                        unsigned int len);
93 unsigned int MXC_SPI_RevA1_GetTXFIFOAvailable(mxc_spi_reva_regs_t *spi);
94 unsigned int MXC_SPI_RevA1_GetRXFIFOAvailable(mxc_spi_reva_regs_t *spi);
95 void MXC_SPI_RevA1_ClearRXFIFO(mxc_spi_reva_regs_t *spi);
96 void MXC_SPI_RevA1_ClearTXFIFO(mxc_spi_reva_regs_t *spi);
97 int MXC_SPI_RevA1_SetRXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes);
98 unsigned int MXC_SPI_RevA1_GetRXThreshold(mxc_spi_reva_regs_t *spi);
99 int MXC_SPI_RevA1_SetTXThreshold(mxc_spi_reva_regs_t *spi, unsigned int numBytes);
100 unsigned int MXC_SPI_RevA1_GetTXThreshold(mxc_spi_reva_regs_t *spi);
101 unsigned int MXC_SPI_RevA1_GetFlags(mxc_spi_reva_regs_t *spi);
102 void MXC_SPI_RevA1_ClearFlags(mxc_spi_reva_regs_t *spi);
103 void MXC_SPI_RevA1_EnableInt(mxc_spi_reva_regs_t *spi, unsigned int mask);
104 void MXC_SPI_RevA1_DisableInt(mxc_spi_reva_regs_t *spi, unsigned int mask);
105 int MXC_SPI_RevA1_MasterTransaction(mxc_spi_reva_req_t *req);
106 int MXC_SPI_RevA1_MasterTransactionAsync(mxc_spi_reva_req_t *req);
107 int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx,
108                                        mxc_dma_regs_t *dma);
109 int MXC_SPI_RevA1_SlaveTransaction(mxc_spi_reva_req_t *req);
110 int MXC_SPI_RevA1_SlaveTransactionAsync(mxc_spi_reva_req_t *req);
111 int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int reqselRx,
112                                       mxc_dma_regs_t *dma);
113 void MXC_SPI_RevA1_DMACallback(int ch, int error);
114 int MXC_SPI_RevA1_SetDefaultTXData(mxc_spi_reva_regs_t *spi, unsigned int defaultTXData);
115 void MXC_SPI_RevA1_AbortAsync(mxc_spi_reva_regs_t *spi);
116 void MXC_SPI_RevA1_AsyncHandler(mxc_spi_reva_regs_t *spi);
117 void MXC_SPI_RevA1_HWSSControl(mxc_spi_reva_regs_t *spi, int state);
118 
119 #ifdef __cplusplus
120 }
121 #endif
122 
123 #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_SPI_SPI_REVA1_H_
124