1 /**************************************************************************//** 2 * @file spi_reg.h 3 * @version V1.00 4 * @brief SPI register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright Copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SPI_REG_H__ 10 #define __SPI_REG_H__ 11 12 /** @addtogroup REGISTER Control Register 13 14 @{ 15 16 */ 17 18 /*---------------------- Serial Peripheral Interface Controller -------------------------*/ 19 /** 20 @addtogroup SPI Serial Peripheral Interface Controller(SPI) 21 Memory Mapped Structure for SPI Controller 22 @{ 23 */ 24 25 typedef struct 26 { 27 28 29 /** 30 * @var SPI_T::CTL 31 * Offset: 0x00 SPI Control Register 32 * --------------------------------------------------------------------------------------------------- 33 * |Bits |Field |Descriptions 34 * | :----: | :----: | :---- | 35 * |[0] |SPIEN |SPI Transfer Control Enable Bit 36 * | | |In Master mode, the transfer will start when there is data in the FIFO buffer after this bit is set to 1 37 * | | |In Slave mode, this device is ready to receive data when this bit is set to 1. 38 * | | |0 = Transfer control Disabled. 39 * | | |1 = Transfer control Enabled. 40 * | | |Note: Before changing the configurations of SPIx_CTL, SPIx_CLKDIV, SPIx_SSCTL and SPIx_FIFOCTL registers, user shall clear the SPIEN (SPIx_CTL[0]) and confirm the SPIENSTS (SPIx_STATUS[15]) is 0. 41 * |[1] |RXNEG |Receive on Negative Edge 42 * | | |0 = Received data input signal is latched on the rising edge of SPI bus clock. 43 * | | |1 = Received data input signal is latched on the falling edge of SPI bus clock. 44 * |[2] |TXNEG |Transmit on Negative Edge 45 * | | |0 = Transmitted data output signal is changed on the rising edge of SPI bus clock. 46 * | | |1 = Transmitted data output signal is changed on the falling edge of SPI bus clock. 47 * |[3] |CLKPOL |Clock Polarity 48 * | | |0 = SPI bus clock is idle low. 49 * | | |1 = SPI bus clock is idle high. 50 * |[7:4] |SUSPITV |Suspend Interval (Master Only) 51 * | | |The four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer 52 * | | |The definition of the suspend interval is the interval between the last clock edge of the preceding transaction word and the first clock edge of the following transaction word 53 * | | |The default value is 0x3 54 * | | |The period of the suspend interval is obtained according to the following equation. 55 * | | |(SUSPITV[3:0] + 0.5) * period of SPICLK clock cycle 56 * | | |Example: 57 * | | |SUSPITV = 0x0 .... 0.5 SPICLK clock cycle. 58 * | | |SUSPITV = 0x1 .... 1.5 SPICLK clock cycle. 59 * | | |..... 60 * | | |SUSPITV = 0xE .... 14.5 SPICLK clock cycle. 61 * | | |SUSPITV = 0xF .... 15.5 SPICLK clock cycle. 62 * |[12:8] |DWIDTH |Data Width 63 * | | |This field specifies how many bits can be transmitted / received in one transaction 64 * | | |The minimum bit length is 8 bits and can up to 32 bits. 65 * | | |DWIDTH = 0x08 .... 8 bits. 66 * | | |DWIDTH = 0x09 .... 9 bits. 67 * | | |..... 68 * | | |DWIDTH = 0x1F .... 31 bits. 69 * | | |DWIDTH = 0x00 .... 32 bits. 70 * | | |Note: For SPI0~SPI3, this bit field will decide the depth of TX/RX FIFO configuration in SPI mode 71 * | | |Therefore, changing this bit field will clear TX/RX FIFO by hardware automatically in SPI0~SPI3. 72 * |[13] |LSB |Send LSB First 73 * | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH, is transmitted/received first. 74 * | | |1 = The LSB, bit 0 of the SPI TX register, is sent first to the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (bit 0 of SPI_RX). 75 * |[14] |HALFDPX |SPI Half-duplex Transfer Enable Bit 76 * | | |This bit is used to select full-duplex or half-duplex for SPI transfer 77 * | | |The bit field DATDIR (SPIx_CTL[20]) can be used to set the data direction in half-duplex transfer. 78 * | | |0 = SPI operates in full-duplex transfer. 79 * | | |1 = SPI operates in half-duplex transfer. 80 * |[15] |RXONLY |Receive-only Mode Enable Bit (Master Only) 81 * | | |This bit field is only available in Master mode 82 * | | |In receive-only mode, SPI Master will generate SPI bus clock continuously for receiving data bit from SPI slave device and assert the BUSY status. 83 * | | |0 = Receive-only mode Disabled. 84 * | | |1 = Receive-only mode Enabled. 85 * |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit 86 * | | |0 = SPI unit transfer interrupt Disabled. 87 * | | |1 = SPI unit transfer interrupt Enabled. 88 * |[18] |SLAVE |Slave Mode Control 89 * | | |0 = Master mode. 90 * | | |1 = Slave mode. 91 * |[19] |REORDER |Byte Reorder Function Enable Bit 92 * | | |0 = Byte Reorder function Disabled. 93 * | | |1 = Byte Reorder function Enabled 94 * | | |A byte suspend interval will be inserted among each byte 95 * | | |The period of the byte suspend interval depends on the setting of SUSPITV. 96 * | | |Note: Byte Reorder function is only available if DWIDTH is defined as 16, 24, and 32 bits. 97 * |[20] |DATDIR |Data Port Direction Control 98 * | | |This bit is used to select the data input/output direction in half-duplex transfer and Dual/Quad transfer 99 * | | |0 = SPI data is input direction. 100 * | | |1 = SPI data is output direction. 101 * @var SPI_T::CLKDIV 102 * Offset: 0x04 SPI Clock Divider Register 103 * --------------------------------------------------------------------------------------------------- 104 * |Bits |Field |Descriptions 105 * | :----: | :----: | :---- | 106 * |[8:0] |DIVIDER |Clock Divider 107 * | | |The value in this field is the frequency divider for generating the peripheral clock, fspi_eclk, and the SPI bus clock of SPI Master 108 * | | |The frequency is obtained according to the following equation. 109 * | | |where 110 * | | |is the peripheral clock source, which is defined in the clock control register, CLK_CLKSEL2. 111 * | | |Note 1: Not supported in I2S mode. 112 * | | |Note 2: The time interval must be larger than or equal 5 peripheral clock cycles between releasing SPI IP software reset and setting this clock divider register. 113 * @var SPI_T::SSCTL 114 * Offset: 0x08 SPI Slave Select Control Register 115 * --------------------------------------------------------------------------------------------------- 116 * |Bits |Field |Descriptions 117 * | :----: | :----: | :---- | 118 * |[0] |SS |Slave Selection Control 119 * | | |If AUTOSS bit is cleared to 0, 120 * | | |0 = set the SPIx_SS line to inactive state. 121 * | | |1 = set the SPIx_SS line to active state. 122 * | | |If the AUTOSS bit is set to 1, 123 * | | |0 = Keep the SPIx_SS line at inactive state. 124 * | | |1 = SPIx_SS line will be automatically driven to active state for the duration of data transfer, and will be driven to inactive state for the rest of the time 125 * | | |The active state of SPIx_SS is specified in SSACTPOL (SPIx_SSCTL[2]). 126 * | | |Note: Master mode only. 127 * |[2] |SSACTPOL |Slave Selection Active Polarity 128 * | | |This bit defines the active polarity of slave selection signal (SPIx_SS). 129 * | | |0 = The slave selection signal SPIx_SS is active low. 130 * | | |1 = The slave selection signal SPIx_SS is active high. 131 * |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only) 132 * | | |0 = Automatic slave selection function Disabled 133 * | | |Slave selection signal will be asserted/de-asserted according to SS (SPIx_SSCTL[0]). 134 * | | |1 = Automatic slave selection function Enabled. 135 * | | |Note: Master mode only. 136 * |[4] |SLV3WIRE |Slave 3-wire Mode Enable Bit 137 * | | |In Slave 3-wire mode, the SPI controller can work with 3-wire interface including SPIx_CLK, SPIx_MISO and SPIx_MOSI pins. 138 * | | |0 = 4-wire bi-direction interface. 139 * | | |1 = 3-wire bi-direction interface. 140 * | | |Note: The value of this register equals to control register SLAVE (SPIx_I2SCTL[8]) when I2S mode is enabled. 141 * |[8] |SLVBEIEN |Slave Mode Bit Count Error Interrupt Enable Bit 142 * | | |0 = Slave mode bit count error interrupt Disabled. 143 * | | |1 = Slave mode bit count error interrupt Enabled. 144 * |[9] |SLVURIEN |Slave Mode TX Under Run Interrupt Enable Bit 145 * | | |0 = Slave mode TX under run interrupt Disabled. 146 * | | |1 = Slave mode TX under run interrupt Enabled. 147 * |[12] |SSACTIEN |Slave Select Active Interrupt Enable Bit 148 * | | |0 = Slave select active interrupt Disabled. 149 * | | |1 = Slave select active interrupt Enabled. 150 * |[13] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit 151 * | | |0 = Slave select inactive interrupt Disabled. 152 * | | |1 = Slave select inactive interrupt Enabled. 153 * @var SPI_T::PDMACTL 154 * Offset: 0x0C SPI PDMA Control Register 155 * --------------------------------------------------------------------------------------------------- 156 * |Bits |Field |Descriptions 157 * | :----: | :----: | :---- | 158 * |[0] |TXPDMAEN |Transmit PDMA Enable Bit 159 * | | |0 = Transmit PDMA function Disabled. 160 * | | |1 = Transmit PDMA function Enabled. 161 * | | |Note: In SPI Master mode with full duplex transfer, if both TX and RX PDMA functions are enabled, RX PDMA function cannot be enabled prior to TX PDMA function 162 * | | |User can enable TX PDMA function firstly or enable both functions simultaneously. 163 * |[1] |RXPDMAEN |Receive PDMA Enable Bit 164 * | | |0 = Receive PDMA function Disabled. 165 * | | |1 = Receive PDMA function Enabled. 166 * |[2] |PDMARST |PDMA Reset 167 * | | |0 = No effect. 168 * | | |1 = Reset the PDMA control logic of the SPI controller. This bit will be automatically cleared to 0. 169 * @var SPI_T::FIFOCTL 170 * Offset: 0x10 SPI FIFO Control Register 171 * --------------------------------------------------------------------------------------------------- 172 * |Bits |Field |Descriptions 173 * | :----: | :----: | :---- | 174 * |[0] |RXRST |Receive Reset 175 * | | |0 = No effect. 176 * | | |1 = Reset receive FIFO pointer and receive circuit 177 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 178 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 179 * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. 180 * |[1] |TXRST |Transmit Reset 181 * | | |0 = No effect. 182 * | | |1 = Reset transmit FIFO pointer and transmit circuit 183 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 184 * | | |This bit will be cleared to 0 by hardware about 3 system clock cycles + 2 peripheral clock cycles after it is set to 1 185 * | | |User can read TXRXRST (SPIx_STATUS[23]) to check if reset is accomplished or not. 186 * | | |Note: If TX underflow event occurs in SPI Slave mode, this bit can be used to make SPI return to idle state. 187 * |[2] |RXTHIEN |Receive FIFO Threshold Interrupt Enable Bit 188 * | | |0 = RX FIFO threshold interrupt Disabled. 189 * | | |1 = RX FIFO threshold interrupt Enabled. 190 * |[3] |TXTHIEN |Transmit FIFO Threshold Interrupt Enable Bit 191 * | | |0 = TX FIFO threshold interrupt Disabled. 192 * | | |1 = TX FIFO threshold interrupt Enabled. 193 * |[4] |RXTOIEN |Receive Time-out Interrupt Enable Bit 194 * | | |0 = Receive time-out interrupt Disabled. 195 * | | |1 = Receive time-out interrupt Enabled. 196 * |[5] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit 197 * | | |0 = Receive FIFO overrun interrupt Disabled. 198 * | | |1 = Receive FIFO overrun interrupt Enabled. 199 * |[6] |TXUFPOL |TX Underflow Data Polarity 200 * | | |0 = The SPI data out is keep 0 if there is TX underflow event in Slave mode. 201 * | | |1 = The SPI data out is keep 1 if there is TX underflow event in Slave mode. 202 * | | |Note: 203 * | | |1. The TX underflow event occurs if there is no any data in TX FIFO when the slave selection signal is active. 204 * | | |2. This bit should be set as 0 in I2S mode. 205 * | | |3. When TX underflow event occurs, SPIx_MISO pin state will be determined by this setting even though TX FIFO is not empty afterward 206 * | | |Data stored in TX FIFO will be sent through SPIx_MISO pin in the next transfer frame. 207 * |[7] |TXUFIEN |TX Underflow Interrupt Enable Bit 208 * | | |When TX underflow event occurs in Slave mode, TXUFIF (SPIx_STATUS[19]) will be set to 1 209 * | | |This bit is used to enable the TX underflow interrupt. 210 * | | |0 = Slave TX underflow interrupt Disabled. 211 * | | |1 = Slave TX underflow interrupt Enabled. 212 * |[8] |RXFBCLR |Receive FIFO Buffer Clear 213 * | | |0 = No effect. 214 * | | |1 = Clear receive FIFO pointer 215 * | | |The RXFULL bit will be cleared to 0 and the RXEMPTY bit will be set to 1 216 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 217 * | | |Note: The RX shift register will not be cleared. 218 * |[9] |TXFBCLR |Transmit FIFO Buffer Clear 219 * | | |0 = No effect. 220 * | | |1 = Clear transmit FIFO pointer 221 * | | |The TXFULL bit will be cleared to 0 and the TXEMPTY bit will be set to 1 222 * | | |This bit will be cleared to 0 by hardware about 1 system clock after it is set to 1. 223 * | | |Note: The TX shift register will not be cleared. 224 * |[10] |SLVBERX |RX FIFO Write Data Enable Bit When Slave Mode Bit Count Error 225 * | | |0 = Uncompleted RX data will be dropped from RX FIFO when bit count error event happened in SPI Slave mode. 226 * | | |1 = Uncompleted RX data will be written into RX FIFO when bit count error event happened in SPI Slave mode 227 * | | |User can read SLVBENUM (SPIx_STATUS2[29:24]) to know that the effective bit number of uncompleted RX data when SPI slave bit count error happened. 228 * | | |Note: Slave mode only. 229 * |[26:24] |RXTH |Receive FIFO Threshold 230 * | | |If the valid data count of the receive FIFO buffer is larger than the RXTH setting, the RXTHIF bit will be set to 1, else the RXTHIF bit will be cleared to 0 231 * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 232 * |[30:28] |TXTH |Transmit FIFO Threshold 233 * | | |If the valid data count of the transmit FIFO buffer is less than or equal to the TXTH setting, the TXTHIF bit will be set to 1, else the TXTHIF bit will be cleared to 0 234 * | | |For SPI0~SPI3, the MSB of this bit field is only meaningful while SPI mode 8~16 bits of data length. 235 * @var SPI_T::STATUS 236 * Offset: 0x14 SPI Status Register 237 * --------------------------------------------------------------------------------------------------- 238 * |Bits |Field |Descriptions 239 * | :----: | :----: | :---- | 240 * |[0] |BUSY |Busy Status (Read Only) 241 * | | |0 = SPI controller is in idle state. 242 * | | |1 = SPI controller is in busy state. 243 * | | |The following listing are the bus busy conditions: 244 * | | |a. SPIx_CTL[0] = 1 and TXEMPTY = 0. 245 * | | |b 246 * | | |For SPI Master mode, SPIx_CTL[0] = 1 and TXEMPTY = 1 but the current transaction is not finished yet. 247 * | | |c. For SPI Master mode, SPIx_CTL[0] = 1 and RXONLY = 1. 248 * | | |d. 249 * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and there is serial clock input into the SPI core logic when slave select is active. 250 * | | |e. 251 * | | |For SPI Slave mode, the SPIx_CTL[0] = 1 and the transmit buffer or transmit shift register is not empty even if the slave select is inactive. 252 * | | |Note: By applications, this SPI busy flag should be used with other status registers in SPIx_STATUS such as TXCNT, RXCNT, TXTHIF, TXFULL, TXEMPTY, RXTHIF, RXFULL, RXEMPTY, and UNITIF 253 * | | |Therefore the SPI transfer done events of TX/RX operations can be obtained at correct timing point. 254 * |[1] |UNITIF |Unit Transfer Interrupt Flag 255 * | | |0 = No transaction has been finished since this bit was cleared to 0. 256 * | | |1 = SPI controller has finished one unit transfer. 257 * | | |Note: This bit will be cleared by writing 1 to it. 258 * |[2] |SSACTIF |Slave Select Active Interrupt Flag 259 * | | |0 = Slave select active interrupt was cleared or not occurred. 260 * | | |1 = Slave select active interrupt event occurred. 261 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 262 * |[3] |SSINAIF |Slave Select Inactive Interrupt Flag 263 * | | |0 = Slave select inactive interrupt was cleared or not occurred. 264 * | | |1 = Slave select inactive interrupt event occurred. 265 * | | |Note: Only available in Slave mode. This bit will be cleared by writing 1 to it. 266 * |[4] |SSLINE |Slave Select Line Bus Status (Read Only) 267 * | | |0 = The slave select line status is 0. 268 * | | |1 = The slave select line status is 1. 269 * | | |Note: This bit is only available in Slave mode 270 * | | |If SSACTPOL (SPIx_SSCTL[2]) is set 0, and the SSLINE is 1, the SPI slave select is in inactive status. 271 * |[6] |SLVBEIF |Slave Mode Bit Count Error Interrupt Flag 272 * | | |In Slave mode, when the slave select line goes to inactive state, if bit counter is mismatch with DWIDTH, this interrupt flag will be set to 1. 273 * | | |0 = No Slave mode bit count error event. 274 * | | |1 = Slave mode bit count error event occurs. 275 * | | |Note: If the slave select active but there is no any bus clock input, the SLVBEIF also active when the slave select goes to inactive state 276 * | | |This bit will be cleared by writing 1 to it. 277 * |[7] |SLVURIF |Slave Mode TX Under Run Interrupt Flag 278 * | | |In Slave mode, if TX underflow event occurs and the slave select line goes to inactive state, this interrupt flag will be set to 1. 279 * | | |0 = No Slave TX under run event. 280 * | | |1 = Slave TX under run event occurs. 281 * | | |Note: This bit will be cleared by writing 1 to it. 282 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 283 * | | |0 = Receive FIFO buffer is not empty. 284 * | | |1 = Receive FIFO buffer is empty. 285 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 286 * | | |0 = Receive FIFO buffer is not full. 287 * | | |1 = Receive FIFO buffer is full. 288 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 289 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 290 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 291 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 292 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 293 * | | |0 = No FIFO is overrun. 294 * | | |1 = Receive FIFO is overrun. 295 * | | |Note: This bit will be cleared by writing 1 to it. 296 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 297 * | | |0 = No receive FIFO time-out event. 298 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock periods in Master mode or over 576 SPI peripheral clock periods in Slave mode 299 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 300 * | | |Note: This bit will be cleared by writing 1 to it. 301 * |[15] |SPIENSTS |SPI Enable Status (Read Only) 302 * | | |0 = The SPI controller is disabled. 303 * | | |1 = The SPI controller is enabled. 304 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 305 * | | |In order to make sure the SPI control logic is disabled, this bit indicates the real status of SPI controller. 306 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 307 * | | |0 = Transmit FIFO buffer is not empty. 308 * | | |1 = Transmit FIFO buffer is empty. 309 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 310 * | | |0 = Transmit FIFO buffer is not full. 311 * | | |1 = Transmit FIFO buffer is full. 312 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 313 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 314 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 315 * |[19] |TXUFIF |TX Underflow Interrupt Flag 316 * | | |When the TX underflow event occurs, this bit will be set to 1, the state of data output pin depends on the setting of TXUFPOL. 317 * | | |0 = No effect. 318 * | | |1 = No data in Transmit FIFO and TX shift register when the slave selection signal is active. 319 * | | |Note 1: This bit will be cleared by writing 1 to it. 320 * | | |Note 2: If reset slave's transmission circuit when slave selection signal is active, this flag will be set to 1 after 2 peripheral clock cycles + 3 system clock cycles since the reset operation is done. 321 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 322 * | | |0 = The reset function of TXRST or RXRST is done. 323 * | | |1 = Doing the reset function of TXRST or RXRST. 324 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 325 * | | |User can check the status of this bit to monitor the reset function is doing or done. 326 * |[27:24] |RXCNT |Receive FIFO Data Count (Read Only) 327 * | | |This bit field indicates the valid data count of receive FIFO buffer. 328 * |[31:28] |TXCNT |Transmit FIFO Data Count (Read Only) 329 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 330 * @var SPI_T::STATUS2 331 * Offset: 0x18 SPI Status2 Register 332 * --------------------------------------------------------------------------------------------------- 333 * |Bits |Field |Descriptions 334 * | :----: | :----: | :---- | 335 * |[29:24] |SLVBENUM |Effective Bit Number of Uncompleted RX Data 336 * | | |This status register indicates that effective bit number of uncompleted RX data when SLVBERX (SPIx_FIFOCTL[10]) is enabled and RX bit count error event happen in SPI Slave mode 337 * | | |This status register will be fixed to 0x0 when SLVBERX (SPIx_FIFOCTL[10]) is disabled. 338 * | | |Note 1: This register will be cleared to 0x0 when user writes 0x1 to SLVBEIF (SPIx_STATUS[6]). 339 * | | |Note 2: Slave mode only. 340 * @var SPI_T::TX 341 * Offset: 0x20 SPI Data Transmit Register 342 * --------------------------------------------------------------------------------------------------- 343 * |Bits |Field |Descriptions 344 * | :----: | :----: | :---- | 345 * |[31:0] |TX |Data Transmit Register 346 * | | |The data transmit registers pass through the transmitted data into the 4-level transmit FIFO buffers 347 * | | |The number of valid bits depends on the setting of DWIDTH (SPIx_CTL[12:8]) in SPI mode or WDWIDTH (SPIx_I2SCTL[5:4]) in I2S mode. 348 * | | |In SPI mode, if DWIDTH is set to 0x08, the bits TX[7:0] will be transmitted 349 * | | |If DWIDTH is set to 0x00 , the SPI controller will perform a 32-bit transfer. 350 * | | |In I2S mode, if WDWIDTH (SPIx_I2SCTL[5:4]) is set to 0x2, the data width of audio channel is 24-bit and corresponding to TX[23:0] 351 * | | |If WDWIDTH is set as 0x0, 0x1, or 0x3, all bits of this field are valid and referred to the data arrangement in I2S mode FIFO operation section 352 * | | |Note: In Master mode, SPI controller will start to transfer the SPI bus clock after 1 APB clock and 6 peripheral clock cycles after user writes to this register. 353 * @var SPI_T::RX 354 * Offset: 0x30 SPI Data Receive Register 355 * --------------------------------------------------------------------------------------------------- 356 * |Bits |Field |Descriptions 357 * | :----: | :----: | :---- | 358 * |[31:0] |RX |Data Receive Register (Read Only) 359 * | | |There are 4-level FIFO buffers in this controller. 360 * | | |The data receive register holds the data received from SPI data input pin. 361 * | | |If the RXEMPTY (SPIx_STATUS[8] or SPIx_I2SSTS[8]) is not set to 1, the receive FIFO buffers can be accessed through software by reading this register. 362 * @var SPI_T::I2SCTL 363 * Offset: 0x60 I2S Control Register 364 * --------------------------------------------------------------------------------------------------- 365 * |Bits |Field |Descriptions 366 * | :----: | :----: | :---- | 367 * |[0] |I2SEN |I2S Controller Enable Bit 368 * | | |0 = Disabled I2S mode. 369 * | | |1 = Enabled I2S mode. 370 * | | |Note: 371 * | | |1. If enable this bit, I2Sx_BCLK will start to output in Master mode. 372 * | | |2 373 * | | |Before changing the configurations of SPIx_I2SCTL, SPIx_I2SCLK, and SPIx_FIFOCTL registers, user shall clear the I2SEN (SPIx_I2SCTL[0]) and confirm the I2SENSTS (SPIx_I2SSTS[15]) is 0. 374 * |[1] |TXEN |Transmit Enable Bit 375 * | | |0 = Data transmit Disabled. 376 * | | |1 = Data transmit Enabled. 377 * |[2] |RXEN |Receive Enable Bit 378 * | | |0 = Data receive Disabled. 379 * | | |1 = Data receive Enabled. 380 * |[3] |MUTE |Transmit Mute Enable Bit 381 * | | |0 = Transmit data is shifted from buffer. 382 * | | |1 = Transmit channel zero. 383 * |[5:4] |WDWIDTH |Word Width 384 * | | |00 = data size is 8-bit. 385 * | | |01 = data size is 16-bit. 386 * | | |10 = data size is 24-bit. 387 * | | |11 = data size is 32-bit. 388 * |[6] |MONO |Monaural Data 389 * | | |0 = Data is stereo format. 390 * | | |1 = Data is monaural format. 391 * |[7] |ORDER |Stereo Data Order in FIFO 392 * | | |0 = Left channel data at high byte. 393 * | | |1 = Left channel data at low byte. 394 * |[8] |SLAVE |Slave Mode 395 * | | |I2S can operate as master or slave 396 * | | |For Master mode, I2Sx_BCLK and I2Sx_LRCLK pins are output mode and send bit clock from NuMicro M2354 series to audio CODEC chip 397 * | | |In Slave mode, I2Sx_BCLK and I2Sx_LRCLK pins are input mode and I2Sx_BCLK and I2Sx_LRCLK signals are received from outer audio CODEC chip. 398 * | | |0 = Master mode. 399 * | | |1 = Slave mode. 400 * |[15] |MCLKEN |Master Clock Enable Bit 401 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on SPIx_I2SMCLK pin for external audio devices. 402 * | | |0 = Master clock Disabled. 403 * | | |1 = Master clock Enabled. 404 * |[16] |RZCEN |Right Channel Zero Cross Detection Enable Bit 405 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCIF flag in SPIx_I2SSTS register is set to 1 406 * | | |This function is only available in transmit operation. 407 * | | |0 = Right channel zero cross detection Disabled. 408 * | | |1 = Right channel zero cross detection Enabled. 409 * |[17] |LZCEN |Left Channel Zero Cross Detection Enable Bit 410 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCIF flag in SPIx_I2SSTS register is set to 1 411 * | | |This function is only available in transmit operation. 412 * | | |0 = Left channel zero cross detection Disabled. 413 * | | |1 = Left channel zero cross detection Enabled. 414 * |[23] |RXLCH |Receive Left Channel Enable Bit 415 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0, and receive left channel data if RXLCH is set to 1. 416 * | | |0 = Receive right channel data in Mono mode. 417 * | | |1 = Receive left channel data in Mono mode. 418 * |[24] |RZCIEN |Right Channel Zero Cross Interrupt Enable Bit 419 * | | |Interrupt occurs if this bit is set to 1 and right channel zero cross event occurs. 420 * | | |0 = Interrupt Disabled. 421 * | | |1 = Interrupt Enabled. 422 * |[25] |LZCIEN |Left Channel Zero Cross Interrupt Enable Bit 423 * | | |Interrupt occurs if this bit is set to 1 and left channel zero cross event occurs. 424 * | | |0 = Interrupt Disabled. 425 * | | |1 = Interrupt Enabled. 426 * |[29:28] |FORMAT |Data Format Selection 427 * | | |00 = I2S data format. 428 * | | |01 = MSB justified data format. 429 * | | |10 = PCM mode A. 430 * | | |11 = PCM mode B. 431 * |[31] |SLVERRIEN |Bit Clock Loss Interrupt Enable Bit for Slave Mode 432 * | | |Interrupt occurs if this bit is set to 1 and bit clock loss event occurs. 433 * | | |0 = Interrupt Disabled. 434 * | | |1 = Interrupt Enabled. 435 * @var SPI_T::I2SCLK 436 * Offset: 0x64 I2S Clock Divider Control Register 437 * --------------------------------------------------------------------------------------------------- 438 * |Bits |Field |Descriptions 439 * | :----: | :----: | :---- | 440 * |[6:0] |MCLKDIV |Master Clock Divider 441 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices. 442 * | | |The frequency of master clock, F_MCLK, is determined by the following expressions: 443 * | | |If MCLKDIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLKDIV)). 444 * | | |If MCLKDIV = 0, F_MCLK = F_I2SCLK. 445 * | | |where 446 * | | |is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. 447 * | | |F_I2SCLK is the frequency of I2S peripheral clock. 448 * | | |In general, the master clock rate is 256 times sampling clock rate. 449 * |[17:8] |BCLKDIV |Bit Clock Divider 450 * | | |The I2S controller will generate bit clock in Master mode. 451 * | | |The clock frequency of bit clock, F_BCLK, is determined by the following expression: 452 * | | |F_BCLK = F_I2SCLK/(2x(BCLKDIV + 1)), 453 * | | |where 454 * | | |F_I2SCLK is the frequency of I2S peripheral clock source, which is defined in the clock control register CLK_CLKSEL2. 455 * | | |In I2S Slave mode, this field is used to define the frequency of peripheral clock and it's determined by F_I2SCLK/(BCLKDIV/2 + 1). 456 * | | |The peripheral clock frequency in I2S Slave mode must be equal to or faster than 6 times of input bit clock. 457 * |[24] |I2SMODE |I2S Clock Divider Number Selection for I2S Mode and SPI Mode 458 * | | |User sets I2SMODE to set frequency of peripheral clock of I2S mode or SPI mode when BCLKDIV (SPIx_I2SCLK[17:8]) or DIVIDER (SPIx_CLKDIV[8:0]) is set. 459 * | | |User needs to set I2SMODE before I2SEN (SPIx_I2SCTL[0]) or SPIEN (SPIx_CTL[0]) is enabled. 460 * | | |0 = The frequency of peripheral clock is set to SPI mode. 461 * | | |1 = The frequency of peripheral clock is set to I2S mode. 462 * |[25] |I2SSLAVE |I2S Clock Divider Number Selection for I2S Slave Mode and I2S Master Mode 463 * | | |User sets I2SSLAVE to set frequency of peripheral clock of I2S master mode and I2S slave mode when BCLKDIV (SPIx_I2SCLK[17:8]) is set. 464 * | | |I2SSLAVE needs to set before I2SEN (SPIx_I2SCTL[0]) is enabled. 465 * | | |0 = The frequency of peripheral clock is set to I2S Master mode. 466 * | | |1 = The frequency of peripheral clock is set to I2S Slave mode. 467 * @var SPI_T::I2SSTS 468 * Offset: 0x68 I2S Status Register 469 * --------------------------------------------------------------------------------------------------- 470 * |Bits |Field |Descriptions 471 * | :----: | :----: | :---- | 472 * |[4] |RIGHT |Right Channel (Read Only) 473 * | | |This bit indicates the current transmit data is belong to which channel. 474 * | | |0 = Left channel. 475 * | | |1 = Right channel. 476 * |[8] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only) 477 * | | |0 = Receive FIFO buffer is not empty. 478 * | | |1 = Receive FIFO buffer is empty. 479 * |[9] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only) 480 * | | |0 = Receive FIFO buffer is not full. 481 * | | |1 = Receive FIFO buffer is full. 482 * |[10] |RXTHIF |Receive FIFO Threshold Interrupt Flag (Read Only) 483 * | | |0 = The valid data count within the receive FIFO buffer is smaller than or equal to the setting value of RXTH. 484 * | | |1 = The valid data count within the receive FIFO buffer is larger than the setting value of RXTH. 485 * | | |Note: If RXTHIEN = 1 and RXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. 486 * |[11] |RXOVIF |Receive FIFO Overrun Interrupt Flag 487 * | | |When the receive FIFO buffer is full, the follow-up data will be dropped and this bit will be set to 1. 488 * | | |Note: This bit will be cleared by writing 1 to it. 489 * |[12] |RXTOIF |Receive Time-out Interrupt Flag 490 * | | |0 = No receive FIFO time-out event. 491 * | | |1 = Receive FIFO buffer is not empty and no read operation on receive FIFO buffer over 64 SPI peripheral clock period in Master mode or over 576 SPI peripheral clock period in Slave mode 492 * | | |When the received FIFO buffer is read by software, the time-out status will be cleared automatically. 493 * | | |Note: This bit will be cleared by writing 1 to it. 494 * |[15] |I2SENSTS |I2S Enable Status (Read Only) 495 * | | |0 = The SPI/I2S control logic is disabled. 496 * | | |1 = The SPI/I2S control logic is enabled. 497 * | | |Note: The SPI peripheral clock is asynchronous with the system clock 498 * | | |In order to make sure the SPI/I2S control logic is disabled, this bit indicates the real status of SPI/I2S control logic for user. 499 * |[16] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only) 500 * | | |0 = Transmit FIFO buffer is not empty. 501 * | | |1 = Transmit FIFO buffer is empty. 502 * |[17] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only) 503 * | | |0 = Transmit FIFO buffer is not full. 504 * | | |1 = Transmit FIFO buffer is full. 505 * |[18] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only) 506 * | | |0 = The valid data count within the transmit FIFO buffer is larger than the setting value of TXTH. 507 * | | |1 = The valid data count within the transmit FIFO buffer is less than or equal to the setting value of TXTH. 508 * | | |Note: If TXTHIEN = 1 and TXTHIF = 1, the SPI/I2S controller will generate a SPI interrupt request. 509 * |[19] |TXUFIF |Transmit FIFO Underflow Interrupt Flag 510 * | | |When the transmit FIFO buffer is empty and there is no datum written into the FIFO buffer, if there is more bus clock input, this bit will be set to 1. 511 * | | |Note: This bit will be cleared by writing 1 to it. 512 * |[20] |RZCIF |Right Channel Zero Cross Interrupt Flag 513 * | | |0 = No zero cross event occurred on right channel. 514 * | | |1 = Zero cross event occurred on right channel. 515 * |[21] |LZCIF |Left Channel Zero Cross Interrupt Flag 516 * | | |0 = No zero cross event occurred on left channel. 517 * | | |1 = Zero cross event occurred on left channel. 518 * |[22] |SLVERRIF |Bit Clock Loss Interrupt Flag for Slave Mode 519 * | | |0 = No bit clock loss event occurred. 520 * | | |1 = Bit clock loss event occurred. 521 * | | |Note: This bit will be cleared by writing 1 to it. 522 * |[23] |TXRXRST |TX or RX Reset Status (Read Only) 523 * | | |0 = The reset function of TXRST or RXRST is done. 524 * | | |1 = Doing the reset function of TXRST or RXRST. 525 * | | |Note: Both the reset operations of TXRST and RXRST need 3 system clock cycles + 2 peripheral clock cycles 526 * | | |User can check the status of this bit to monitor the reset function is doing or done. 527 * |[26:24] |RXCNT |Receive FIFO Data Count (Read Only) 528 * | | |This bit field indicates the valid data count of receive FIFO buffer. 529 * |[30:28] |TXCNT |Transmit FIFO Data Count (Read Only) 530 * | | |This bit field indicates the valid data count of transmit FIFO buffer. 531 */ 532 __IO uint32_t CTL; /*!< [0x0000] SPI Control Register */ 533 __IO uint32_t CLKDIV; /*!< [0x0004] SPI Clock Divider Register */ 534 __IO uint32_t SSCTL; /*!< [0x0008] SPI Slave Select Control Register */ 535 __IO uint32_t PDMACTL; /*!< [0x000c] SPI PDMA Control Register */ 536 __IO uint32_t FIFOCTL; /*!< [0x0010] SPI FIFO Control Register */ 537 __IO uint32_t STATUS; /*!< [0x0014] SPI Status Register */ 538 __I uint32_t STATUS2; /*!< [0x0018] SPI Status2 Register */ 539 __I uint32_t RESERVE0[1]; 540 __O uint32_t TX; /*!< [0x0020] SPI Data Transmit Register */ 541 __I uint32_t RESERVE1[3]; 542 __I uint32_t RX; /*!< [0x0030] SPI Data Receive Register */ 543 __I uint32_t RESERVE2[11]; 544 __IO uint32_t I2SCTL; /*!< [0x0060] I2S Control Register */ 545 __IO uint32_t I2SCLK; /*!< [0x0064] I2S Clock Divider Control Register */ 546 __IO uint32_t I2SSTS; /*!< [0x0068] I2S Status Register */ 547 548 } SPI_T; 549 550 /** 551 @addtogroup SPI_CONST SPI Bit Field Definition 552 Constant Definitions for SPI Controller 553 @{ 554 */ 555 556 #define SPI_CTL_SPIEN_Pos (0) /*!< SPI_T::CTL: SPIEN Position */ 557 #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) /*!< SPI_T::CTL: SPIEN Mask */ 558 559 #define SPI_CTL_RXNEG_Pos (1) /*!< SPI_T::CTL: RXNEG Position */ 560 #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) /*!< SPI_T::CTL: RXNEG Mask */ 561 562 #define SPI_CTL_TXNEG_Pos (2) /*!< SPI_T::CTL: TXNEG Position */ 563 #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) /*!< SPI_T::CTL: TXNEG Mask */ 564 565 #define SPI_CTL_CLKPOL_Pos (3) /*!< SPI_T::CTL: CLKPOL Position */ 566 #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) /*!< SPI_T::CTL: CLKPOL Mask */ 567 568 #define SPI_CTL_SUSPITV_Pos (4) /*!< SPI_T::CTL: SUSPITV Position */ 569 #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) /*!< SPI_T::CTL: SUSPITV Mask */ 570 571 #define SPI_CTL_DWIDTH_Pos (8) /*!< SPI_T::CTL: DWIDTH Position */ 572 #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) /*!< SPI_T::CTL: DWIDTH Mask */ 573 574 #define SPI_CTL_LSB_Pos (13) /*!< SPI_T::CTL: LSB Position */ 575 #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) /*!< SPI_T::CTL: LSB Mask */ 576 577 #define SPI_CTL_HALFDPX_Pos (14) /*!< SPI_T::CTL: HALFDPX Position */ 578 #define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) /*!< SPI_T::CTL: HALFDPX Mask */ 579 580 #define SPI_CTL_RXONLY_Pos (15) /*!< SPI_T::CTL: RXONLY Position */ 581 #define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) /*!< SPI_T::CTL: RXONLY Mask */ 582 583 #define SPI_CTL_UNITIEN_Pos (17) /*!< SPI_T::CTL: UNITIEN Position */ 584 #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) /*!< SPI_T::CTL: UNITIEN Mask */ 585 586 #define SPI_CTL_SLAVE_Pos (18) /*!< SPI_T::CTL: SLAVE Position */ 587 #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) /*!< SPI_T::CTL: SLAVE Mask */ 588 589 #define SPI_CTL_REORDER_Pos (19) /*!< SPI_T::CTL: REORDER Position */ 590 #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) /*!< SPI_T::CTL: REORDER Mask */ 591 592 #define SPI_CTL_DATDIR_Pos (20) /*!< SPI_T::CTL: DATDIR Position */ 593 #define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) /*!< SPI_T::CTL: DATDIR Mask */ 594 595 #define SPI_CLKDIV_DIVIDER_Pos (0) /*!< SPI_T::CLKDIV: DIVIDER Position */ 596 #define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) /*!< SPI_T::CLKDIV: DIVIDER Mask */ 597 598 #define SPI_SSCTL_SS_Pos (0) /*!< SPI_T::SSCTL: SS Position */ 599 #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) /*!< SPI_T::SSCTL: SS Mask */ 600 601 #define SPI_SSCTL_SSACTPOL_Pos (2) /*!< SPI_T::SSCTL: SSACTPOL Position */ 602 #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) /*!< SPI_T::SSCTL: SSACTPOL Mask */ 603 604 #define SPI_SSCTL_AUTOSS_Pos (3) /*!< SPI_T::SSCTL: AUTOSS Position */ 605 #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) /*!< SPI_T::SSCTL: AUTOSS Mask */ 606 607 #define SPI_SSCTL_SLV3WIRE_Pos (4) /*!< SPI_T::SSCTL: SLV3WIRE Position */ 608 #define SPI_SSCTL_SLV3WIRE_Msk (0x1ul << SPI_SSCTL_SLV3WIRE_Pos) /*!< SPI_T::SSCTL: SLV3WIRE Mask */ 609 610 #define SPI_SSCTL_SLVBEIEN_Pos (8) /*!< SPI_T::SSCTL: SLVBEIEN Position */ 611 #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) /*!< SPI_T::SSCTL: SLVBEIEN Mask */ 612 613 #define SPI_SSCTL_SLVURIEN_Pos (9) /*!< SPI_T::SSCTL: SLVURIEN Position */ 614 #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) /*!< SPI_T::SSCTL: SLVURIEN Mask */ 615 616 #define SPI_SSCTL_SSACTIEN_Pos (12) /*!< SPI_T::SSCTL: SSACTIEN Position */ 617 #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) /*!< SPI_T::SSCTL: SSACTIEN Mask */ 618 619 #define SPI_SSCTL_SSINAIEN_Pos (13) /*!< SPI_T::SSCTL: SSINAIEN Position */ 620 #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) /*!< SPI_T::SSCTL: SSINAIEN Mask */ 621 622 #define SPI_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI_T::PDMACTL: TXPDMAEN Position */ 623 #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) /*!< SPI_T::PDMACTL: TXPDMAEN Mask */ 624 625 #define SPI_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI_T::PDMACTL: RXPDMAEN Position */ 626 #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) /*!< SPI_T::PDMACTL: RXPDMAEN Mask */ 627 628 #define SPI_PDMACTL_PDMARST_Pos (2) /*!< SPI_T::PDMACTL: PDMARST Position */ 629 #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) /*!< SPI_T::PDMACTL: PDMARST Mask */ 630 631 #define SPI_FIFOCTL_RXRST_Pos (0) /*!< SPI_T::FIFOCTL: RXRST Position */ 632 #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) /*!< SPI_T::FIFOCTL: RXRST Mask */ 633 634 #define SPI_FIFOCTL_TXRST_Pos (1) /*!< SPI_T::FIFOCTL: TXRST Position */ 635 #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) /*!< SPI_T::FIFOCTL: TXRST Mask */ 636 637 #define SPI_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI_T::FIFOCTL: RXTHIEN Position */ 638 #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) /*!< SPI_T::FIFOCTL: RXTHIEN Mask */ 639 640 #define SPI_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI_T::FIFOCTL: TXTHIEN Position */ 641 #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) /*!< SPI_T::FIFOCTL: TXTHIEN Mask */ 642 643 #define SPI_FIFOCTL_RXTOIEN_Pos (4) /*!< SPI_T::FIFOCTL: RXTOIEN Position */ 644 #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) /*!< SPI_T::FIFOCTL: RXTOIEN Mask */ 645 646 #define SPI_FIFOCTL_RXOVIEN_Pos (5) /*!< SPI_T::FIFOCTL: RXOVIEN Position */ 647 #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) /*!< SPI_T::FIFOCTL: RXOVIEN Mask */ 648 649 #define SPI_FIFOCTL_TXUFPOL_Pos (6) /*!< SPI_T::FIFOCTL: TXUFPOL Position */ 650 #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) /*!< SPI_T::FIFOCTL: TXUFPOL Mask */ 651 652 #define SPI_FIFOCTL_TXUFIEN_Pos (7) /*!< SPI_T::FIFOCTL: TXUFIEN Position */ 653 #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) /*!< SPI_T::FIFOCTL: TXUFIEN Mask */ 654 655 #define SPI_FIFOCTL_RXFBCLR_Pos (8) /*!< SPI_T::FIFOCTL: RXFBCLR Position */ 656 #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) /*!< SPI_T::FIFOCTL: RXFBCLR Mask */ 657 658 #define SPI_FIFOCTL_TXFBCLR_Pos (9) /*!< SPI_T::FIFOCTL: TXFBCLR Position */ 659 #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) /*!< SPI_T::FIFOCTL: TXFBCLR Mask */ 660 661 #define SPI_FIFOCTL_SLVBERX_Pos (10) /*!< SPI_T::FIFOCTL: SLVBERX Position */ 662 #define SPI_FIFOCTL_SLVBERX_Msk (0x1ul << SPI_FIFOCTL_SLVBERX_Pos) /*!< SPI_T::FIFOCTL: SLVBERX Mask */ 663 664 #define SPI_FIFOCTL_RXTH_Pos (24) /*!< SPI_T::FIFOCTL: RXTH Position */ 665 #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) /*!< SPI_T::FIFOCTL: RXTH Mask */ 666 667 #define SPI_FIFOCTL_TXTH_Pos (28) /*!< SPI_T::FIFOCTL: TXTH Position */ 668 #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) /*!< SPI_T::FIFOCTL: TXTH Mask */ 669 670 #define SPI_STATUS_BUSY_Pos (0) /*!< SPI_T::STATUS: BUSY Position */ 671 #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) /*!< SPI_T::STATUS: BUSY Mask */ 672 673 #define SPI_STATUS_UNITIF_Pos (1) /*!< SPI_T::STATUS: UNITIF Position */ 674 #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) /*!< SPI_T::STATUS: UNITIF Mask */ 675 676 #define SPI_STATUS_SSACTIF_Pos (2) /*!< SPI_T::STATUS: SSACTIF Position */ 677 #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) /*!< SPI_T::STATUS: SSACTIF Mask */ 678 679 #define SPI_STATUS_SSINAIF_Pos (3) /*!< SPI_T::STATUS: SSINAIF Position */ 680 #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) /*!< SPI_T::STATUS: SSINAIF Mask */ 681 682 #define SPI_STATUS_SSLINE_Pos (4) /*!< SPI_T::STATUS: SSLINE Position */ 683 #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) /*!< SPI_T::STATUS: SSLINE Mask */ 684 685 #define SPI_STATUS_SLVBEIF_Pos (6) /*!< SPI_T::STATUS: SLVBEIF Position */ 686 #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) /*!< SPI_T::STATUS: SLVBEIF Mask */ 687 688 #define SPI_STATUS_SLVURIF_Pos (7) /*!< SPI_T::STATUS: SLVURIF Position */ 689 #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) /*!< SPI_T::STATUS: SLVURIF Mask */ 690 691 #define SPI_STATUS_RXEMPTY_Pos (8) /*!< SPI_T::STATUS: RXEMPTY Position */ 692 #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) /*!< SPI_T::STATUS: RXEMPTY Mask */ 693 694 #define SPI_STATUS_RXFULL_Pos (9) /*!< SPI_T::STATUS: RXFULL Position */ 695 #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) /*!< SPI_T::STATUS: RXFULL Mask */ 696 697 #define SPI_STATUS_RXTHIF_Pos (10) /*!< SPI_T::STATUS: RXTHIF Position */ 698 #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) /*!< SPI_T::STATUS: RXTHIF Mask */ 699 700 #define SPI_STATUS_RXOVIF_Pos (11) /*!< SPI_T::STATUS: RXOVIF Position */ 701 #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) /*!< SPI_T::STATUS: RXOVIF Mask */ 702 703 #define SPI_STATUS_RXTOIF_Pos (12) /*!< SPI_T::STATUS: RXTOIF Position */ 704 #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) /*!< SPI_T::STATUS: RXTOIF Mask */ 705 706 #define SPI_STATUS_SPIENSTS_Pos (15) /*!< SPI_T::STATUS: SPIENSTS Position */ 707 #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) /*!< SPI_T::STATUS: SPIENSTS Mask */ 708 709 #define SPI_STATUS_TXEMPTY_Pos (16) /*!< SPI_T::STATUS: TXEMPTY Position */ 710 #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) /*!< SPI_T::STATUS: TXEMPTY Mask */ 711 712 #define SPI_STATUS_TXFULL_Pos (17) /*!< SPI_T::STATUS: TXFULL Position */ 713 #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) /*!< SPI_T::STATUS: TXFULL Mask */ 714 715 #define SPI_STATUS_TXTHIF_Pos (18) /*!< SPI_T::STATUS: TXTHIF Position */ 716 #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) /*!< SPI_T::STATUS: TXTHIF Mask */ 717 718 #define SPI_STATUS_TXUFIF_Pos (19) /*!< SPI_T::STATUS: TXUFIF Position */ 719 #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) /*!< SPI_T::STATUS: TXUFIF Mask */ 720 721 #define SPI_STATUS_TXRXRST_Pos (23) /*!< SPI_T::STATUS: TXRXRST Position */ 722 #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) /*!< SPI_T::STATUS: TXRXRST Mask */ 723 724 #define SPI_STATUS_RXCNT_Pos (24) /*!< SPI_T::STATUS: RXCNT Position */ 725 #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) /*!< SPI_T::STATUS: RXCNT Mask */ 726 727 #define SPI_STATUS_TXCNT_Pos (28) /*!< SPI_T::STATUS: TXCNT Position */ 728 #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) /*!< SPI_T::STATUS: TXCNT Mask */ 729 730 #define SPI_STATUS2_SLVBENUM_Pos (24) /*!< SPI_T::STATUS2: SLVBENUM Position */ 731 #define SPI_STATUS2_SLVBENUM_Msk (0x3ful << SPI_STATUS2_SLVBENUM_Pos) /*!< SPI_T::STATUS2: SLVBENUM Mask */ 732 733 #define SPI_TX_TX_Pos (0) /*!< SPI_T::TX: TX Position */ 734 #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) /*!< SPI_T::TX: TX Mask */ 735 736 #define SPI_RX_RX_Pos (0) /*!< SPI_T::RX: RX Position */ 737 #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) /*!< SPI_T::RX: RX Mask */ 738 739 #define SPI_I2SCTL_I2SEN_Pos (0) /*!< SPI_T::I2SCTL: I2SEN Position */ 740 #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) /*!< SPI_T::I2SCTL: I2SEN Mask */ 741 742 #define SPI_I2SCTL_TXEN_Pos (1) /*!< SPI_T::I2SCTL: TXEN Position */ 743 #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) /*!< SPI_T::I2SCTL: TXEN Mask */ 744 745 #define SPI_I2SCTL_RXEN_Pos (2) /*!< SPI_T::I2SCTL: RXEN Position */ 746 #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) /*!< SPI_T::I2SCTL: RXEN Mask */ 747 748 #define SPI_I2SCTL_MUTE_Pos (3) /*!< SPI_T::I2SCTL: MUTE Position */ 749 #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) /*!< SPI_T::I2SCTL: MUTE Mask */ 750 751 #define SPI_I2SCTL_WDWIDTH_Pos (4) /*!< SPI_T::I2SCTL: WDWIDTH Position */ 752 #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) /*!< SPI_T::I2SCTL: WDWIDTH Mask */ 753 754 #define SPI_I2SCTL_MONO_Pos (6) /*!< SPI_T::I2SCTL: MONO Position */ 755 #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) /*!< SPI_T::I2SCTL: MONO Mask */ 756 757 #define SPI_I2SCTL_ORDER_Pos (7) /*!< SPI_T::I2SCTL: ORDER Position */ 758 #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) /*!< SPI_T::I2SCTL: ORDER Mask */ 759 760 #define SPI_I2SCTL_SLAVE_Pos (8) /*!< SPI_T::I2SCTL: SLAVE Position */ 761 #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) /*!< SPI_T::I2SCTL: SLAVE Mask */ 762 763 #define SPI_I2SCTL_MCLKEN_Pos (15) /*!< SPI_T::I2SCTL: MCLKEN Position */ 764 #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) /*!< SPI_T::I2SCTL: MCLKEN Mask */ 765 766 #define SPI_I2SCTL_RZCEN_Pos (16) /*!< SPI_T::I2SCTL: RZCEN Position */ 767 #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) /*!< SPI_T::I2SCTL: RZCEN Mask */ 768 769 #define SPI_I2SCTL_LZCEN_Pos (17) /*!< SPI_T::I2SCTL: LZCEN Position */ 770 #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) /*!< SPI_T::I2SCTL: LZCEN Mask */ 771 772 #define SPI_I2SCTL_RXLCH_Pos (23) /*!< SPI_T::I2SCTL: RXLCH Position */ 773 #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) /*!< SPI_T::I2SCTL: RXLCH Mask */ 774 775 #define SPI_I2SCTL_RZCIEN_Pos (24) /*!< SPI_T::I2SCTL: RZCIEN Position */ 776 #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) /*!< SPI_T::I2SCTL: RZCIEN Mask */ 777 778 #define SPI_I2SCTL_LZCIEN_Pos (25) /*!< SPI_T::I2SCTL: LZCIEN Position */ 779 #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) /*!< SPI_T::I2SCTL: LZCIEN Mask */ 780 781 #define SPI_I2SCTL_FORMAT_Pos (28) /*!< SPI_T::I2SCTL: FORMAT Position */ 782 #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) /*!< SPI_T::I2SCTL: FORMAT Mask */ 783 784 #define SPI_I2SCTL_SLVERRIEN_Pos (31) /*!< SPI_T::I2SCTL: SLVERRIEN Position */ 785 #define SPI_I2SCTL_SLVERRIEN_Msk (0x1ul << SPI_I2SCTL_SLVERRIEN_Pos) /*!< SPI_T::I2SCTL: SLVERRIEN Mask */ 786 787 #define SPI_I2SCLK_MCLKDIV_Pos (0) /*!< SPI_T::I2SCLK: MCLKDIV Position */ 788 #define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) /*!< SPI_T::I2SCLK: MCLKDIV Mask */ 789 790 #define SPI_I2SCLK_BCLKDIV_Pos (8) /*!< SPI_T::I2SCLK: BCLKDIV Position */ 791 #define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) /*!< SPI_T::I2SCLK: BCLKDIV Mask */ 792 793 #define SPI_I2SCLK_I2SMODE_Pos (24) /*!< SPI_T::I2SCLK: I2SMODE Position */ 794 #define SPI_I2SCLK_I2SMODE_Msk (0x1ul << SPI_I2SCLK_I2SMODE_Pos) /*!< SPI_T::I2SCLK: I2SMODE Mask */ 795 796 #define SPI_I2SCLK_I2SSLAVE_Pos (25) /*!< SPI_T::I2SCLK: I2SSLAVE Position */ 797 #define SPI_I2SCLK_I2SSLAVE_Msk (0x1ul << SPI_I2SCLK_I2SSLAVE_Pos) /*!< SPI_T::I2SCLK: I2SSLAVE Mask */ 798 799 #define SPI_I2SSTS_RIGHT_Pos (4) /*!< SPI_T::I2SSTS: RIGHT Position */ 800 #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) /*!< SPI_T::I2SSTS: RIGHT Mask */ 801 802 #define SPI_I2SSTS_RXEMPTY_Pos (8) /*!< SPI_T::I2SSTS: RXEMPTY Position */ 803 #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) /*!< SPI_T::I2SSTS: RXEMPTY Mask */ 804 805 #define SPI_I2SSTS_RXFULL_Pos (9) /*!< SPI_T::I2SSTS: RXFULL Position */ 806 #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) /*!< SPI_T::I2SSTS: RXFULL Mask */ 807 808 #define SPI_I2SSTS_RXTHIF_Pos (10) /*!< SPI_T::I2SSTS: RXTHIF Position */ 809 #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) /*!< SPI_T::I2SSTS: RXTHIF Mask */ 810 811 #define SPI_I2SSTS_RXOVIF_Pos (11) /*!< SPI_T::I2SSTS: RXOVIF Position */ 812 #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) /*!< SPI_T::I2SSTS: RXOVIF Mask */ 813 814 #define SPI_I2SSTS_RXTOIF_Pos (12) /*!< SPI_T::I2SSTS: RXTOIF Position */ 815 #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) /*!< SPI_T::I2SSTS: RXTOIF Mask */ 816 817 #define SPI_I2SSTS_I2SENSTS_Pos (15) /*!< SPI_T::I2SSTS: I2SENSTS Position */ 818 #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) /*!< SPI_T::I2SSTS: I2SENSTS Mask */ 819 820 #define SPI_I2SSTS_TXEMPTY_Pos (16) /*!< SPI_T::I2SSTS: TXEMPTY Position */ 821 #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) /*!< SPI_T::I2SSTS: TXEMPTY Mask */ 822 823 #define SPI_I2SSTS_TXFULL_Pos (17) /*!< SPI_T::I2SSTS: TXFULL Position */ 824 #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) /*!< SPI_T::I2SSTS: TXFULL Mask */ 825 826 #define SPI_I2SSTS_TXTHIF_Pos (18) /*!< SPI_T::I2SSTS: TXTHIF Position */ 827 #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) /*!< SPI_T::I2SSTS: TXTHIF Mask */ 828 829 #define SPI_I2SSTS_TXUFIF_Pos (19) /*!< SPI_T::I2SSTS: TXUFIF Position */ 830 #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) /*!< SPI_T::I2SSTS: TXUFIF Mask */ 831 832 #define SPI_I2SSTS_RZCIF_Pos (20) /*!< SPI_T::I2SSTS: RZCIF Position */ 833 #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) /*!< SPI_T::I2SSTS: RZCIF Mask */ 834 835 #define SPI_I2SSTS_LZCIF_Pos (21) /*!< SPI_T::I2SSTS: LZCIF Position */ 836 #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) /*!< SPI_T::I2SSTS: LZCIF Mask */ 837 838 #define SPI_I2SSTS_SLVERRIF_Pos (22) /*!< SPI_T::I2SSTS: SLVERRIF Position */ 839 #define SPI_I2SSTS_SLVERRIF_Msk (0x1ul << SPI_I2SSTS_SLVERRIF_Pos) /*!< SPI_T::I2SSTS: SLVERRIF Mask */ 840 841 #define SPI_I2SSTS_TXRXRST_Pos (23) /*!< SPI_T::I2SSTS: TXRXRST Position */ 842 #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) /*!< SPI_T::I2SSTS: TXRXRST Mask */ 843 844 #define SPI_I2SSTS_RXCNT_Pos (24) /*!< SPI_T::I2SSTS: RXCNT Position */ 845 #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) /*!< SPI_T::I2SSTS: RXCNT Mask */ 846 847 #define SPI_I2SSTS_TXCNT_Pos (28) /*!< SPI_T::I2SSTS: TXCNT Position */ 848 #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) /*!< SPI_T::I2SSTS: TXCNT Mask */ 849 850 /**@}*/ /* SPI_CONST */ 851 /**@}*/ /* end of SPI register group */ 852 /**@}*/ /* end of REGISTER group */ 853 854 #endif /* __SPI_REG_H__ */ 855
