1 /* 2 * Copyright 2022, Cypress Semiconductor Corporation (an Infineon company) 3 * SPDX-License-Identifier: Apache-2.0 4 * 5 * Licensed under the Apache License, Version 2.0 (the "License"); 6 * you may not use this file except in compliance with the License. 7 * You may obtain a copy of the License at 8 * 9 * http://www.apache.org/licenses/LICENSE-2.0 10 * 11 * Unless required by applicable law or agreed to in writing, software 12 * distributed under the License is distributed on an "AS IS" BASIS, 13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14 * See the License for the specific language governing permissions and 15 * limitations under the License. 16 */ 17 18 #ifndef INCLUDED_WHD_SPI_H_ 19 #define INCLUDED_WHD_SPI_H_ 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /****************************************************** 26 * SPI Constants 27 ******************************************************/ 28 /* GSPI v1 */ 29 #define SPI_FRAME_CONTROL ( (uint32_t)0x1000D ) 30 31 /* Register addresses */ 32 #define SPI_BUS_CONTROL ( (uint32_t)0x0000 ) 33 #define SPI_RESPONSE_DELAY ( (uint32_t)0x0001 ) 34 #define SPI_STATUS_ENABLE ( (uint32_t)0x0002 ) 35 #define SPI_RESET_BP ( (uint32_t)0x0003 ) /* (corerev >= 1) */ 36 #define SPI_INTERRUPT_REGISTER ( (uint32_t)0x0004 ) /* 16 bits - Interrupt status */ 37 #define SPI_INTERRUPT_ENABLE_REGISTER ( (uint32_t)0x0006 ) /* 16 bits - Interrupt mask */ 38 #define SPI_STATUS_REGISTER ( (uint32_t)0x0008 ) /* 32 bits */ 39 #define SPI_FUNCTION1_INFO ( (uint32_t)0x000C ) /* 16 bits */ 40 #define SPI_FUNCTION2_INFO ( (uint32_t)0x000E ) /* 16 bits */ 41 #define SPI_FUNCTION3_INFO ( (uint32_t)0x0010 ) /* 16 bits */ 42 #define SPI_READ_TEST_REGISTER ( (uint32_t)0x0014 ) /* 32 bits */ 43 #define SPI_RESP_DELAY_F0 ( (uint32_t)0x001c ) /* 8 bits (corerev >= 3) */ 44 #define SPI_RESP_DELAY_F1 ( (uint32_t)0x001d ) /* 8 bits (corerev >= 3) */ 45 #define SPI_RESP_DELAY_F2 ( (uint32_t)0x001e ) /* 8 bits (corerev >= 3) */ 46 #define SPI_RESP_DELAY_F3 ( (uint32_t)0x001f ) /* 8 bits (corerev >= 3) */ 47 48 /****************************************************** 49 * Bit Masks 50 ******************************************************/ 51 52 /* GSPI */ 53 #define SPI_READ_TEST_REGISTER_VALUE ( (uint32_t)0xFEEDBEAD ) 54 #define SPI_READ_TEST_REG_LSB ( ( (SPI_READ_TEST_REGISTER_VALUE) ) & 0xff ) 55 #define SPI_READ_TEST_REG_LSB_SFT1 ( ( (SPI_READ_TEST_REGISTER_VALUE << 1) ) & 0xff ) 56 #define SPI_READ_TEST_REG_LSB_SFT2 ( ( (SPI_READ_TEST_REGISTER_VALUE << 1) + 1 ) & 0xff ) 57 #define SPI_READ_TEST_REG_LSB_SFT3 ( ( (SPI_READ_TEST_REGISTER_VALUE + 1) << 1 ) & 0xff ) 58 59 /* SPI_BUS_CONTROL Bits */ 60 #define WORD_LENGTH_32 ( (uint32_t)0x01 ) /* 0/1 16/32 bit word length */ 61 #define ENDIAN_BIG ( (uint32_t)0x02 ) /* 0/1 Little/Big Endian */ 62 #define CLOCK_PHASE ( (uint32_t)0x04 ) /* 0/1 clock phase delay */ 63 #define CLOCK_POLARITY ( (uint32_t)0x08 ) /* 0/1 Idle state clock polarity is low/high */ 64 #define HIGH_SPEED_MODE ( (uint32_t)0x10 ) /* 1/0 High Speed mode / Normal mode */ 65 #define INTERRUPT_POLARITY_HIGH ( (uint32_t)0x20 ) /* 1/0 Interrupt active polarity is high/low */ 66 #define WAKE_UP ( (uint32_t)0x80 ) /* 0/1 Wake-up command from Host to WLAN */ 67 68 /* SPI_RESPONSE_DELAY Bit mask */ 69 #define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */ 70 71 /* SPI_STATUS_ENABLE Bits */ 72 #define STATUS_ENABLE ( (uint32_t)0x01 ) /* 1/0 Status sent/not sent to host after read/write */ 73 #define INTR_WITH_STATUS ( (uint32_t)0x02 ) /* 0/1 Do-not / do-interrupt if status is sent */ 74 #define RESP_DELAY_ALL ( (uint32_t)0x04 ) /* Applicability of resp delay to F1 or all func's read */ 75 #define DWORD_PKT_LEN_EN ( (uint32_t)0x08 ) /* Packet len denoted in dwords instead of bytes */ 76 #define CMD_ERR_CHK_EN ( (uint32_t)0x20 ) /* Command error check enable */ 77 #define DATA_ERR_CHK_EN ( (uint32_t)0x40 ) /* Data error check enable */ 78 79 /* SPI_RESET_BP Bits*/ 80 #define RESET_ON_WLAN_BP_RESET ( (uint32_t)0x04 ) /* enable reset for WLAN backplane */ 81 #define RESET_SPI ( (uint32_t)0x80 ) /* reset the above enabled logic */ 82 83 /* SPI_INTERRUPT_REGISTER and SPI_INTERRUPT_ENABLE_REGISTER Bits */ 84 #define DATA_UNAVAILABLE ( (uint32_t)0x0001 ) /* Requested data not available; Clear by writing a "1" */ 85 #define F2_F3_FIFO_RD_UNDERFLOW ( (uint32_t)0x0002 ) 86 #define F2_F3_FIFO_WR_OVERFLOW ( (uint32_t)0x0004 ) 87 #define COMMAND_ERROR ( (uint32_t)0x0008 ) /* Cleared by writing 1 */ 88 #define DATA_ERROR ( (uint32_t)0x0010 ) /* Cleared by writing 1 */ 89 #define F2_PACKET_AVAILABLE ( (uint32_t)0x0020 ) 90 #define F3_PACKET_AVAILABLE ( (uint32_t)0x0040 ) 91 #define F1_OVERFLOW ( (uint32_t)0x0080 ) /* Due to last write. Bkplane has pending write requests */ 92 #define MISC_INTR0 ( (uint32_t)0x0100 ) 93 #define MISC_INTR1 ( (uint32_t)0x0200 ) 94 #define MISC_INTR2 ( (uint32_t)0x0400 ) 95 #define MISC_INTR3 ( (uint32_t)0x0800 ) 96 #define MISC_INTR4 ( (uint32_t)0x1000 ) 97 #define F1_INTR ( (uint32_t)0x2000 ) 98 #define F2_INTR ( (uint32_t)0x4000 ) 99 #define F3_INTR ( (uint32_t)0x8000 ) 100 101 /* SPI_STATUS_REGISTER Bits */ 102 #define STATUS_DATA_NOT_AVAILABLE ( (uint32_t)0x00000001 ) 103 #define STATUS_UNDERFLOW ( (uint32_t)0x00000002 ) 104 #define STATUS_OVERFLOW ( (uint32_t)0x00000004 ) 105 #define STATUS_F2_INTR ( (uint32_t)0x00000008 ) 106 #define STATUS_F3_INTR ( (uint32_t)0x00000010 ) 107 #define STATUS_F2_RX_READY ( (uint32_t)0x00000020 ) 108 #define STATUS_F3_RX_READY ( (uint32_t)0x00000040 ) 109 #define STATUS_HOST_CMD_DATA_ERR ( (uint32_t)0x00000080 ) 110 #define STATUS_F2_PKT_AVAILABLE ( (uint32_t)0x00000100 ) 111 #define STATUS_F2_PKT_LEN_MASK ( (uint32_t)0x000FFE00 ) 112 #define STATUS_F2_PKT_LEN_SHIFT ( (uint32_t)9 ) 113 #define STATUS_F3_PKT_AVAILABLE ( (uint32_t)0x00100000 ) 114 #define STATUS_F3_PKT_LEN_MASK ( (uint32_t)0xFFE00000 ) 115 #define STATUS_F3_PKT_LEN_SHIFT ( (uint32_t)21 ) 116 117 #ifdef __cplusplus 118 } /* extern "C" */ 119 #endif 120 121 #endif /* ifndef INCLUDED_WHD_SPI_H_ */ 122
