1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 /* SPI commands (actual on-wire commands not SPI controller bitmasks) 10 Suitable for use with spi_flash_hal_common_command static function. 11 */ 12 #define CMD_RDID 0x9F 13 #define CMD_RDUID 0x4B /* Read the flash unique ID*/ 14 #define CMD_WRSR 0x01 15 #define SR_WIP (1<<0) /* Status register write-in-progress bit */ 16 #define SR_WREN (1<<1) /* Status register write enable bit */ 17 #define CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ 18 #define CMD_WREN 0x06 19 #define CMD_WRDI 0x04 20 #define CMD_RDSR 0x05 21 #define CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ 22 #define CMD_RDSCUR 0x2B /* MXIC-specific, read security register */ 23 #define CMD_8READ 0xEC /* MXIC-specific, 8 I/O read */ 24 #define CMD_8DTRD 0xEE /* MXIC-specific, 8 I/O DTR read */ 25 #define CMD_RDFR 0x48 /* ISSI-specific, read function register */ 26 27 #define CMD_FASTRD_QIO 0xEB 28 #define CMD_FASTRD_QIO_4B 0xEC 29 #define CMD_FASTRD_QUAD 0x6B 30 #define CMD_FASTRD_QUAD_4B 0x6C 31 #define CMD_FASTRD_DIO 0xBB 32 #define CMD_FASTRD_DIO_4B 0xBC 33 #define CMD_FASTRD_DUAL 0x3B 34 #define CMD_FASTRD_DUAL_4B 0x3C 35 #define CMD_FASTRD 0x0B 36 #define CMD_FASTRD_4B 0x0C 37 #define CMD_READ 0x03 /* Speed limited */ 38 #define CMD_READ_4B 0x13 /* Speed limited */ 39 40 #define CMD_CHIP_ERASE 0xC7 41 #define CMD_SECTOR_ERASE 0x20 42 #define CMD_SECTOR_ERASE_4B 0x21 43 #define CMD_LARGE_BLOCK_ERASE 0xD8 /* 64KB block erase command */ 44 #define CMD_LARGE_BLOCK_ERASE_4B 0xDC /* 64KB block erase command */ 45 #define CMD_PROGRAM_PAGE 0x02 46 #define CMD_PROGRAM_PAGE_4B 0x12 47 #define CMD_SUSPEND 0x75 48 #define CMD_RESUME 0x7A 49 #define CMD_HPMEN 0xA3 /* Enable High Performance mode on flash */ 50 #define CMD_WRAP 0x77 51 #define CMD_BURST_RD 0xC0 /* wrap(0x77) and burst read are functionally same. But commands and formats is different */ 52 53 #define CMD_RST_EN 0x66 54 #define CMD_RST_DEV 0x99 55 56 #define SPI_FLASH_DIO_ADDR_BITLEN 24 57 #define SPI_FLASH_DIO_DUMMY_BITLEN 4 58 #define SPI_FLASH_QIO_ADDR_BITLEN 24 59 #define SPI_FLASH_QIO_DUMMY_BITLEN 6 60 #define SPI_FLASH_QOUT_ADDR_BITLEN 24 61 #define SPI_FLASH_QOUT_DUMMY_BITLEN 8 62 #define SPI_FLASH_DOUT_ADDR_BITLEN 24 63 #define SPI_FLASH_DOUT_DUMMY_BITLEN 8 64 #define SPI_FLASH_FASTRD_ADDR_BITLEN 24 65 #define SPI_FLASH_FASTRD_DUMMY_BITLEN 8 66 #define SPI_FLASH_SLOWRD_ADDR_BITLEN 24 67 #define SPI_FLASH_SLOWRD_DUMMY_BITLEN 0 68 #define SPI_FLASH_OPISTR_ADDR_BITLEN 32 69 #define SPI_FLASH_OPISTR_DUMMY_BITLEN 20 70 #define SPI_FLASH_OPIDTR_ADDR_BITLEN 32 71 #define SPI_FLASH_OPIDTR_DUMMY_BITLEN 40 72 #define SPI_FLASH_QIO_HPM_DUMMY_BITLEN 10 73 #define SPI_FLASH_DIO_HPM_DUMMY_BITLEN 8 74
