1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright(c) 2018 Intel Corporation. All rights reserved. 4 * 5 * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> 6 * Keyon Jie <yang.jie@linux.intel.com> 7 */ 8 9 /** 10 * \file include/ipc/topology.h 11 * \brief IPC definitions 12 * \author Liam Girdwood <liam.r.girdwood@linux.intel.com> 13 * \author Keyon Jie <yang.jie@linux.intel.com> 14 */ 15 16 #ifndef __IPC_TOPOLOGY_H__ 17 #define __IPC_TOPOLOGY_H__ 18 19 #include <ipc/header.h> 20 #include <stdint.h> 21 22 /* 23 * Component 24 */ 25 26 /* types of component */ 27 enum sof_comp_type { 28 SOF_COMP_NONE = 0, 29 SOF_COMP_HOST, 30 SOF_COMP_DAI, 31 SOF_COMP_SG_HOST, /**< scatter gather variant */ 32 SOF_COMP_SG_DAI, /**< scatter gather variant */ 33 SOF_COMP_VOLUME, 34 SOF_COMP_MIXER, 35 SOF_COMP_MUX, 36 SOF_COMP_SRC, 37 SOF_COMP_SPLITTER, 38 SOF_COMP_TONE, 39 SOF_COMP_SWITCH, 40 SOF_COMP_BUFFER, 41 SOF_COMP_EQ_IIR, 42 SOF_COMP_EQ_FIR, 43 SOF_COMP_KEYWORD_DETECT, 44 SOF_COMP_KPB, /* A key phrase buffer component */ 45 SOF_COMP_SELECTOR, /**< channel selector component */ 46 SOF_COMP_DEMUX, 47 SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ 48 SOF_COMP_DCBLOCK, 49 SOF_COMP_SMART_AMP, /**< smart amplifier component */ 50 SOF_COMP_CODEC_ADAPTOR, /**< codec adaptor */ 51 /* keep FILEREAD/FILEWRITE as the last ones */ 52 SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ 53 SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ 54 }; 55 56 /* XRUN action for component */ 57 #define SOF_XRUN_STOP 1 /**< stop stream */ 58 #define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ 59 #define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ 60 61 /* create new generic component - SOF_IPC_TPLG_COMP_NEW */ 62 struct sof_ipc_comp { 63 struct sof_ipc_cmd_hdr hdr; 64 uint32_t id; 65 enum sof_comp_type type; 66 uint32_t pipeline_id; 67 uint32_t core; 68 69 /** extended data length, 0 if no extended data (ABI3.17) */ 70 uint32_t ext_data_length; 71 } __attribute__((packed, aligned(4))); 72 73 /* 74 * Component Buffers 75 */ 76 77 /* 78 * SOF memory capabilities, add new ones at the end 79 */ 80 #define SOF_MEM_CAPS_RAM (1 << 0) 81 #define SOF_MEM_CAPS_ROM (1 << 1) 82 #define SOF_MEM_CAPS_EXT (1 << 2) /**< external */ 83 #define SOF_MEM_CAPS_LP (1 << 3) /**< low power */ 84 #define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */ 85 #define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */ 86 #define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */ 87 #define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */ 88 /* 89 * overrun will cause ring buffer overwrite, instead of XRUN. 90 */ 91 #define SOF_BUF_OVERRUN_PERMITTED BIT(0) 92 93 /* 94 * underrun will cause readback of 0s, instead of XRUN. 95 */ 96 #define SOF_BUF_UNDERRUN_PERMITTED BIT(1) 97 98 /* the UUID size in bytes, shared between FW and host */ 99 #define SOF_UUID_SIZE 16 100 101 /* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ 102 struct sof_ipc_buffer { 103 struct sof_ipc_comp comp; 104 uint32_t size; /**< buffer size in bytes */ 105 uint32_t caps; /**< SOF_MEM_CAPS_ */ 106 uint32_t flags; /**< SOF_BUF_ flags defined above */ 107 uint32_t reserved; /**< reserved for future use */ 108 } __attribute__((packed, aligned(4))); 109 110 /* generic component config data - must always be after struct sof_ipc_comp */ 111 struct sof_ipc_comp_config { 112 struct sof_ipc_cmd_hdr hdr; 113 uint32_t periods_sink; /**< 0 means variable */ 114 uint32_t periods_source;/**< 0 means variable */ 115 uint32_t reserved1; /**< reserved */ 116 uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ 117 uint32_t xrun_action; 118 119 /* reserved for future use */ 120 uint32_t reserved[2]; 121 } __attribute__((packed, aligned(4))); 122 123 /* generic host component */ 124 struct sof_ipc_comp_host { 125 struct sof_ipc_comp comp; 126 struct sof_ipc_comp_config config; 127 uint32_t direction; /**< SOF_IPC_STREAM_ */ 128 uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ 129 uint32_t dmac_config; /**< DMA engine specific */ 130 } __attribute__((packed, aligned(4))); 131 132 /* generic DAI component */ 133 struct sof_ipc_comp_dai { 134 struct sof_ipc_comp comp; 135 struct sof_ipc_comp_config config; 136 uint32_t direction; /**< SOF_IPC_STREAM_ */ 137 uint32_t dai_index; /**< index of this type dai */ 138 uint32_t type; /**< DAI type - SOF_DAI_ */ 139 uint32_t reserved; /**< reserved */ 140 } __attribute__((packed, aligned(4))); 141 142 /* generic mixer component */ 143 struct sof_ipc_comp_mixer { 144 struct sof_ipc_comp comp; 145 struct sof_ipc_comp_config config; 146 } __attribute__((packed, aligned(4))); 147 148 /* volume ramping types */ 149 enum sof_volume_ramp { 150 SOF_VOLUME_LINEAR = 0, 151 SOF_VOLUME_LOG, 152 SOF_VOLUME_LINEAR_ZC, 153 SOF_VOLUME_LOG_ZC, 154 }; 155 156 /* generic volume component */ 157 struct sof_ipc_comp_volume { 158 struct sof_ipc_comp comp; 159 struct sof_ipc_comp_config config; 160 uint32_t channels; 161 uint32_t min_value; 162 uint32_t max_value; 163 uint32_t ramp; /**< SOF_VOLUME_ */ 164 uint32_t initial_ramp; /**< ramp space in ms */ 165 } __attribute__((packed, aligned(4))); 166 167 /* generic SRC component */ 168 struct sof_ipc_comp_src { 169 struct sof_ipc_comp comp; 170 struct sof_ipc_comp_config config; 171 /* either source or sink rate must be non zero */ 172 uint32_t source_rate; /**< source rate or 0 for variable */ 173 uint32_t sink_rate; /**< sink rate or 0 for variable */ 174 uint32_t rate_mask; /**< SOF_RATE_ supported rates */ 175 } __attribute__((packed, aligned(4))); 176 177 /* generic ASRC component */ 178 struct sof_ipc_comp_asrc { 179 struct sof_ipc_comp comp; 180 struct sof_ipc_comp_config config; 181 /* either source or sink rate must be non zero */ 182 uint32_t source_rate; /**< Define fixed source rate or */ 183 /**< use 0 to indicate need to get */ 184 /**< the rate from stream */ 185 uint32_t sink_rate; /**< Define fixed sink rate or */ 186 /**< use 0 to indicate need to get */ 187 /**< the rate from stream */ 188 uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ 189 /**< When 1 the ASRC tracks and */ 190 /**< compensates for drift. */ 191 uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ 192 /**< ASRC consumes a defined number */ 193 /**< of frames at input, with varying */ 194 /**< number of frames at output. */ 195 /**< In pull mode the ASRC outputs */ 196 /**< a defined number of frames while */ 197 /**< number of input frames varies. */ 198 199 /* reserved for future use */ 200 uint32_t reserved[4]; 201 } __attribute__((packed, aligned(4))); 202 203 /* generic MUX component */ 204 struct sof_ipc_comp_mux { 205 struct sof_ipc_comp comp; 206 struct sof_ipc_comp_config config; 207 } __attribute__((packed, aligned(4))); 208 209 /* generic tone generator component */ 210 struct sof_ipc_comp_tone { 211 struct sof_ipc_comp comp; 212 struct sof_ipc_comp_config config; 213 int32_t sample_rate; 214 int32_t frequency; 215 int32_t amplitude; 216 int32_t freq_mult; 217 int32_t ampl_mult; 218 int32_t length; 219 int32_t period; 220 int32_t repeats; 221 int32_t ramp_step; 222 } __attribute__((packed, aligned(4))); 223 224 /* generic "effect", "codec" or proprietary processing component */ 225 struct sof_ipc_comp_process { 226 struct sof_ipc_comp comp; 227 struct sof_ipc_comp_config config; 228 uint32_t size; /**< size of bespoke data section in bytes */ 229 uint32_t type; /**< sof_ipc_process_type */ 230 231 /* reserved for future use */ 232 uint32_t reserved[7]; 233 234 unsigned char data[0]; 235 } __attribute__((packed, aligned(4))); 236 237 /* IPC file component used by testbench only */ 238 struct sof_ipc_comp_file { 239 struct sof_ipc_comp comp; 240 struct sof_ipc_comp_config config; 241 uint32_t rate; 242 uint32_t channels; 243 char *fn; 244 uint32_t mode; 245 uint32_t frame_fmt; 246 } __attribute__((packed, aligned(4))); 247 248 /* frees components, buffers and pipelines 249 * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE 250 */ 251 struct sof_ipc_free { 252 struct sof_ipc_cmd_hdr hdr; 253 uint32_t id; 254 } __attribute__((packed, aligned(4))); 255 256 struct sof_ipc_comp_reply { 257 struct sof_ipc_reply rhdr; 258 uint32_t id; 259 uint32_t offset; 260 } __attribute__((packed, aligned(4))); 261 262 /* 263 * Pipeline 264 */ 265 266 /** \brief Types of pipeline scheduling time domains */ 267 enum sof_ipc_pipe_sched_time_domain { 268 SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ 269 SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ 270 }; 271 272 /* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ 273 struct sof_ipc_pipe_new { 274 struct sof_ipc_cmd_hdr hdr; 275 uint32_t comp_id; /**< component id for pipeline */ 276 uint32_t pipeline_id; /**< pipeline id */ 277 uint32_t sched_id; /**< Scheduling component id */ 278 uint32_t core; /**< core we run on */ 279 uint32_t period; /**< execution period in us*/ 280 uint32_t priority; /**< priority level 0 (low) to 10 (max) */ 281 uint32_t period_mips; /**< worst case instruction count per period */ 282 uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ 283 uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ 284 uint32_t time_domain; /**< scheduling time domain */ 285 } __attribute__((packed, aligned(4))); 286 287 /* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ 288 struct sof_ipc_pipe_ready { 289 struct sof_ipc_cmd_hdr hdr; 290 uint32_t comp_id; 291 } __attribute__((packed, aligned(4))); 292 293 struct sof_ipc_pipe_free { 294 struct sof_ipc_cmd_hdr hdr; 295 uint32_t comp_id; 296 } __attribute__((packed, aligned(4))); 297 298 /* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ 299 struct sof_ipc_pipe_comp_connect { 300 struct sof_ipc_cmd_hdr hdr; 301 uint32_t source_id; 302 uint32_t sink_id; 303 } __attribute__((packed, aligned(4))); 304 305 /* extended data struct for UUID components */ 306 struct sof_ipc_comp_ext { 307 uint8_t uuid[SOF_UUID_SIZE]; 308 } __attribute__((packed, aligned(4))); 309 310 #endif /* __IPC_TOPOLOGY_H__ */ 311
