1 /* 2 * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 // The long term plan is to have a single soc_caps.h for each peripheral. 8 // During the refactoring and multichip support development process, we 9 // seperate these information into periph_caps.h for each peripheral and 10 // include them here. 11 12 /* 13 * These defines are parsed and imported as kconfig variables via the script 14 * `tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py` 15 * 16 * If this file is changed the script will automatically run the script 17 * and generate the kconfig variables as part of the pre-commit hooks. 18 * 19 * It can also be ran manually with `./tools/gen_soc_caps_kconfig/gen_soc_caps_kconfig.py 'components/soc/esp32c6/include/soc/'` 20 * 21 * For more information see `tools/gen_soc_caps_kconfig/README.md` 22 * 23 */ 24 25 #pragma once 26 27 /*-------------------------- COMMON CAPS ---------------------------------------*/ 28 #define SOC_ADC_SUPPORTED 1 29 #define SOC_DEDICATED_GPIO_SUPPORTED 1 30 #define SOC_UART_SUPPORTED 1 31 #define SOC_GDMA_SUPPORTED 1 32 #define SOC_GPTIMER_SUPPORTED 1 33 #define SOC_PCNT_SUPPORTED 1 34 #define SOC_MCPWM_SUPPORTED 1 35 #define SOC_TWAI_SUPPORTED 1 36 #define SOC_ETM_SUPPORTED 1 37 #define SOC_PARLIO_SUPPORTED 1 38 #define SOC_BT_SUPPORTED 1 39 #define SOC_IEEE802154_SUPPORTED 1 40 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 41 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 42 #define SOC_TEMP_SENSOR_SUPPORTED 1 43 #define SOC_WIFI_SUPPORTED 1 44 #define SOC_SUPPORTS_SECURE_DL_MODE 1 45 #define SOC_ULP_SUPPORTED 1 46 #define SOC_LP_CORE_SUPPORTED 1 47 #define SOC_EFUSE_KEY_PURPOSE_FIELD 1 48 #define SOC_RTC_FAST_MEM_SUPPORTED 1 49 #define SOC_RTC_MEM_SUPPORTED 1 50 #define SOC_I2S_SUPPORTED 1 51 #define SOC_RMT_SUPPORTED 1 52 #define SOC_SDM_SUPPORTED 1 53 #define SOC_GPSPI_SUPPORTED 1 54 #define SOC_LEDC_SUPPORTED 1 55 #define SOC_I2C_SUPPORTED 1 56 #define SOC_SYSTIMER_SUPPORTED 1 57 #define SOC_SUPPORT_COEXISTENCE 1 58 #define SOC_AES_SUPPORTED 1 59 #define SOC_MPI_SUPPORTED 1 60 #define SOC_SHA_SUPPORTED 1 61 #define SOC_HMAC_SUPPORTED 1 62 #define SOC_DIG_SIGN_SUPPORTED 1 63 #define SOC_ECC_SUPPORTED 1 64 #define SOC_FLASH_ENC_SUPPORTED 1 65 #define SOC_SECURE_BOOT_SUPPORTED 1 66 #define SOC_SDIO_SLAVE_SUPPORTED 1 67 #define SOC_BOD_SUPPORTED 1 68 #define SOC_APM_SUPPORTED 1 69 #define SOC_PMU_SUPPORTED 1 70 #define SOC_PAU_SUPPORTED 1 71 #define SOC_LP_TIMER_SUPPORTED 1 72 #define SOC_LP_AON_SUPPORTED 1 73 #define SOC_LP_I2C_SUPPORTED 1 74 75 /*-------------------------- XTAL CAPS ---------------------------------------*/ 76 #define SOC_XTAL_SUPPORT_40M 1 77 78 /*-------------------------- AES CAPS -----------------------------------------*/ 79 #define SOC_AES_SUPPORT_DMA (1) 80 81 /* Has a centralized DMA, which is shared with all peripherals */ 82 #define SOC_AES_GDMA (1) 83 84 #define SOC_AES_SUPPORT_AES_128 (1) 85 #define SOC_AES_SUPPORT_AES_256 (1) 86 87 /*-------------------------- ADC CAPS -------------------------------*/ 88 /*!< SAR ADC Module*/ 89 #define SOC_ADC_DIG_CTRL_SUPPORTED 1 90 #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1 91 #define SOC_ADC_MONITOR_SUPPORTED 1 92 #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit 93 #define SOC_ADC_DMA_SUPPORTED 1 94 #define SOC_ADC_PERIPH_NUM (1U) 95 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7) 96 #define SOC_ADC_MAX_CHANNEL_NUM (7) 97 #define SOC_ADC_ATTEN_NUM (4) 98 99 /*!< Digital */ 100 #define SOC_ADC_DIGI_CONTROLLER_NUM (1U) 101 #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */ 102 #define SOC_ADC_DIGI_MAX_BITWIDTH (12) 103 #define SOC_ADC_DIGI_MIN_BITWIDTH (12) 104 #define SOC_ADC_DIGI_IIR_FILTER_NUM (2) 105 #define SOC_ADC_DIGI_MONITOR_NUM (2) 106 #define SOC_ADC_DIGI_RESULT_BYTES (4) 107 #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4) 108 /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */ 109 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 110 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 111 112 /*!< RTC */ 113 #define SOC_ADC_RTC_MIN_BITWIDTH (12) 114 #define SOC_ADC_RTC_MAX_BITWIDTH (12) 115 116 /*!< Calibration */ 117 #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ 118 #define SOC_ADC_SELF_HW_CALI_SUPPORTED (1) /*!< support HW offset self calibration */ 119 #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */ 120 121 /*!< Interrupt */ 122 #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) 123 124 // ESP32C6-TODO: Copy from esp32c6, need check 125 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ 126 #define SOC_APB_BACKUP_DMA (0) 127 128 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 129 #define SOC_BROWNOUT_RESET_SUPPORTED 1 130 131 /*-------------------------- CACHE CAPS --------------------------------------*/ 132 #define SOC_SHARED_IDCACHE_SUPPORTED 1 //Shared Cache for both instructions and data 133 #define SOC_CACHE_FREEZE_SUPPORTED 1 134 135 /*-------------------------- CPU CAPS ----------------------------------------*/ 136 #define SOC_CPU_CORES_NUM (1U) 137 #define SOC_CPU_INTR_NUM 32 138 #define SOC_CPU_HAS_FLEXIBLE_INTC 1 139 #define SOC_INT_PLIC_SUPPORTED 1 //riscv platform-level interrupt controller 140 141 #define SOC_CPU_BREAKPOINTS_NUM 4 142 #define SOC_CPU_WATCHPOINTS_NUM 4 143 #define SOC_CPU_WATCHPOINT_MAX_REGION_SIZE 0x80000000 // bytes 144 145 #define SOC_CPU_HAS_PMA 1 146 #define SOC_CPU_IDRAM_SPLIT_USING_PMP 1 147 148 // TODO: IDF-5360 (Copy from esp32c3, need check) 149 /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ 150 /** The maximum length of a Digital Signature in bits. */ 151 #define SOC_DS_SIGNATURE_MAX_BIT_LEN (3072) 152 153 /** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ 154 #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) 155 156 /** Maximum wait time for DS parameter decryption key. If overdue, then key error. 157 See TRM DS chapter for more details */ 158 #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) 159 160 /*-------------------------- GDMA CAPS -------------------------------------*/ 161 #define SOC_GDMA_GROUPS (1U) // Number of GDMA groups 162 #define SOC_GDMA_PAIRS_PER_GROUP (3) // Number of GDMA pairs in each group 163 #define SOC_GDMA_SUPPORT_ETM (1) // Support ETM submodule 164 165 /*-------------------------- ETM CAPS --------------------------------------*/ 166 #define SOC_ETM_GROUPS 1U // Number of ETM groups 167 #define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group 168 169 /*-------------------------- GPIO CAPS ---------------------------------------*/ 170 // ESP32-C6 has 1 GPIO peripheral 171 #define SOC_GPIO_PORT 1U 172 #define SOC_GPIO_PIN_COUNT 31 173 #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 174 #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 175 176 // GPIO peripheral has the ETM extension 177 #define SOC_GPIO_SUPPORT_ETM 1 178 179 // Target has the full LP IO subsystem 180 // On ESP32-C6, Digital IOs have their own registers to control pullup/down capability, independent of LP registers. 181 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) 182 // GPIO0~7 on ESP32C6 can support chip deep sleep wakeup 183 #define SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP (1) 184 185 #define SOC_GPIO_VALID_GPIO_MASK ((1U<<SOC_GPIO_PIN_COUNT) - 1) 186 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK SOC_GPIO_VALID_GPIO_MASK 187 188 #define SOC_GPIO_IN_RANGE_MAX 30 189 #define SOC_GPIO_OUT_RANGE_MAX 30 190 191 #define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7) 192 193 // digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30) 194 #define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL 195 196 // Support to force hold all IOs 197 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) 198 // Support to hold a single digital I/O when the digital domain is powered off 199 #define SOC_GPIO_SUPPORT_HOLD_SINGLE_IO_IN_DSLP (1) 200 201 /*-------------------------- RTCIO CAPS --------------------------------------*/ 202 #define SOC_RTCIO_PIN_COUNT 8 203 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 /* This macro indicates that the target has separate RTC IOMUX hardware feature, 204 * so it supports unique IOMUX configuration (including IE, OE, PU, PD, DRV etc.) 205 * when the pins are switched to RTC function. 206 */ 207 #define SOC_RTCIO_HOLD_SUPPORTED 1 208 #define SOC_RTCIO_WAKE_SUPPORTED 1 209 210 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ 211 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ 212 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ 213 #define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */ 214 215 /*-------------------------- I2C CAPS ----------------------------------------*/ 216 // ESP32-C6 has 1 I2C 217 #define SOC_I2C_NUM (1U) 218 219 #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ 220 #define SOC_I2C_CMD_REG_NUM (8) /*!< Number of I2C command registers */ 221 #define SOC_I2C_SUPPORT_SLAVE (1) 222 223 // FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined. 224 #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) 225 226 #define SOC_I2C_SUPPORT_XTAL (1) 227 #define SOC_I2C_SUPPORT_RTC (1) 228 229 /*-------------------------- LP_I2C CAPS -------------------------------------*/ 230 // ESP32-C6 has 1 LP_I2C 231 #define SOC_LP_I2C_NUM (1U) 232 233 #define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */ 234 235 /*-------------------------- I2S CAPS ----------------------------------------*/ 236 #define SOC_I2S_NUM (1U) 237 #define SOC_I2S_HW_VERSION_2 (1) 238 #define SOC_I2S_SUPPORTS_XTAL (1) 239 #define SOC_I2S_SUPPORTS_PLL_F160M (1) 240 #define SOC_I2S_SUPPORTS_PCM (1) 241 #define SOC_I2S_SUPPORTS_PDM (1) 242 #define SOC_I2S_SUPPORTS_PDM_TX (1) 243 #define SOC_I2S_PDM_MAX_TX_LINES (2) 244 #define SOC_I2S_SUPPORTS_TDM (1) 245 246 /*-------------------------- LEDC CAPS ---------------------------------------*/ 247 #define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1) 248 #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) 249 #define SOC_LEDC_CHANNEL_NUM (6) 250 #define SOC_LEDC_TIMER_BIT_WIDTH (20) 251 #define SOC_LEDC_SUPPORT_FADE_STOP (1) 252 #define SOC_LEDC_GAMMA_CURVE_FADE_SUPPORTED (1) 253 #define SOC_LEDC_GAMMA_CURVE_FADE_RANGE_MAX (16) 254 #define SOC_LEDC_FADE_PARAMS_BIT_WIDTH (10) 255 256 /*-------------------------- MMU CAPS ----------------------------------------*/ 257 #define SOC_MMU_PAGE_SIZE_CONFIGURABLE (1) 258 #define SOC_MMU_PERIPH_NUM (1U) 259 #define SOC_MMU_LINEAR_ADDRESS_REGION_NUM (1U) 260 #define SOC_MMU_DI_VADDR_SHARED (1) /*!< D/I vaddr are shared */ 261 262 /*-------------------------- MPU CAPS ----------------------------------------*/ 263 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 264 #define SOC_MPU_MIN_REGION_SIZE 0x20000000U 265 #define SOC_MPU_REGIONS_MAX_NUM 8 266 #define SOC_MPU_REGION_RO_SUPPORTED 0 267 #define SOC_MPU_REGION_WO_SUPPORTED 0 268 269 /*-------------------------- PCNT CAPS ---------------------------------------*/ 270 #define SOC_PCNT_GROUPS 1U 271 #define SOC_PCNT_UNITS_PER_GROUP 4 272 #define SOC_PCNT_CHANNELS_PER_UNIT 2 273 #define SOC_PCNT_THRES_POINT_PER_UNIT 2 274 #define SOC_PCNT_SUPPORT_RUNTIME_THRES_UPDATE 1 275 276 /*--------------------------- RMT CAPS ---------------------------------------*/ 277 #define SOC_RMT_GROUPS 1U /*!< One RMT group */ 278 #define SOC_RMT_TX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Transmit */ 279 #define SOC_RMT_RX_CANDIDATES_PER_GROUP 2 /*!< Number of channels that capable of Receive */ 280 #define SOC_RMT_CHANNELS_PER_GROUP 4 /*!< Total 4 channels */ 281 #define SOC_RMT_MEM_WORDS_PER_CHANNEL 48 /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ 282 #define SOC_RMT_SUPPORT_RX_PINGPONG 1 /*!< Support Ping-Pong mode on RX path */ 283 #define SOC_RMT_SUPPORT_RX_DEMODULATION 1 /*!< Support signal demodulation on RX path (i.e. remove carrier) */ 284 #define SOC_RMT_SUPPORT_TX_ASYNC_STOP 1 /*!< Support stop transmission asynchronously */ 285 #define SOC_RMT_SUPPORT_TX_LOOP_COUNT 1 /*!< Support transmit specified number of cycles in loop mode */ 286 #define SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP 1 /*!< Hardware support of auto-stop in loop mode */ 287 #define SOC_RMT_SUPPORT_TX_SYNCHRO 1 /*!< Support coordinate a group of TX channels to start simultaneously */ 288 #define SOC_RMT_SUPPORT_TX_CARRIER_DATA_ONLY 1 /*!< TX carrier can be modulated to data phase only */ 289 #define SOC_RMT_SUPPORT_XTAL 1 /*!< Support set XTAL clock as the RMT clock source */ 290 #define SOC_RMT_SUPPORT_RC_FAST 1 /*!< Support set RC_FAST as the RMT clock source */ 291 292 /*-------------------------- MCPWM CAPS --------------------------------------*/ 293 #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) 294 #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has 295 #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has 296 #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has 297 #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has 298 #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has 299 #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has 300 #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has 301 #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has 302 #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has 303 #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output 304 #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix) 305 #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers 306 307 /*------------------------ USB SERIAL JTAG CAPS ------------------------------*/ 308 // #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395 309 310 /*-------------------------- PARLIO CAPS --------------------------------------*/ 311 #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */ 312 #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */ 313 #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */ 314 #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ 315 #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */ 316 #define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */ 317 318 /*--------------------------- RSA CAPS ---------------------------------------*/ 319 #define SOC_RSA_MAX_BIT_LEN (3072) 320 321 // TODO: IDF-5353 (Copy from esp32c3, need check) 322 /*--------------------------- SHA CAPS ---------------------------------------*/ 323 324 /* Max amount of bytes in a single DMA operation is 4095, 325 for SHA this means that the biggest safe amount of bytes is 326 31 blocks of 128 bytes = 3968 327 */ 328 #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) 329 #define SOC_SHA_SUPPORT_DMA (1) 330 331 /* The SHA engine is able to resume hashing from a user */ 332 #define SOC_SHA_SUPPORT_RESUME (1) 333 334 /* Has a centralized DMA, which is shared with all peripherals */ 335 #define SOC_SHA_GDMA (1) 336 337 /* Supported HW algorithms */ 338 #define SOC_SHA_SUPPORT_SHA1 (1) 339 #define SOC_SHA_SUPPORT_SHA224 (1) 340 #define SOC_SHA_SUPPORT_SHA256 (1) 341 342 /*-------------------------- Sigma Delta Modulator CAPS -----------------*/ 343 #define SOC_SDM_GROUPS 1U 344 #define SOC_SDM_CHANNELS_PER_GROUP 4 345 #define SOC_SDM_CLK_SUPPORT_PLL_F80M 1 346 #define SOC_SDM_CLK_SUPPORT_XTAL 1 347 348 /*-------------------------- SPI CAPS ----------------------------------------*/ 349 #define SOC_SPI_PERIPH_NUM 2 350 #define SOC_SPI_PERIPH_CS_NUM(i) 6 351 #define SOC_SPI_MAX_CS_NUM 6 352 353 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 354 355 #define SOC_SPI_SUPPORT_DDRCLK 1 356 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 357 #define SOC_SPI_SUPPORT_CD_SIG 1 358 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 359 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 360 #define SOC_SPI_SUPPORT_CLK_XTAL 1 361 #define SOC_SPI_SUPPORT_CLK_PLL_F80M 1 362 #define SOC_SPI_SUPPORT_CLK_RC_FAST 1 363 364 // Peripheral supports DIO, DOUT, QIO, or QOUT 365 // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, 366 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) 367 368 #define SOC_MEMSPI_IS_INDEPENDENT 1 369 #define SOC_SPI_MAX_PRE_DIVIDER 16 370 371 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ 372 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) 373 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) 374 #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) 375 #define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1) 376 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) 377 #define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1) 378 #define SOC_SPI_MEM_SUPPORT_WRAP (1) 379 380 #define SOC_MEMSPI_SRC_FREQ_80M_SUPPORTED 1 381 #define SOC_MEMSPI_SRC_FREQ_40M_SUPPORTED 1 382 #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 383 384 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ 385 #define SOC_SYSTIMER_COUNTER_NUM 2 // Number of counter units 386 #define SOC_SYSTIMER_ALARM_NUM 3 // Number of alarm units 387 #define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part 388 #define SOC_SYSTIMER_BIT_WIDTH_HI 20 // Bit width of systimer high part 389 #define SOC_SYSTIMER_FIXED_DIVIDER 1 // Clock source divider is fixed: 2.5 390 #define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source 391 #define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt 392 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current) 393 #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event 394 395 /*-------------------------- LP_TIMER CAPS ----------------------------------*/ 396 #define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part 397 #define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part 398 399 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ 400 #define SOC_TIMER_GROUPS (2) 401 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U) 402 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) 403 #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) 404 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1) 405 #define SOC_TIMER_GROUP_TOTAL_TIMERS (2) 406 #define SOC_TIMER_SUPPORT_ETM (1) 407 408 /*--------------------------- WATCHDOG CAPS ---------------------------------------*/ 409 #define SOC_MWDT_SUPPORT_XTAL (1) 410 411 /*-------------------------- TWAI CAPS ---------------------------------------*/ 412 #define SOC_TWAI_CONTROLLER_NUM 2 413 #define SOC_TWAI_CLK_SUPPORT_XTAL 1 414 #define SOC_TWAI_BRP_MIN 2 415 #define SOC_TWAI_BRP_MAX 32768 416 #define SOC_TWAI_SUPPORTS_RX_STATUS 1 417 418 /*-------------------------- eFuse CAPS----------------------------*/ 419 #define SOC_EFUSE_DIS_DOWNLOAD_ICACHE 1 420 #define SOC_EFUSE_DIS_PAD_JTAG 1 421 #define SOC_EFUSE_DIS_USB_JTAG 1 422 #define SOC_EFUSE_DIS_DIRECT_BOOT 1 423 #define SOC_EFUSE_SOFT_DIS_JTAG 1 424 #define SOC_EFUSE_DIS_ICACHE 1 425 #define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // AES-XTS key purpose not supported for this block 426 427 /*-------------------------- Secure Boot CAPS----------------------------*/ 428 #define SOC_SECURE_BOOT_V2_RSA 1 429 #define SOC_SECURE_BOOT_V2_ECC 1 430 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 431 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 432 #define SOC_SUPPORT_SECURE_BOOT_REVOKE_KEY 1 433 434 /*-------------------------- Flash Encryption CAPS----------------------------*/ 435 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (32) 436 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 437 #define SOC_FLASH_ENCRYPTION_XTS_AES_128 1 438 439 /*------------------------ Anti DPA (Security) CAPS --------------------------*/ 440 #define SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 1 441 442 /*-------------------------- UART CAPS ---------------------------------------*/ 443 // ESP32-C6 has 2 UARTs 444 #define SOC_UART_NUM (3) 445 #define SOC_UART_HP_NUM (2) 446 #define SOC_UART_LP_NUM (1U) 447 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ 448 #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ 449 #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */ 450 #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ 451 #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ 452 #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ 453 454 // UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled 455 #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1) 456 457 // TODO: IDF-5679 (Copy from esp32c3, need check) 458 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ 459 #define SOC_COEX_HW_PTI (1) 460 461 /*-------------------------- EXTERNAL COEXISTENCE CAPS -------------------------------------*/ 462 #define SOC_EXTERNAL_COEX_ADVANCE (1) /*!< HARDWARE ADVANCED EXTERNAL COEXISTENCE CAPS */ 463 #define SOC_EXTERNAL_COEX_LEADER_TX_LINE (0) /*!< EXTERNAL COEXISTENCE TX LINE CAPS */ 464 465 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 466 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 467 468 // TODO: IDF-5679 (Copy from esp32c3, need check) 469 /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ 470 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) 471 472 // TODO: IDF-5351 (Copy from esp32c3, need check) 473 /*-------------------------- Power Management CAPS ----------------------------*/ 474 #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) 475 #define SOC_PM_SUPPORT_BEACON_WAKEUP (1) 476 #define SOC_PM_SUPPORT_BT_WAKEUP (1) 477 #define SOC_PM_SUPPORT_EXT1_WAKEUP (1) 478 #define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configue the EXT1 trigger level */ 479 #define SOC_PM_SUPPORT_CPU_PD (1) 480 #define SOC_PM_SUPPORT_MODEM_PD (1) 481 #define SOC_PM_SUPPORT_XTAL32K_PD (1) 482 #define SOC_PM_SUPPORT_RC32K_PD (1) 483 #define SOC_PM_SUPPORT_RC_FAST_PD (1) 484 #define SOC_PM_SUPPORT_VDDSDIO_PD (1) 485 #define SOC_PM_SUPPORT_TOP_PD (1) 486 #define SOC_PM_SUPPORT_HP_AON_PD (1) 487 #define SOC_PM_SUPPORT_MAC_BB_PD (1) 488 #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) 489 490 #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) 491 /* macro redefine for pass esp_wifi headers md5sum check */ 492 #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE 493 494 495 #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */ 496 497 #define SOC_PM_CPU_RETENTION_BY_SW (1) 498 #define SOC_PM_MODEM_RETENTION_BY_REGDMA (1) 499 #define SOC_PM_RETENTION_HAS_CLOCK_BUG (1) 500 501 #define SOC_PM_PAU_LINK_NUM (4) 502 503 #define SOC_PM_PAU_REGDMA_UPDATE_CACHE_BEFORE_WAIT_COMPARE (1) 504 505 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/ 506 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1) 507 #define SOC_MODEM_CLOCK_IS_INDEPENDENT (1) 508 509 #define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */ 510 #define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */ 511 #define SOC_CLK_RC32K_SUPPORTED (1) /*!< Support an internal 32kHz RC oscillator */ 512 513 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/ 514 #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1) 515 #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1) 516 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT (1) 517 518 /*--------------------------------- RNG CAPS ---------------------------------------------*/ 519 #define SOC_RNG_CLOCK_IS_INDEPENDENT (1) 520 521 /*------------------------------------ WI-FI CAPS ------------------------------------*/ 522 #define SOC_WIFI_HW_TSF (1) /*!< Support hardware TSF */ 523 #define SOC_WIFI_FTM_SUPPORT (1) /*!< Support FTM */ 524 #define SOC_WIFI_GCMP_SUPPORT (1) /*!< Support GCMP(GCMP128 and GCMP256) */ 525 #define SOC_WIFI_WAPI_SUPPORT (1) /*!< Support WAPI */ 526 #define SOC_WIFI_CSI_SUPPORT (1) /*!< Support CSI */ 527 #define SOC_WIFI_MESH_SUPPORT (1) /*!< Support WIFI MESH */ 528 #define SOC_WIFI_HE_SUPPORT (1) /*!< Support Wi-Fi 6 */ 529 530 /*---------------------------------- Bluetooth CAPS ----------------------------------*/ 531 #define SOC_BLE_SUPPORTED (1) /*!< Support Bluetooth Low Energy hardware */ 532 #define SOC_BLE_MESH_SUPPORTED (1) /*!< Support BLE MESH */ 533 #define SOC_ESP_NIMBLE_CONTROLLER (1) /*!< Support BLE EMBEDDED controller V1 */ 534 #define SOC_BLE_50_SUPPORTED (1) /*!< Support Bluetooth 5.0 */ 535 #define SOC_BLE_DEVICE_PRIVACY_SUPPORTED (1) /*!< Support BLE device privacy mode */ 536 #define SOC_BLE_POWER_CONTROL_SUPPORTED (1) /*!< Support Bluetooth Power Control */ 537 #define SOC_BLE_PERIODIC_ADV_ENH_SUPPORTED (1) /*!< Support For BLE Periodic Adv Enhancements */ 538 #define SOC_BLUFI_SUPPORTED (1) /*!< Support BLUFI */ 539 #define SOC_BLE_MULTI_CONN_OPTIMIZATION (1) /*!< Support multiple connections optimization */ 540 541 #define SOC_BLE_USE_WIFI_PWR_CLK_WORKAROUND (1) 542 543 /*------------------------------------- PHY CAPS -------------------------------------*/ 544 #define SOC_PHY_COMBO_MODULE (1) /*!< Support Wi-Fi, BLE and 15.4*/ 545 546 /*------------------------------------- No Reset CAPS -------------------------------------*/ 547 #define SOC_CAPS_NO_RESET_BY_ANA_BOD (1) 548
