1 /* 2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /* 8 * Soc capabilities file, describing the following chip attributes: 9 * - Peripheral or feature supported or not 10 * - Number of resources (peripheral, channel, etc.) 11 * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency 12 * supported, etc. 13 * 14 * For boolean definitions: 15 * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`. 16 * (`#define` blank string causes error when checking by `#if x`) 17 * - if false: not define anything at all. 18 * (`#ifdef x` is true even when `#define 0` is defined before.) 19 * 20 * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`. 21 * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define 22 * x 0`, it's still a risk.) 23 * 24 * ECO & exceptions: 25 * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by 26 * `#if x` and `#if !x`, making these missing definitions more obvious. 27 */ 28 29 #pragma once 30 31 /*-------------------------- COMMON CAPS ---------------------------------------*/ 32 #define SOC_ADC_SUPPORTED 1 33 #define SOC_DAC_SUPPORTED 1 34 #define SOC_TWAI_SUPPORTED 1 35 #define SOC_CP_DMA_SUPPORTED 1 36 #define SOC_CPU_CORES_NUM 1 37 #define SOC_DEDICATED_GPIO_SUPPORTED 1 38 #define SOC_SUPPORTS_SECURE_DL_MODE 1 39 #define SOC_RISCV_COPROC_SUPPORTED 1 40 #define SOC_USB_OTG_SUPPORTED 1 41 #define SOC_PCNT_SUPPORTED 1 42 #define SOC_ULP_SUPPORTED 1 43 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 44 #define SOC_CCOMP_TIMER_SUPPORTED 1 45 #define SOC_DIG_SIGN_SUPPORTED 1 46 #define SOC_HMAC_SUPPORTED 1 47 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 48 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 49 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 50 #define SOC_TEMP_SENSOR_SUPPORTED 1 51 #define SOC_CACHE_SUPPORT_WRAP 1 52 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 53 #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 54 #define SOC_PSRAM_DMA_CAPABLE 1 55 #define SOC_XT_WDT_SUPPORTED 1 56 57 /*-------------------------- ADC CAPS ----------------------------------------*/ 58 /*!< SAR ADC Module*/ 59 #define SOC_ADC_RTC_CTRL_SUPPORTED 1 60 #define SOC_ADC_DIG_CTRL_SUPPORTED 1 61 #define SOC_ADC_ARBITER_SUPPORTED 1 62 #define SOC_ADC_FILTER_SUPPORTED 1 63 #define SOC_ADC_MONITOR_SUPPORTED 1 64 #define SOC_ADC_PERIPH_NUM (2) 65 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) 66 #define SOC_ADC_MAX_CHANNEL_NUM (10) 67 68 /*!< Digital */ 69 #define SOC_ADC_DIGI_CONTROLLER_NUM (2) 70 #define SOC_ADC_PATT_LEN_MAX (32) /*!< Two pattern table, each contains 16 items. Each item takes 1 byte */ 71 #define SOC_ADC_DIGI_MAX_BITWIDTH (12) 72 /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ 73 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 74 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 75 76 /*!< RTC */ 77 #define SOC_ADC_MAX_BITWIDTH (13) 78 79 /*!< Calibration */ 80 #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ 81 82 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 83 #define SOC_BROWNOUT_RESET_SUPPORTED 1 84 85 /*-------------------------- CP-DMA CAPS -------------------------------------*/ 86 #define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ 87 88 /*-------------------------- CPU CAPS ----------------------------------------*/ 89 #define SOC_CPU_BREAKPOINTS_NUM 2 90 #define SOC_CPU_WATCHPOINTS_NUM 2 91 92 #define SOC_CPU_WATCHPOINT_SIZE 64 // bytes 93 94 /*-------------------------- DAC CAPS ----------------------------------------*/ 95 #define SOC_DAC_PERIPH_NUM 2 96 #define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit 97 98 /*-------------------------- GPIO CAPS ---------------------------------------*/ 99 // ESP32-S2 has 1 GPIO peripheral 100 #define SOC_GPIO_PORT (1) 101 #define SOC_GPIO_PIN_COUNT (47) 102 103 // On ESP32-S2 those PADs which have RTC functions must set pullup/down/capability via RTC register. 104 // On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. 105 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) 106 // Force hold is a new function of ESP32-S2 107 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) 108 109 // 0~46 except from 22~25 are valid 110 #define SOC_GPIO_VALID_GPIO_MASK (0x7FFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) 111 // GPIO 46 is input only 112 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46)) 113 114 // Support to configure slept status 115 #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) 116 117 /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ 118 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ 119 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ 120 #define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */ 121 #define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */ 122 #define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */ 123 124 /*-------------------------- I2C CAPS ----------------------------------------*/ 125 // ESP32-S2 have 2 I2C. 126 #define SOC_I2C_NUM (2) 127 128 #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ 129 130 //ESP32-S2 support hardware FSM reset 131 #define SOC_I2C_SUPPORT_HW_FSM_RST (1) 132 //ESP32-S2 support hardware clear bus 133 #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) 134 135 #define SOC_I2C_SUPPORT_REF_TICK (1) 136 #define SOC_I2C_SUPPORT_APB (1) 137 138 /*-------------------------- APLL CAPS ----------------------------------------*/ 139 #define SOC_CLK_APLL_SUPPORTED (1) 140 // apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536) 141 #define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz 142 #define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz 143 #define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz 144 #define SOC_APLL_MAX_HZ (125000000) // 125MHz 145 146 /*-------------------------- I2S CAPS ----------------------------------------*/ 147 // ESP32-S2 have 1 I2S 148 #define SOC_I2S_NUM (1) 149 #define SOC_I2S_SUPPORTS_APLL (1)// ESP32-S2 support APLL 150 #define SOC_I2S_SUPPORTS_DMA_EQUAL (1) 151 #define SOC_I2S_LCD_I80_VARIANT (1) 152 153 /*-------------------------- LCD CAPS ----------------------------------------*/ 154 /* Notes: On esp32-s2, LCD intel 8080 timing is generated by I2S peripheral */ 155 #define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */ 156 #define SOC_LCD_I80_BUSES (1) /*!< Only I2S0 has LCD mode */ 157 #define SOC_LCD_I80_BUS_WIDTH (24) /*!< Intel 8080 bus width */ 158 159 /*-------------------------- LEDC CAPS ---------------------------------------*/ 160 #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) 161 #define SOC_LEDC_CHANNEL_NUM (8) 162 #define SOC_LEDC_TIMER_BIT_WIDE_NUM (14) 163 164 /*-------------------------- MPU CAPS ----------------------------------------*/ 165 //TODO: correct the caller and remove unsupported lines 166 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 167 #define SOC_MPU_MIN_REGION_SIZE 0x20000000U 168 #define SOC_MPU_REGIONS_MAX_NUM 8 169 #define SOC_MPU_REGION_RO_SUPPORTED 0 170 #define SOC_MPU_REGION_WO_SUPPORTED 0 171 172 /*-------------------------- PCNT CAPS ---------------------------------------*/ 173 #define SOC_PCNT_GROUPS (1) 174 #define SOC_PCNT_UNITS_PER_GROUP (4) 175 #define SOC_PCNT_CHANNELS_PER_UNIT (2) 176 #define SOC_PCNT_THRES_POINT_PER_UNIT (2) 177 178 /*-------------------------- RMT CAPS ----------------------------------------*/ 179 #define SOC_RMT_GROUPS (1) /*!< One RMT group */ 180 #define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */ 181 #define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */ 182 #define SOC_RMT_CHANNELS_PER_GROUP (4) /*!< Total 4 channels */ 183 #define SOC_RMT_MEM_WORDS_PER_CHANNEL (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ 184 #define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ 185 #define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmiting specified number of cycles in loop mode */ 186 #define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ 187 #define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ 188 #define SOC_RMT_CHANNEL_CLK_INDEPENDENT (1) /*!< Can select different source clock for each channel */ 189 190 /*-------------------------- RTCIO CAPS --------------------------------------*/ 191 #define SOC_RTCIO_PIN_COUNT 22 192 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 193 #define SOC_RTCIO_HOLD_SUPPORTED 1 194 #define SOC_RTCIO_WAKE_SUPPORTED 1 195 196 197 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ 198 #define SOC_SIGMADELTA_NUM 1 199 #define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels 200 201 /*-------------------------- SPI CAPS ----------------------------------------*/ 202 #define SOC_SPI_PERIPH_NUM 3 203 #define SOC_SPI_DMA_CHAN_NUM 3 204 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) 205 206 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 207 #define SOC_SPI_MAX_PRE_DIVIDER 8192 208 209 //#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles 210 #define SOC_SPI_SUPPORT_DDRCLK 1 211 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 212 #define SOC_SPI_SUPPORT_CD_SIG 1 213 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 214 /// The SPI Slave half duplex mode has been updated greatly in ESP32-S2 215 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 216 217 // Peripheral supports DIO, DOUT, QIO, or QOUT 218 // VSPI (SPI3) only support 1-bit mode 219 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) 220 221 // Peripheral supports output given level during its "dummy phase" 222 // Only SPI1 supports this feature 223 #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 224 225 #define SOC_MEMSPI_IS_INDEPENDENT 1 226 #define SOC_SPI_SUPPORT_OCT 1 227 228 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ 229 #define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units 230 #define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units 231 #define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part 232 #define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part 233 234 /*-------------------------- TIMER GROUP CAPS --------------------------------*/ 235 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64) 236 #define SOC_TIMER_GROUPS (2) 237 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) 238 #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) 239 #define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) 240 241 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ 242 #define SOC_TOUCH_VERSION_2 (1) /*!<Hardware version of touch sensor */ 243 #define SOC_TOUCH_SENSOR_NUM (15) /*!<15 Touch channels */ 244 #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */ 245 246 #define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!<If set touch threshold max value, The touch sensor can't be in touched status */ 247 #define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */ 248 249 /*-------------------------- TWAI CAPS ---------------------------------------*/ 250 #define SOC_TWAI_BRP_MIN 2 251 #define SOC_TWAI_BRP_MAX 32768 252 #define SOC_TWAI_SUPPORTS_RX_STATUS 1 253 254 /*-------------------------- UART CAPS ---------------------------------------*/ 255 // ESP32-S2 has 2 UART. 256 #define SOC_UART_NUM (2) 257 #define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */ 258 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ 259 #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ 260 261 /*-------------------------- SPIRAM CAPS -------------------------------------*/ 262 #define SOC_SPIRAM_SUPPORTED 1 263 264 /*-------------------------- USB CAPS ----------------------------------------*/ 265 #define SOC_USB_PERIPH_NUM 1 266 267 268 /*--------------------------- SHA CAPS ---------------------------------------*/ 269 /* Max amount of bytes in a single DMA operation is 4095, 270 for SHA this means that the biggest safe amount of bytes is 271 31 blocks of 128 bytes = 3968 272 */ 273 #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) 274 #define SOC_SHA_SUPPORT_DMA (1) 275 276 /* The SHA engine is able to resume hashing from a user supplied context */ 277 #define SOC_SHA_SUPPORT_RESUME (1) 278 279 /* Has "crypto DMA", which is shared with AES */ 280 #define SOC_SHA_CRYPTO_DMA (1) 281 282 /* Supported HW algorithms */ 283 #define SOC_SHA_SUPPORT_SHA1 (1) 284 #define SOC_SHA_SUPPORT_SHA224 (1) 285 #define SOC_SHA_SUPPORT_SHA256 (1) 286 #define SOC_SHA_SUPPORT_SHA384 (1) 287 #define SOC_SHA_SUPPORT_SHA256 (1) 288 #define SOC_SHA_SUPPORT_SHA512 (1) 289 #define SOC_SHA_SUPPORT_SHA512_224 (1) 290 #define SOC_SHA_SUPPORT_SHA512_256 (1) 291 #define SOC_SHA_SUPPORT_SHA512_T (1) 292 293 /* Supported HW algorithms */ 294 #define SOC_SHA_SUPPORT_SHA1 (1) 295 #define SOC_SHA_SUPPORT_SHA256 (1) 296 #define SOC_SHA_SUPPORT_SHA384 (1) 297 #define SOC_SHA_SUPPORT_SHA512 (1) 298 299 300 /*--------------------------- RSA CAPS ---------------------------------------*/ 301 #define SOC_RSA_MAX_BIT_LEN (4096) 302 303 304 /*-------------------------- AES CAPS -----------------------------------------*/ 305 #define SOC_AES_SUPPORT_DMA (1) 306 #define SOC_AES_SUPPORT_GCM (1) 307 308 /*-------------------------- Flash Encryption CAPS----------------------------*/ 309 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) 310 311 /* Has "crypto DMA", which is shared with SHA */ 312 #define SOC_AES_CRYPTO_DMA (1) 313 314 #define SOC_AES_SUPPORT_AES_128 (1) 315 #define SOC_AES_SUPPORT_AES_192 (1) 316 #define SOC_AES_SUPPORT_AES_256 (1) 317 318 /*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/ 319 #define SOC_WIFI_HW_TSF (1) 320 321 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 322 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 323 324 /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ 325 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) 326 327 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ 328 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) 329 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) 330 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) 331 /*-------------------------- Power Management CAPS ---------------------------*/ 332 #define SOC_PM_SUPPORT_EXT_WAKEUP (1) 333 334 #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) 335 336 #define SOC_PM_SUPPORT_WIFI_PD (1) 337 338 #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */ 339 340 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ 341 #define SOC_COEX_HW_PTI (1) 342 /* ---------------------------- Compatibility ------------------------------- */ 343 // No contents 344
