1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 /* 16 * Soc capabilities file, describing the following chip attributes: 17 * - Peripheral or feature supported or not 18 * - Number of resources (peripheral, channel, etc.) 19 * - Maximum / Minimum value of HW, including: buffer/fifo size, length of transaction, frequency 20 * supported, etc. 21 * 22 * For boolean definitions: 23 * - if true: `#define MODULE_[SUBMODULE_]SUPPORT_FEATURE 1`. 24 * (`#define` blank string causes error when checking by `#if x`) 25 * - if false: not define anything at all. 26 * (`#ifdef x` is true even when `#define 0` is defined before.) 27 * 28 * The code depending on this file uses these boolean definitions as `#if x` or `#if !x`. 29 * (`#ifdef/ifndef x` is not compatible with `#define x 0`. Though we don't suggest to use `#define 30 * x 0`, it's still a risk.) 31 * 32 * ECO & exceptions: 33 * For ECO-ed booleans, `#define x "Not determined"` for them. This will cause error when used by 34 * `#if x` and `#if !x`, making these missing definitions more obvious. 35 */ 36 37 #pragma once 38 39 /*-------------------------- COMMON CAPS ---------------------------------------*/ 40 #define SOC_TWAI_SUPPORTED 1 41 #define SOC_CP_DMA_SUPPORTED 1 42 #define SOC_CPU_CORES_NUM 1 43 #define SOC_DEDICATED_GPIO_SUPPORTED 1 44 #define SOC_SUPPORTS_SECURE_DL_MODE 1 45 #define SOC_RISCV_COPROC_SUPPORTED 1 46 #define SOC_USB_SUPPORTED 1 47 #define SOC_PCNT_SUPPORTED 1 48 #define SOC_ULP_SUPPORTED 1 49 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 50 #define SOC_CCOMP_TIMER_SUPPORTED 1 51 #define SOC_DIG_SIGN_SUPPORTED 1 52 #define SOC_HMAC_SUPPORTED 1 53 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 54 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 55 56 #define SOC_CACHE_SUPPORT_WRAP 1 57 58 /*-------------------------- ADC CAPS ----------------------------------------*/ 59 #define SOC_ADC_PERIPH_NUM (2) 60 #define SOC_ADC_PATT_LEN_MAX (16) 61 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) 62 #define SOC_ADC_MAX_CHANNEL_NUM (10) 63 #define SOC_ADC_MAX_BITWIDTH (13) 64 #define SOC_ADC_HW_CALIBRATION_V1 (1) /*!< support HW offset calibration */ 65 66 67 /** 68 * Check if adc support digital controller (DMA) mode. 69 * @value 70 * - 1 : support; 71 * - 0 : not support; 72 */ 73 #define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1) 74 #define SOC_ADC_SUPPORT_RTC_CTRL 1 75 76 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 77 #define SOC_BROWNOUT_RESET_SUPPORTED 1 78 79 /*-------------------------- CP-DMA CAPS -------------------------------------*/ 80 #define SOC_CP_DMA_MAX_BUFFER_SIZE (4095) /*!< Maximum size of the buffer that can be attached to descriptor */ 81 82 /*-------------------------- CPU CAPS ----------------------------------------*/ 83 #define SOC_CPU_BREAKPOINTS_NUM 2 84 #define SOC_CPU_WATCHPOINTS_NUM 2 85 86 #define SOC_CPU_WATCHPOINT_SIZE 64 // bytes 87 88 /*-------------------------- DAC CAPS ----------------------------------------*/ 89 #define SOC_DAC_PERIPH_NUM 2 90 91 #define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit 92 93 /*-------------------------- GPIO CAPS ---------------------------------------*/ 94 // ESP32-S2 has 1 GPIO peripheral 95 #define SOC_GPIO_PORT (1) 96 #define SOC_GPIO_PIN_COUNT (48) 97 98 // On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. 99 // On ESP32-S2, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. 100 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) 101 // Force hold is a new function of ESP32-S2 102 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) 103 104 // 0~47 except from 22~25, 47 are valid 105 #define SOC_GPIO_VALID_GPIO_MASK (0xFFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25 | BIT47)) 106 // GPIO 46, 47 are input only 107 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK & ~(0ULL | BIT46 | BIT47)) 108 109 // Support to configure slept status 110 #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) 111 112 /*-------------------------- Dedicated GPIO CAPS ---------------------------------------*/ 113 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ 114 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ 115 #define SOC_DEDIC_GPIO_ALLOW_REG_ACCESS (1) /*!< Allow access dedicated GPIO channel by register */ 116 #define SOC_DEDIC_GPIO_HAS_INTERRUPT (1) /*!< Dedicated GPIO has its own interrupt source */ 117 118 /*-------------------------- I2C CAPS ----------------------------------------*/ 119 // ESP32-S2 have 2 I2C. 120 #define SOC_I2C_NUM (2) 121 122 #define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ 123 124 //ESP32-S2 support hardware FSM reset 125 #define SOC_I2C_SUPPORT_HW_FSM_RST (1) 126 //ESP32-S2 support hardware clear bus 127 #define SOC_I2C_SUPPORT_HW_CLR_BUS (1) 128 129 #define SOC_I2C_SUPPORT_REF_TICK (1) 130 #define SOC_I2C_SUPPORT_APB (1) 131 132 /*-------------------------- I2S CAPS ----------------------------------------*/ 133 // ESP32-S2 have 2 I2S 134 #define SOC_I2S_NUM (1) 135 136 #define SOC_I2S_SUPPORTS_DMA_EQUAL (1) // ESP32-S2 need dma equal 137 138 #define SOC_I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated 139 140 #define SOC_I2S_APLL_MIN_FREQ (250000000) 141 #define SOC_I2S_APLL_MAX_FREQ (500000000) 142 #define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware 143 144 /*-------------------------- LEDC CAPS ---------------------------------------*/ 145 #define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) 146 #define SOC_LEDC_CHANNEL_NUM (8) 147 #define SOC_LEDC_TIMER_BIT_WIDE_NUM (14) 148 149 /*-------------------------- MPU CAPS ----------------------------------------*/ 150 //TODO: correct the caller and remove unsupported lines 151 #define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 152 #define SOC_MPU_MIN_REGION_SIZE 0x20000000 153 #define SOC_MPU_REGIONS_MAX_NUM 8 154 #define SOC_MPU_REGION_RO_SUPPORTED 0 155 #define SOC_MPU_REGION_WO_SUPPORTED 0 156 157 /*-------------------------- PCNT CAPS ---------------------------------------*/ 158 // ESP32-S2 have 1 PCNT peripheral 159 #define SOC_PCNT_PORT_NUM (1) 160 #define SOC_PCNT_UNIT_NUM (4) // ESP32-S2 only have 4 unit 161 #define SOC_PCNT_UNIT_CHANNEL_NUM (2) 162 163 /*-------------------------- RMT CAPS ----------------------------------------*/ 164 #define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ 165 #define SOC_RMT_TX_CHANNELS_NUM (4) /*!< Number of channels that capable of Transmit */ 166 #define SOC_RMT_RX_CHANNELS_NUM (4) /*!< Number of channels that capable of Receive */ 167 #define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels (each channel can be configured to either TX or RX) */ 168 #define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ 169 #define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ 170 #define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ 171 #define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ 172 #define SOC_RMT_SUPPORT_REF_TICK (1) /*!< Support set REF_TICK as the RMT clock source */ 173 #define SOC_RMT_SOURCE_CLK_INDEPENDENT (1) /*!< Can select different source clock for channels */ 174 175 /*-------------------------- RTCIO CAPS --------------------------------------*/ 176 #define SOC_RTCIO_PIN_COUNT 22 177 #define SOC_RTCIO_INPUT_OUTPUT_SUPPORTED 1 178 #define SOC_RTCIO_HOLD_SUPPORTED 1 179 #define SOC_RTCIO_WAKE_SUPPORTED 1 180 181 182 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ 183 #define SOC_SIGMADELTA_NUM 1 184 #define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels 185 186 /*-------------------------- SPI CAPS ----------------------------------------*/ 187 #define SOC_SPI_PERIPH_NUM 3 188 #define SOC_SPI_DMA_CHAN_NUM 3 189 #define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3)) 190 191 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 192 #define SOC_SPI_MAX_PRE_DIVIDER 8192 193 194 //#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles 195 #define SOC_SPI_SUPPORT_DDRCLK 1 196 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 197 #define SOC_SPI_SUPPORT_CD_SIG 1 198 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 199 /// The SPI Slave half duplex mode has been updated greatly in ESP32-S2 200 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 201 202 // Peripheral supports DIO, DOUT, QIO, or QOUT 203 // VSPI (SPI3) only support 1-bit mode 204 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ((host_id) != 2) 205 206 // Peripheral supports output given level during its "dummy phase" 207 // Only SPI1 supports this feature 208 #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 209 210 #define SOC_MEMSPI_IS_INDEPENDENT 1 211 212 /*-------------------------- SYS TIMER CAPS ----------------------------------*/ 213 #define SOC_SYSTIMER_COUNTER_NUM (1) // Number of counter units 214 #define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units 215 216 #define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part 217 #define SOC_SYSTIMER_BIT_WIDTH_HI (32) // Bit width of systimer high part 218 219 /*-------------------------- TIMER GROUP CAPS --------------------------------*/ 220 #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) 221 #define SOC_TIMER_GROUP_XTAL_MHZ (40) 222 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (64) 223 #define SOC_TIMER_GROUP_PRESCALE_BIT_WIDTH (16) 224 #define SOC_TIMER_GROUPS (2) 225 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) 226 #define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) 227 #define SOC_TIMER_GROUP_LAYOUT {2,2} 228 229 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ 230 #define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */ 231 #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */ 232 233 #define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!<If set touch threshold max value, The touch sensor can't be in touched status */ 234 #define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */ 235 #define SOC_TOUCH_PAD_WAKE_SUPPORTED (1) /*!<Supports waking up from touch pad trigger */ 236 237 /*-------------------------- TWAI CAPS ---------------------------------------*/ 238 #define SOC_TWAI_BRP_MIN 2 239 #define SOC_TWAI_BRP_MAX 32768 240 #define SOC_TWAI_SUPPORTS_RX_STATUS 1 241 242 /*-------------------------- UART CAPS ---------------------------------------*/ 243 // ESP32-S2 have 2 UART. 244 #define SOC_UART_NUM (2) 245 #define SOC_UART_SUPPORT_REF_TICK (1) /*!< Support REF_TICK as the clock source */ 246 #define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ 247 #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ 248 249 /*-------------------------- SPIRAM CAPS -------------------------------------*/ 250 #define SOC_SPIRAM_SUPPORTED 1 251 252 /*-------------------------- USB CAPS ----------------------------------------*/ 253 #define SOC_USB_PERIPH_NUM 1 254 255 256 /*--------------------------- SHA CAPS ---------------------------------------*/ 257 /* Max amount of bytes in a single DMA operation is 4095, 258 for SHA this means that the biggest safe amount of bytes is 259 31 blocks of 128 bytes = 3968 260 */ 261 #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) 262 #define SOC_SHA_SUPPORT_DMA (1) 263 264 /* The SHA engine is able to resume hashing from a user supplied context */ 265 #define SOC_SHA_SUPPORT_RESUME (1) 266 267 /* Has "crypto DMA", which is shared with AES */ 268 #define SOC_SHA_CRYPTO_DMA (1) 269 270 /* Supported HW algorithms */ 271 #define SOC_SHA_SUPPORT_SHA1 (1) 272 #define SOC_SHA_SUPPORT_SHA224 (1) 273 #define SOC_SHA_SUPPORT_SHA256 (1) 274 #define SOC_SHA_SUPPORT_SHA384 (1) 275 #define SOC_SHA_SUPPORT_SHA256 (1) 276 #define SOC_SHA_SUPPORT_SHA512 (1) 277 #define SOC_SHA_SUPPORT_SHA512_224 (1) 278 #define SOC_SHA_SUPPORT_SHA512_256 (1) 279 #define SOC_SHA_SUPPORT_SHA512_T (1) 280 281 /* Supported HW algorithms */ 282 #define SOC_SHA_SUPPORT_SHA1 (1) 283 #define SOC_SHA_SUPPORT_SHA256 (1) 284 #define SOC_SHA_SUPPORT_SHA384 (1) 285 #define SOC_SHA_SUPPORT_SHA512 (1) 286 287 288 /*--------------------------- RSA CAPS ---------------------------------------*/ 289 #define SOC_RSA_MAX_BIT_LEN (4096) 290 291 292 /*-------------------------- AES CAPS -----------------------------------------*/ 293 #define SOC_AES_SUPPORT_DMA (1) 294 #define SOC_AES_SUPPORT_GCM (1) 295 296 /* Has "crypto DMA", which is shared with SHA */ 297 #define SOC_AES_CRYPTO_DMA (1) 298 299 #define SOC_AES_SUPPORT_AES_128 (1) 300 #define SOC_AES_SUPPORT_AES_192 (1) 301 #define SOC_AES_SUPPORT_AES_256 (1) 302 303 /*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/ 304 #define SOC_WIFI_HW_TSF (1) 305 306 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 307 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 308 309 /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ 310 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) 311 312 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ 313 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) 314 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) 315 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) 316 /*-------------------------- Power Management CAPS ---------------------------*/ 317 #define SOC_PM_SUPPORT_EXT_WAKEUP (1) 318 319 #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) 320 321 #define SOC_PM_SUPPORT_WIFI_PD (1) 322 323 /* ---------------------------- Compatibility ------------------------------- */ 324 // No contents 325
