1 /* 2 * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #ifndef __ASSEMBLER__ 10 #include <stdint.h> 11 #include "esp_assert.h" 12 #include "soc/soc_caps.h" 13 #endif 14 15 #include "esp_bit_defs.h" 16 #include "reg_base.h" 17 18 #define PRO_CPU_NUM (0) 19 #define APP_CPU_NUM (1) 20 21 22 #define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space 23 24 //Registers Operation {{ 25 #define ETS_UNCACHED_ADDR(addr) (addr) 26 #define ETS_CACHED_ADDR(addr) (addr) 27 28 29 #ifndef __ASSEMBLER__ 30 31 #define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END) 32 33 #if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && SOC_DPORT_WORKAROUND 34 #define ASSERT_IF_DPORT_REG(_r, OP) TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP)); 35 #else 36 #define ASSERT_IF_DPORT_REG(_r, OP) 37 #endif 38 39 //write value to register 40 #define REG_WRITE(_r, _v) do { \ 41 ASSERT_IF_DPORT_REG((_r), REG_WRITE); \ 42 (*(volatile uint32_t *)(_r)) = (_v); \ 43 } while(0) 44 45 //read value from register 46 #define REG_READ(_r) ({ \ 47 ASSERT_IF_DPORT_REG((_r), REG_READ); \ 48 (*(volatile uint32_t *)(_r)); \ 49 }) 50 51 //get bit or get bits from register 52 #define REG_GET_BIT(_r, _b) ({ \ 53 ASSERT_IF_DPORT_REG((_r), REG_GET_BIT); \ 54 (*(volatile uint32_t*)(_r) & (_b)); \ 55 }) 56 57 //set bit or set bits to register 58 #define REG_SET_BIT(_r, _b) do { \ 59 ASSERT_IF_DPORT_REG((_r), REG_SET_BIT); \ 60 *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) | (_b); \ 61 } while(0) 62 63 //clear bit or clear bits of register 64 #define REG_CLR_BIT(_r, _b) do { \ 65 ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT); \ 66 *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r)) & (~(_b)); \ 67 } while(0) 68 69 //set bits of register controlled by mask 70 #define REG_SET_BITS(_r, _b, _m) do { \ 71 ASSERT_IF_DPORT_REG((_r), REG_SET_BITS); \ 72 *(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)); \ 73 } while(0) 74 75 //get field from register, uses field _S & _V to determine mask 76 #define REG_GET_FIELD(_r, _f) ({ \ 77 ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD); \ 78 ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ 79 }) 80 81 //set field of a register from variable, uses field _S & _V to determine mask 82 #define REG_SET_FIELD(_r, _f, _v) do { \ 83 ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD); \ 84 REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))); \ 85 } while(0) 86 87 //get field value from a variable, used when _f is not left shifted by _f##_S 88 #define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) 89 90 //get field value from a variable, used when _f is left shifted by _f##_S 91 #define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) 92 93 //set field value to a variable, used when _f is not left shifted by _f##_S 94 #define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) 95 96 //set field value to a variable, used when _f is left shifted by _f##_S 97 #define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) 98 99 //generate a value from a field value, used when _f is not left shifted by _f##_S 100 #define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) 101 102 //generate a value from a field value, used when _f is left shifted by _f##_S 103 #define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) 104 105 //read value from register 106 #define READ_PERI_REG(addr) ({ \ 107 ASSERT_IF_DPORT_REG((addr), READ_PERI_REG); \ 108 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ 109 }) 110 111 //write value to register 112 #define WRITE_PERI_REG(addr, val) do { \ 113 ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); \ 114 (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ 115 } while(0) 116 117 //clear bits of register controlled by mask 118 #define CLEAR_PERI_REG_MASK(reg, mask) do { \ 119 ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK); \ 120 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ 121 } while(0) 122 123 //set bits of register controlled by mask 124 #define SET_PERI_REG_MASK(reg, mask) do { \ 125 ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK); \ 126 WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ 127 } while(0) 128 129 //get bits of register controlled by mask 130 #define GET_PERI_REG_MASK(reg, mask) ({ \ 131 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK); \ 132 (READ_PERI_REG(reg) & (mask)); \ 133 }) 134 135 //get bits of register controlled by highest bit and lowest bit 136 #define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ 137 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS); \ 138 ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ 139 }) 140 141 //set bits of register controlled by mask and shift 142 #define SET_PERI_REG_BITS(reg,bit_map,value,shift) do { \ 143 ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS); \ 144 WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift)) ); \ 145 } while(0) 146 147 //get field of register 148 #define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ 149 ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2); \ 150 ((READ_PERI_REG(reg)>>(shift))&(mask)); \ 151 }) 152 153 #endif /* !__ASSEMBLER__ */ 154 //}} 155 156 //Periheral Clock {{ 157 #define APB_CLK_FREQ_ROM ( 26*1000000 ) 158 #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM 159 #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration 160 #define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP_DEFAULT_CPU_FREQ_MHZ 161 #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz 162 #define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) 163 #define REF_CLK_FREQ ( 1000000 ) 164 #define UART_CLK_FREQ APB_CLK_FREQ 165 #define WDT_CLK_FREQ APB_CLK_FREQ 166 #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 16 167 #define SPI_CLK_DIV 4 168 #define TICKS_PER_US_ROM 26 // CPU is 80MHz 169 #define GPIO_MATRIX_DELAY_NS 25 170 //}} 171 172 /* Overall memory map */ 173 #define SOC_DROM_LOW 0x3F400000 174 #define SOC_DROM_HIGH 0x3F800000 175 #define SOC_DRAM_LOW 0x3FFAE000 176 #define SOC_DRAM_HIGH 0x40000000 177 #define SOC_IROM_LOW 0x400D0000 178 #define SOC_IROM_HIGH 0x40400000 179 #define SOC_IROM_MASK_LOW 0x40000000 180 #define SOC_IROM_MASK_HIGH 0x40064F00 181 #define SOC_CACHE_PRO_LOW 0x40070000 182 #define SOC_CACHE_PRO_HIGH 0x40078000 183 #define SOC_CACHE_APP_LOW 0x40078000 184 #define SOC_CACHE_APP_HIGH 0x40080000 185 #define SOC_IRAM_LOW 0x40080000 186 #define SOC_IRAM_HIGH 0x400AA000 187 #define SOC_RTC_IRAM_LOW 0x400C0000 188 #define SOC_RTC_IRAM_HIGH 0x400C2000 189 #define SOC_RTC_DRAM_LOW 0x3FF80000 190 #define SOC_RTC_DRAM_HIGH 0x3FF82000 191 #define SOC_RTC_DATA_LOW 0x50000000 192 #define SOC_RTC_DATA_HIGH 0x50002000 193 #define SOC_EXTRAM_DATA_LOW 0x3F800000 194 #define SOC_EXTRAM_DATA_HIGH 0x3FC00000 195 196 #define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) 197 198 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. 199 #define SOC_DIRAM_IRAM_LOW 0x400A0000 200 #define SOC_DIRAM_IRAM_HIGH 0x400C0000 201 #define SOC_DIRAM_DRAM_LOW 0x3FFE0000 202 #define SOC_DIRAM_DRAM_HIGH 0x40000000 203 // Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM 204 #define SOC_DIRAM_INVERTED 1 205 206 // Region of memory accessible via DMA. See esp_ptr_dma_capable(). 207 #define SOC_DMA_LOW 0x3FFAE000 208 #define SOC_DMA_HIGH 0x40000000 209 210 // Region of memory that is byte-accessible. See esp_ptr_byte_accessible(). 211 #define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000 212 #define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000 213 214 //Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs 215 //(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). 216 #define SOC_MEM_INTERNAL_LOW 0x3FF90000 217 #define SOC_MEM_INTERNAL_HIGH 0x400C2000 218 219 // Start (highest address) of ROM boot stack, only relevant during early boot 220 #define SOC_ROM_STACK_START 0x3ffe3f20 221 222 //Interrupt hardware source table 223 //This table is decided by hardware, don't touch this. 224 #define ETS_WIFI_MAC_INTR_SOURCE 0/**< interrupt of WiFi MAC, level*/ 225 #define ETS_WIFI_MAC_NMI_SOURCE 1/**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ 226 #define ETS_WIFI_BB_INTR_SOURCE 2/**< interrupt of WiFi BB, level, we can do some calibartion*/ 227 #define ETS_BT_MAC_INTR_SOURCE 3/**< will be cancelled*/ 228 #define ETS_BT_BB_INTR_SOURCE 4/**< interrupt of BT BB, level*/ 229 #define ETS_BT_BB_NMI_SOURCE 5/**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ 230 #define ETS_RWBT_INTR_SOURCE 6/**< interrupt of RWBT, level*/ 231 #define ETS_RWBLE_INTR_SOURCE 7/**< interrupt of RWBLE, level*/ 232 #define ETS_RWBT_NMI_SOURCE 8/**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ 233 #define ETS_RWBLE_NMI_SOURCE 9/**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ 234 #define ETS_SLC0_INTR_SOURCE 10/**< interrupt of SLC0, level*/ 235 #define ETS_SLC1_INTR_SOURCE 11/**< interrupt of SLC1, level*/ 236 #define ETS_UHCI0_INTR_SOURCE 12/**< interrupt of UHCI0, level*/ 237 #define ETS_UHCI1_INTR_SOURCE 13/**< interrupt of UHCI1, level*/ 238 #define ETS_TG0_T0_LEVEL_INTR_SOURCE 14/**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ 239 #define ETS_TG0_T1_LEVEL_INTR_SOURCE 15/**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ 240 #define ETS_TG0_WDT_LEVEL_INTR_SOURCE 16/**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ 241 #define ETS_TG0_LACT_LEVEL_INTR_SOURCE 17/**< interrupt of TIMER_GROUP0, LACT, level*/ 242 #define ETS_TG1_T0_LEVEL_INTR_SOURCE 18/**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ 243 #define ETS_TG1_T1_LEVEL_INTR_SOURCE 19/**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ 244 #define ETS_TG1_WDT_LEVEL_INTR_SOURCE 20/**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ 245 #define ETS_TG1_LACT_LEVEL_INTR_SOURCE 21/**< interrupt of TIMER_GROUP1, LACT, level*/ 246 #define ETS_GPIO_INTR_SOURCE 22/**< interrupt of GPIO, level*/ 247 #define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/ 248 #define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ 249 #define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ 250 #define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */ 251 #define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */ 252 #define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/ 253 #define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ 254 #define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/ 255 #define ETS_SPI3_INTR_SOURCE 31/**< interrupt of SPI3, level*/ 256 #define ETS_I2S0_INTR_SOURCE 32/**< interrupt of I2S0, level*/ 257 #define ETS_I2S1_INTR_SOURCE 33/**< interrupt of I2S1, level*/ 258 #define ETS_UART0_INTR_SOURCE 34/**< interrupt of UART0, level*/ 259 #define ETS_UART1_INTR_SOURCE 35/**< interrupt of UART1, level*/ 260 #define ETS_UART2_INTR_SOURCE 36/**< interrupt of UART2, level*/ 261 #define ETS_SDIO_HOST_INTR_SOURCE 37/**< interrupt of SD/SDIO/MMC HOST, level*/ 262 #define ETS_ETH_MAC_INTR_SOURCE 38/**< interrupt of ethernet mac, level*/ 263 #define ETS_PWM0_INTR_SOURCE 39/**< interrupt of PWM0, level, Reserved*/ 264 #define ETS_PWM1_INTR_SOURCE 40/**< interrupt of PWM1, level, Reserved*/ 265 #define ETS_LEDC_INTR_SOURCE 43/**< interrupt of LED PWM, level*/ 266 #define ETS_EFUSE_INTR_SOURCE 44/**< interrupt of efuse, level, not likely to use*/ 267 #define ETS_TWAI_INTR_SOURCE 45/**< interrupt of twai, level*/ 268 #define ETS_CAN_INTR_SOURCE ETS_TWAI_INTR_SOURCE 269 #define ETS_RTC_CORE_INTR_SOURCE 46/**< interrupt of rtc core, level, include rtc watchdog*/ 270 #define ETS_RMT_INTR_SOURCE 47/**< interrupt of remote controller, level*/ 271 #define ETS_PCNT_INTR_SOURCE 48/**< interrupt of pluse count, level*/ 272 #define ETS_I2C_EXT0_INTR_SOURCE 49/**< interrupt of I2C controller1, level*/ 273 #define ETS_I2C_EXT1_INTR_SOURCE 50/**< interrupt of I2C controller0, level*/ 274 #define ETS_RSA_INTR_SOURCE 51/**< interrupt of RSA accelerator, level*/ 275 #define ETS_SPI1_DMA_INTR_SOURCE 52/**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/ 276 #define ETS_SPI2_DMA_INTR_SOURCE 53/**< interrupt of SPI2 DMA, level*/ 277 #define ETS_SPI3_DMA_INTR_SOURCE 54/**< interrupt of SPI3 DMA, level*/ 278 #define ETS_WDT_INTR_SOURCE 55/**< will be cancelled*/ 279 #define ETS_TIMER1_INTR_SOURCE 56/**< will be cancelled*/ 280 #define ETS_TIMER2_INTR_SOURCE 57/**< will be cancelled*/ 281 #define ETS_TG0_T0_EDGE_INTR_SOURCE 58/**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ 282 #define ETS_TG0_T1_EDGE_INTR_SOURCE 59/**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ 283 #define ETS_TG0_WDT_EDGE_INTR_SOURCE 60/**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ 284 #define ETS_TG0_LACT_EDGE_INTR_SOURCE 61/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 285 #define ETS_TG1_T0_EDGE_INTR_SOURCE 62/**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ 286 #define ETS_TG1_T1_EDGE_INTR_SOURCE 63/**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ 287 #define ETS_TG1_WDT_EDGE_INTR_SOURCE 64/**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ 288 #define ETS_TG1_LACT_EDGE_INTR_SOURCE 65/**< interrupt of TIMER_GROUP0, LACT, EDGE*/ 289 #define ETS_MMU_IA_INTR_SOURCE 66/**< interrupt of MMU Invalid Access, LEVEL*/ 290 #define ETS_MPU_IA_INTR_SOURCE 67/**< interrupt of MPU Invalid Access, LEVEL*/ 291 #define ETS_CACHE_IA_INTR_SOURCE 68/**< interrupt of Cache Invalied Access, LEVEL*/ 292 #define ETS_MAX_INTR_SOURCE 69/**< total number of interrupt sources*/ 293 294 #if CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 295 //interrupt cpu using table, Please see the core-isa.h 296 /************************************************************************************************************* 297 * Intr num Level Type PRO CPU usage APP CPU uasge 298 * 0 1 extern level WMAC Reserved 299 * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA 300 * 2 1 extern level 301 * 3 1 extern level 302 * 4 1 extern level WBB 303 * 5 1 extern level 304 * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) 305 * 7 1 software BT/BLE VHCI BT/BLE VHCI 306 * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) 307 * 9 1 extern level 308 * 10 1 extern edge 309 * 11 3 profiling 310 * 12 1 extern level 311 * 13 1 extern level 312 * 14 7 nmi Reserved Reserved 313 * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) 314 * 16 5 timer Reserved Reserved 315 * 17 1 extern level 316 * 18 1 extern level 317 * 19 2 extern level 318 * 20 2 extern level 319 * 21 2 extern level 320 * 22 3 extern edge 321 * 23 3 extern level 322 * 24 4 extern level 323 * 25 4 extern level BT/BLE Controller BT/BLE Controller 324 * 26 5 extern level TG1_WDT & CACHEERR 325 * 27 3 extern level Reserved Reserved 326 * 28 4 extern edge 327 * 29 3 software BT/BLE hli BT/BLE hli 328 * 30 4 extern edge Reserved Reserved 329 * 31 5 extern level IPC_ISR IPC_ISR 330 ************************************************************************************************************* 331 */ 332 333 //CPU0 Interrupt number reserved, not touch this. 334 #define ETS_WMAC_INUM 0 335 #define ETS_BT_HOST_INUM 1 336 #define ETS_WBB_INUM 4 337 #define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ 338 #define ETS_FRC1_INUM 22 339 #define ETS_T1_WDT_CACHEERR_INUM 26 340 #define ETS_T1_WDT_INUM ETS_T1_WDT_CACHEERR_INUM 341 #define ETS_MEMACCESS_ERR_INUM ETS_T1_WDT_CACHEERR_INUM 342 /* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/ 343 #define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM 344 #define ETS_IPC_ISR_INUM 31 345 346 #elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 347 348 //interrupt cpu using table, Please see the core-isa.h 349 /************************************************************************************************************* 350 * Intr num Level Type PRO CPU usage APP CPU uasge 351 * 0 1 extern level WMAC Reserved 352 * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA 353 * 2 1 extern level 354 * 3 1 extern level 355 * 4 1 extern level WBB 356 * 5 1 extern level BT/BLE Controller BT/BLE Controller 357 * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) 358 * 7 1 software BT/BLE VHCI BT/BLE VHCI 359 * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) 360 * 9 1 extern level 361 * 10 1 extern edge 362 * 11 3 profiling 363 * 12 1 extern level 364 * 13 1 extern level 365 * 14 7 nmi Reserved Reserved 366 * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) 367 * 16 5 timer 368 * 17 1 extern level 369 * 18 1 extern level 370 * 19 2 extern level 371 * 20 2 extern level 372 * 21 2 extern level 373 * 22 3 extern edge 374 * 23 3 extern level 375 * 24 4 extern level TG1_WDT 376 * 25 4 extern level CACHEERR 377 * 26 5 extern level 378 * 27 3 extern level Reserved Reserved 379 * 28 4 extern edge IPC_ISR IPC_ISR 380 * 29 3 software Reserved Reserved 381 * 30 4 extern edge Reserved Reserved 382 * 31 5 extern level 383 ************************************************************************************************************* 384 */ 385 386 //CPU0 Interrupt number reserved, not touch this. 387 #define ETS_WMAC_INUM 0 388 #define ETS_BT_HOST_INUM 1 389 #define ETS_WBB_INUM 4 390 #define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ 391 #define ETS_FRC1_INUM 22 392 #define ETS_T1_WDT_INUM 24 393 #define ETS_MEMACCESS_ERR_INUM 25 394 /* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/ 395 #define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM 396 #define ETS_IPC_ISR_INUM 28 397 398 #endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */ 399 400 //CPU0 Interrupt number used in ROM, should be cancelled in SDK 401 #define ETS_SLC_INUM 1 402 #define ETS_UART0_INUM 5 403 #define ETS_UART1_INUM 5 404 //Other interrupt number should be managed by the user 405 406 //Invalid interrupt for number interrupt matrix 407 #define ETS_INVALID_INUM 6 408 409 // Interrupt number for the Interrupt watchdog 410 #define ETS_INT_WDT_INUM (ETS_T1_WDT_INUM) 411
