1 /* 2 * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 // The long term plan is to have a single soc_caps.h for all peripherals. 8 // During the refactoring and multichip support development process, we 9 // separate these information into periph_caps.h for each peripheral and 10 // include them here to avoid developing conflicts. 11 12 #pragma once 13 14 /*-------------------------- COMMON CAPS ---------------------------------------*/ 15 #define SOC_ADC_SUPPORTED 1 16 #define SOC_PCNT_SUPPORTED 1 17 #define SOC_TWAI_SUPPORTED 1 18 #define SOC_GDMA_SUPPORTED 1 19 #define SOC_LCDCAM_SUPPORTED 1 20 #define SOC_MCPWM_SUPPORTED 1 21 #define SOC_DEDICATED_GPIO_SUPPORTED 1 22 #define SOC_CPU_CORES_NUM 2 23 #define SOC_CACHE_SUPPORT_WRAP 1 24 #define SOC_ULP_SUPPORTED 1 25 #define SOC_BT_SUPPORTED 1 26 #define SOC_USB_OTG_SUPPORTED 1 27 #define SOC_USB_SERIAL_JTAG_SUPPORTED 1 28 #define SOC_RTC_SLOW_MEM_SUPPORTED 1 29 #define SOC_CCOMP_TIMER_SUPPORTED 1 30 #define SOC_DIG_SIGN_SUPPORTED 1 31 #define SOC_HMAC_SUPPORTED 1 32 #define SOC_ASYNC_MEMCPY_SUPPORTED 1 33 #define SOC_SUPPORTS_SECURE_DL_MODE 1 34 #define SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS 3 35 #define SOC_EFUSE_REVOKE_BOOT_KEY_DIGESTS 1 36 #define SOC_SDMMC_HOST_SUPPORTED 1 37 #define SOC_FLASH_ENCRYPTION_XTS_AES 1 38 #define SOC_FLASH_ENCRYPTION_XTS_AES_256 1 39 #define SOC_PSRAM_DMA_CAPABLE 1 40 #define SOC_XT_WDT_SUPPORTED 1 41 42 /*-------------------------- SOC CAPS ----------------------------------------*/ 43 #define SOC_APPCPU_HAS_CLOCK_GATING_BUG (1) 44 45 /*-------------------------- ADC CAPS ----------------------------------------*/ 46 /*!< SAR ADC Module*/ 47 #define SOC_ADC_RTC_CTRL_SUPPORTED 1 48 #define SOC_ADC_DIG_CTRL_SUPPORTED 1 49 #define SOC_ADC_ARBITER_SUPPORTED 1 50 #define SOC_ADC_FILTER_SUPPORTED 1 51 #define SOC_ADC_MONITOR_SUPPORTED 1 52 #define SOC_ADC_PERIPH_NUM (2) 53 #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) 54 #define SOC_ADC_MAX_CHANNEL_NUM (10) 55 56 /*!< Digital */ 57 #define SOC_ADC_DIGI_CONTROLLER_NUM (2) 58 #define SOC_ADC_PATT_LEN_MAX (24) //Two pattern table, each contains 12 items. Each item takes 1 byte 59 #define SOC_ADC_DIGI_MAX_BITWIDTH (13) 60 /*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */ 61 #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333 62 #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611 63 64 /*!< RTC */ 65 #define SOC_ADC_MAX_BITWIDTH (12) 66 67 /*!< Calibration */ 68 #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/ 69 70 71 /*-------------------------- APB BACKUP DMA CAPS -------------------------------*/ 72 #define SOC_APB_BACKUP_DMA (1) 73 74 /*-------------------------- BROWNOUT CAPS -----------------------------------*/ 75 #include "brownout_caps.h" 76 77 /*-------------------------- CPU CAPS ----------------------------------------*/ 78 #include "cpu_caps.h" 79 80 /*-------------------------- DIGITAL SIGNATURE CAPS ----------------------------------------*/ 81 /** The maximum length of a Digital Signature in bits. */ 82 #define SOC_DS_SIGNATURE_MAX_BIT_LEN (4096) 83 84 /** Initialization vector (IV) length for the RSA key parameter message digest (MD) in bytes. */ 85 #define SOC_DS_KEY_PARAM_MD_IV_LENGTH (16) 86 87 /** Maximum wait time for DS parameter decryption key. If overdue, then key error. 88 See TRM DS chapter for more details */ 89 #define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100) 90 91 /*-------------------------- GDMA CAPS ---------------------------------------*/ 92 #define SOC_GDMA_GROUPS (1) // Number of GDMA groups 93 #define SOC_GDMA_PAIRS_PER_GROUP (5) // Number of GDMA pairs in each group 94 #define SOC_GDMA_SUPPORT_PSRAM (1) // GDMA can access external PSRAM 95 #define SOC_GDMA_PSRAM_MIN_ALIGN (16) // Minimal alignment for PSRAM transaction 96 97 /*-------------------------- GPIO CAPS ---------------------------------------*/ 98 #include "gpio_caps.h" 99 100 /*-------------------------- Dedicated GPIO CAPS -----------------------------*/ 101 #define SOC_DEDIC_GPIO_OUT_CHANNELS_NUM (8) /*!< 8 outward channels on each CPU core */ 102 #define SOC_DEDIC_GPIO_IN_CHANNELS_NUM (8) /*!< 8 inward channels on each CPU core */ 103 #define SOC_DEDIC_GPIO_OUT_AUTO_ENABLE (1) /*!< Dedicated GPIO output attribution is enabled automatically */ 104 105 /*-------------------------- I2C CAPS ----------------------------------------*/ 106 #include "i2c_caps.h" 107 108 /*-------------------------- I2S CAPS ----------------------------------------*/ 109 #define SOC_I2S_NUM (2) 110 #define SOC_I2S_SUPPORTS_PCM (1) 111 #define SOC_I2S_SUPPORTS_PDM_TX (1) 112 #define SOC_I2S_SUPPORTS_PDM_RX (1) 113 #define SOC_I2S_SUPPORTS_PDM_CODEC (1) 114 #define SOC_I2S_SUPPORTS_TDM (1) 115 116 /*-------------------------- LEDC CAPS ---------------------------------------*/ 117 #include "ledc_caps.h" 118 119 /*-------------------------- MCPWM CAPS --------------------------------------*/ 120 #define SOC_MCPWM_GROUPS (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals) 121 #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has 122 #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has 123 #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has 124 #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has 125 #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has 126 #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has 127 #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has 128 #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has 129 #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has 130 #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output 131 #define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz 132 133 /*-------------------------- MPU CAPS ----------------------------------------*/ 134 #include "mpu_caps.h" 135 136 /*-------------------------- PCNT CAPS ---------------------------------------*/ 137 #define SOC_PCNT_GROUPS (1) 138 #define SOC_PCNT_UNITS_PER_GROUP (4) 139 #define SOC_PCNT_CHANNELS_PER_UNIT (2) 140 #define SOC_PCNT_THRES_POINT_PER_UNIT (2) 141 142 /*-------------------------- RMT CAPS ----------------------------------------*/ 143 #define SOC_RMT_GROUPS (1) /*!< One RMT group */ 144 #define SOC_RMT_TX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Transmit in each group */ 145 #define SOC_RMT_RX_CANDIDATES_PER_GROUP (4) /*!< Number of channels that capable of Receive in each group */ 146 #define SOC_RMT_CHANNELS_PER_GROUP (8) /*!< Total 8 channels */ 147 #define SOC_RMT_MEM_WORDS_PER_CHANNEL (48) /*!< Each channel owns 48 words memory (1 word = 4 Bytes) */ 148 #define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ 149 #define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ 150 #define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ 151 #define SOC_RMT_SUPPORT_TX_LOOP_AUTOSTOP (1) /*!< Hardware support of auto-stop in loop mode */ 152 #define SOC_RMT_SUPPORT_TX_SYNCHRO (1) /*!< Support coordinate a group of TX channels to start simultaneously */ 153 #define SOC_RMT_SUPPORT_XTAL (1) /*!< Support set XTAL clock as the RMT clock source */ 154 155 156 /*-------------------------- LCD CAPS ----------------------------------------*/ 157 /* Notes: On esp32-s3, I80 bus and RGB timing generator can't work at the same time */ 158 #define SOC_LCD_I80_SUPPORTED (1) /*!< Intel 8080 LCD is supported */ 159 #define SOC_LCD_RGB_SUPPORTED (1) /*!< RGB LCD is supported */ 160 #define SOC_LCD_I80_BUSES (1) /*!< Has one LCD Intel 8080 bus */ 161 #define SOC_LCD_RGB_PANELS (1) /*!< Support one RGB LCD panel */ 162 #define SOC_LCD_I80_BUS_WIDTH (16) /*!< Intel 8080 bus width */ 163 #define SOC_LCD_RGB_DATA_WIDTH (16) /*!< Number of LCD data lines */ 164 165 /*-------------------------- RTC CAPS --------------------------------------*/ 166 #define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128) 167 #define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (549) 168 #define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) 169 #define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3) 170 171 #define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)) 172 173 /* I/D Cache tag memory retention hardware parameters */ 174 #define SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH (128) 175 #define SOC_RTC_CNTL_TAGMEM_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_TAGMEM_PD_DMA_BUS_WIDTH >> 3) 176 177 /*-------------------------- RTCIO CAPS --------------------------------------*/ 178 #include "rtc_io_caps.h" 179 180 /*-------------------------- SIGMA DELTA CAPS --------------------------------*/ 181 #define SOC_SIGMADELTA_NUM (1) // 1 sigma-delta peripheral 182 #define SOC_SIGMADELTA_CHANNEL_NUM (8) // 8 channels 183 184 /*-------------------------- SPI CAPS ----------------------------------------*/ 185 #define SOC_SPI_PERIPH_NUM 3 186 #define SOC_SPI_DMA_CHAN_NUM 3 187 #define SOC_SPI_PERIPH_CS_NUM(i) 3 188 #define SOC_SPI_MAXIMUM_BUFFER_SIZE 64 189 #define SOC_SPI_SUPPORT_DDRCLK 1 190 #define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 191 #define SOC_SPI_SUPPORT_CD_SIG 1 192 #define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 193 #define SOC_SPI_SUPPORT_SLAVE_HD_VER2 1 194 195 // Peripheral supports DIO, DOUT, QIO, or QOUT 196 #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) 197 198 // Peripheral supports output given level during its "dummy phase" 199 #define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT 1 200 #define SOC_MEMSPI_IS_INDEPENDENT 1 201 #define SOC_SPI_MAX_PRE_DIVIDER 16 202 #define SOC_SPI_SUPPORT_OCT 1 203 204 /*-------------------------- SPIRAM CAPS ----------------------------------------*/ 205 #define SOC_SPIRAM_SUPPORTED 1 206 207 /*-------------------------- SYS TIMER CAPS ----------------------------------*/ 208 #define SOC_TOUCH_VERSION_2 (1) // Hardware version of touch sensor 209 #define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units 210 #define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units 211 #define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part 212 #define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part 213 #define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed 214 #define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level 215 #define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) 216 217 /*-------------------------- TIMER GROUP CAPS --------------------------------*/ 218 #define SOC_TIMER_GROUPS (2) 219 #define SOC_TIMER_GROUP_TIMERS_PER_GROUP (2) 220 #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54) 221 #define SOC_TIMER_GROUP_SUPPORT_XTAL (1) 222 #define SOC_TIMER_GROUP_TOTAL_TIMERS (SOC_TIMER_GROUPS * SOC_TIMER_GROUP_TIMERS_PER_GROUP) 223 224 /*-------------------------- TOUCH SENSOR CAPS -------------------------------*/ 225 #define SOC_TOUCH_SENSOR_NUM (15) /*! 15 Touch channels */ 226 #define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) /* Sopport touch proximity channel number. */ 227 #define SOC_TOUCH_PROXIMITY_MEAS_DONE_SUPPORTED (1) /*Sopport touch proximity channel measure done interrupt type. */ 228 229 #define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) /*!<If set touch threshold max value, The touch sensor can't be in touched status */ 230 #define SOC_TOUCH_PAD_MEASURE_WAIT_MAX (0xFF) /*!<The timer frequency is 8Mhz, the max value is 0xff */ 231 232 /*-------------------------- TWAI CAPS ---------------------------------------*/ 233 #include "twai_caps.h" 234 235 /*-------------------------- UART CAPS ---------------------------------------*/ 236 #include "uart_caps.h" 237 238 #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ 239 #define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */ 240 #define SOC_UART_REQUIRE_CORE_RESET (1) 241 242 /*-------------------------- USB CAPS ----------------------------------------*/ 243 #define SOC_USB_PERIPH_NUM 1 244 245 246 /*--------------------------- SHA CAPS ---------------------------------------*/ 247 /* Max amount of bytes in a single DMA operation is 4095, 248 for SHA this means that the biggest safe amount of bytes is 249 31 blocks of 128 bytes = 3968 250 */ 251 #define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968) 252 #define SOC_SHA_SUPPORT_DMA (1) 253 254 /* The SHA engine is able to resume hashing from a user supplied context */ 255 #define SOC_SHA_SUPPORT_RESUME (1) 256 257 /* Has a centralized DMA, which is shared with all peripherals */ 258 #define SOC_SHA_GDMA (1) 259 260 /* Supported HW algorithms */ 261 #define SOC_SHA_SUPPORT_SHA1 (1) 262 #define SOC_SHA_SUPPORT_SHA224 (1) 263 #define SOC_SHA_SUPPORT_SHA256 (1) 264 #define SOC_SHA_SUPPORT_SHA384 (1) 265 #define SOC_SHA_SUPPORT_SHA256 (1) 266 #define SOC_SHA_SUPPORT_SHA512 (1) 267 #define SOC_SHA_SUPPORT_SHA512_224 (1) 268 #define SOC_SHA_SUPPORT_SHA512_256 (1) 269 #define SOC_SHA_SUPPORT_SHA512_T (1) 270 271 272 /*--------------------------- RSA CAPS ---------------------------------------*/ 273 #define SOC_RSA_MAX_BIT_LEN (4096) 274 275 276 /*-------------------------- AES CAPS -----------------------------------------*/ 277 #define SOC_AES_SUPPORT_DMA (1) 278 279 /* Has a centralized DMA, which is shared with all peripherals */ 280 #define SOC_AES_GDMA (1) 281 282 #define SOC_AES_SUPPORT_AES_128 (1) 283 #define SOC_AES_SUPPORT_AES_256 (1) 284 285 286 /*-------------------------- Power Management CAPS ---------------------------*/ 287 #define SOC_PM_SUPPORT_EXT_WAKEUP (1) 288 289 #define SOC_PM_SUPPORT_WIFI_WAKEUP (1) 290 291 #define SOC_PM_SUPPORT_BT_WAKEUP (1) 292 293 #define SOC_PM_SUPPORT_CPU_PD (1) 294 295 #define SOC_PM_SUPPORT_TAGMEM_PD (1) 296 297 #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */ 298 299 #define SOC_PM_SUPPORT_DEEPSLEEP_VERIFY_STUB_ONLY (1) 300 301 302 /*-------------------------- Flash Encryption CAPS----------------------------*/ 303 #define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64) 304 305 306 /*-------------------------- WI-FI HARDWARE TSF CAPS -------------------------------*/ 307 #define SOC_WIFI_HW_TSF (1) 308 309 /*--------------- PHY REGISTER AND MEMORY SIZE CAPS --------------------------*/ 310 #define SOC_PHY_DIG_REGS_MEM_SIZE (21*4) 311 #define SOC_MAC_BB_PD_MEM_SIZE (192*4) 312 313 /*--------------- WIFI LIGHT SLEEP CLOCK WIDTH CAPS --------------------------*/ 314 #define SOC_WIFI_LIGHT_SLEEP_CLK_WIDTH (12) 315 316 /*-------------------------- SPI MEM CAPS ---------------------------------------*/ 317 #define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1) 318 #define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1) 319 #define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1) 320 #define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1) 321 #define SOC_SPI_MEM_SUPPORT_OPI_MODE (1) 322 #define SOC_SPI_MEM_SUPPORT_TIME_TUNING (1) 323 324 /*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/ 325 #define SOC_COEX_HW_PTI (1) 326 327 /*-------------------------- SDMMC CAPS -----------------------------------------*/ 328 329 /* Card detect, write protect, interrupt use GPIO Matrix on all chips. 330 * On ESP32-S3, clock/cmd/data pins use GPIO Matrix as well. 331 */ 332 #define SOC_SDMMC_USE_GPIO_MATRIX 1 333 #define SOC_SDMMC_NUM_SLOTS 2 334 /* Indicates that there is an option to use XTAL clock instead of PLL for SDMMC */ 335 #define SOC_SDMMC_SUPPORT_XTAL_CLOCK 1 336
