1 /*
2 * Copyright (c) 2020 Nuvoton Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _NUVOTON_NPCX_REG_DEF_H
8 #define _NUVOTON_NPCX_REG_DEF_H
9
10 #include <stdint.h>
11
12 #include <zephyr/devicetree.h>
13 #include <zephyr/sys/__assert.h>
14 #include <zephyr/sys/util_macro.h>
15 #include <zephyr/toolchain.h>
16
17 /*
18 * NPCX register structure size/offset checking macro function to mitigate
19 * the risk of unexpected compiling results. All addresses of NPCX registers
20 * must meet the alignment requirement of cortex-m4.
21 * DO NOT use 'packed' attribute if module contains different length ie.
22 * 8/16/32 bits registers.
23 */
24 #define NPCX_REG_SIZE_CHECK(reg_def, size) \
25 BUILD_ASSERT(sizeof(struct reg_def) == size, \
26 "Failed in size check of register structure!")
27 #define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
28 BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
29 "Failed in offset check of register structure member!")
30
31 /*
32 * NPCX register access checking via structure macro function to mitigate the
33 * risk of unexpected compiling results if module contains different length
34 * registers. For example, a word register access might break into two byte
35 * register accesses by adding 'packed' attribute.
36 *
37 * For example, add this macro for word register 'PRSC' of PWM module in its
38 * device init function for checking violation. Once it occurred, core will be
39 * stalled forever and easy to find out what happens.
40 */
41 #define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
42 uint16_t placeholder = reg; \
43 reg = val; \
44 __ASSERT(reg == val, "16-bit reg access failed!"); \
45 reg = placeholder; \
46 }
47 #define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
48 uint32_t placeholder = reg; \
49 reg = val; \
50 __ASSERT(reg == val, "32-bit reg access failed!"); \
51 reg = placeholder; \
52 }
53 /*
54 * Core Domain Clock Generator (CDCG) device registers
55 */
56 struct cdcg_reg {
57 /* High Frequency Clock Generator (HFCG) registers */
58 /* 0x000: HFCG Control */
59 volatile uint8_t HFCGCTRL;
60 volatile uint8_t reserved1;
61 /* 0x002: HFCG M Low Byte Value */
62 volatile uint8_t HFCGML;
63 volatile uint8_t reserved2;
64 /* 0x004: HFCG M High Byte Value */
65 volatile uint8_t HFCGMH;
66 volatile uint8_t reserved3;
67 /* 0x006: HFCG N Value */
68 volatile uint8_t HFCGN;
69 volatile uint8_t reserved4;
70 /* 0x008: HFCG Prescaler */
71 volatile uint8_t HFCGP;
72 volatile uint8_t reserved5[7];
73 /* 0x010: HFCG Bus Clock Dividers */
74 volatile uint8_t HFCBCD;
75 volatile uint8_t reserved6;
76 /* 0x012: HFCG Bus Clock Dividers */
77 volatile uint8_t HFCBCD1;
78 volatile uint8_t reserved7;
79 /* 0x014: HFCG Bus Clock Dividers */
80 volatile uint8_t HFCBCD2;
81 volatile uint8_t reserved8[235];
82
83 /* Low Frequency Clock Generator (LFCG) registers */
84 /* 0x100: LFCG Control */
85 volatile uint8_t LFCGCTL;
86 volatile uint8_t reserved9;
87 /* 0x102: High-Frequency Reference Divisor I */
88 volatile uint16_t HFRDI;
89 /* 0x104: High-Frequency Reference Divisor F */
90 volatile uint16_t HFRDF;
91 /* 0x106: FRCLK Clock Divisor */
92 volatile uint16_t FRCDIV;
93 /* 0x108: Divisor Correction Value 1 */
94 volatile uint16_t DIVCOR1;
95 /* 0x10A: Divisor Correction Value 2 */
96 volatile uint16_t DIVCOR2;
97 volatile uint8_t reserved10[8];
98 /* 0x114: LFCG Control 2 */
99 volatile uint8_t LFCGCTL2;
100 volatile uint8_t reserved11;
101 };
102
103 /* CDCG register fields */
104 #define NPCX_HFCGCTRL_LOAD 0
105 #define NPCX_HFCGCTRL_LOCK 2
106 #define NPCX_HFCGCTRL_CLK_CHNG 7
107
108 #define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
109
110 /*
111 * Power Management Controller (PMC) device registers
112 */
113 struct pmc_reg {
114 /* 0x000: Power Management Controller */
115 volatile uint8_t PMCSR;
116 volatile uint8_t reserved1[2];
117 /* 0x003: Enable in Sleep Control */
118 volatile uint8_t ENIDL_CTL;
119 /* 0x004: Disable in Idle Control */
120 volatile uint8_t DISIDL_CTL;
121 /* 0x005: Disable in Idle Control 1 */
122 volatile uint8_t DISIDL_CTL1;
123 volatile uint8_t reserved2[2];
124 /* 0x008 - 0D: Power-Down Control 1 - 6 */
125 volatile uint8_t PWDWN_CTL1[6];
126 volatile uint8_t reserved3[18];
127 /* 0x020 - 21: Power-Down Control 1 - 2 */
128 volatile uint8_t RAM_PD[2];
129 volatile uint8_t reserved4[2];
130 /* 0x024: Power-Down Control 7 */
131 volatile uint8_t PWDWN_CTL7[1];
132 };
133
134 /* PMC internal inline functions for multi-registers */
npcx_pwdwn_ctl_offset(uint32_t ctl_no)135 static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
136 {
137 if (ctl_no < 6) {
138 return 0x008 + ctl_no;
139 } else {
140 return 0x024 + ctl_no - 6;
141 }
142 }
143
144 /* Macro functions for PMC multi-registers */
145 #define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
146 npcx_pwdwn_ctl_offset(n)))
147
148 /* PMC register fields */
149 #define NPCX_PMCSR_DI_INSTW 0
150 #define NPCX_PMCSR_DHF 1
151 #define NPCX_PMCSR_IDLE 2
152 #define NPCX_PMCSR_NWBI 3
153 #define NPCX_PMCSR_OHFC 6
154 #define NPCX_PMCSR_OLFC 7
155 #define NPCX_DISIDL_CTL_RAM_DID 5
156 #define NPCX_ENIDL_CTL_ADC_LFSL 7
157 #define NPCX_ENIDL_CTL_LP_WK_CTL 6
158 #define NPCX_ENIDL_CTL_PECI_ENI 2
159 #define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
160
161 /* Macro functions for Development and Debugger Interface (DDI) registers */
162 #define NPCX_DBGCTRL(base) (*(volatile uint8_t *)(base + 0x004))
163 #define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006))
164 #define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007))
165 #define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008))
166 #define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009))
167
168 /* DDI register fields */
169 #define NPCX_DBGCTRL_CCDEV_SEL FIELD(6, 2)
170 #define NPCX_DBGCTRL_CCDEV_DIR 5
171 #define NPCX_DBGCTRL_SEQ_WK_EN 4
172 #define NPCX_DBGCTRL_FRCLK_SEL_DIS 3
173 #define NPCX_DBGFRZEN1_SPIFEN 7
174 #define NPCX_DBGFRZEN1_HIFEN 6
175 #define NPCX_DBGFRZEN1_ESPISEN 5
176 #define NPCX_DBGFRZEN1_UART1FEN 4
177 #define NPCX_DBGFRZEN1_SMB3FEN 3
178 #define NPCX_DBGFRZEN1_SMB2FEN 2
179 #define NPCX_DBGFRZEN1_MFT2FEN 1
180 #define NPCX_DBGFRZEN1_MFT1FEN 0
181 #define NPCX_DBGFRZEN2_ITIM6FEN 7
182 #define NPCX_DBGFRZEN2_ITIM5FEN 6
183 #define NPCX_DBGFRZEN2_ITIM4FEN 5
184 #define NPCX_DBGFRZEN2_ITIM64FEN 3
185 #define NPCX_DBGFRZEN2_SMB1FEN 2
186 #define NPCX_DBGFRZEN2_SMB0FEN 1
187 #define NPCX_DBGFRZEN2_MFT3FEN 0
188 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
189 #define NPCX_DBGFRZEN3_ITIM3FEN 6
190 #define NPCX_DBGFRZEN3_ITIM2FEN 5
191 #define NPCX_DBGFRZEN3_ITIM1FEN 4
192 #define NPCX_DBGFRZEN3_I3CFEN 2
193 #define NPCX_DBGFRZEN3_SMB4FEN 1
194 #define NPCX_DBGFRZEN3_SHMFEN 0
195 #define NPCX_DBGFRZEN4_UART2FEN 6
196 #define NPCX_DBGFRZEN4_UART3FEN 5
197 #define NPCX_DBGFRZEN4_UART4FEN 4
198 #define NPCX_DBGFRZEN4_LCTFEN 3
199 #define NPCX_DBGFRZEN4_SMB7FEN 2
200 #define NPCX_DBGFRZEN4_SMB6FEN 1
201 #define NPCX_DBGFRZEN4_SMB5FEN 0
202
203 /*
204 * System Configuration (SCFG) device registers
205 */
206 struct scfg_reg {
207 /* 0x000: Device Control */
208 volatile uint8_t DEVCNT;
209 /* 0x001: Straps Status */
210 volatile uint8_t STRPST;
211 /* 0x002: Reset Control and Status */
212 volatile uint8_t RSTCTL;
213 volatile uint8_t reserved1[3];
214 /* 0x006: Device Control 4 */
215 volatile uint8_t DEV_CTL4;
216 volatile uint8_t reserved2[9];
217 /* 0x010 - 1F: Device Alternate Function 0 - F */
218 volatile uint8_t DEVALT0[16];
219 volatile uint8_t reserved3[6];
220 /* 0x026: Low-Voltage GPIO Pins Control 5 */
221 volatile uint8_t LV_GPIO_CTL5[1];
222 volatile uint8_t reserved4;
223 /* 0x028: Pull-Up/Pull-Down Enable 0 */
224 volatile uint8_t PUPD_EN0;
225 /* 0x029: Pull-Up/Pull-Down Enable 1 */
226 volatile uint8_t PUPD_EN1;
227 /* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
228 volatile uint8_t LV_GPIO_CTL0[5];
229 };
230
231 /* SCFG internal inline functions for multi-registers */
npcx_devalt_offset(uint32_t alt_no)232 static inline uint32_t npcx_devalt_offset(uint32_t alt_no)
233 {
234 return 0x010 + alt_no;
235 }
236
npcx_devalt_lk_offset(uint32_t alt_lk_no)237 static inline uint32_t npcx_devalt_lk_offset(uint32_t alt_lk_no)
238 {
239 return 0x210 + alt_lk_no;
240 }
241
npcx_pupd_en_offset(uint32_t pupd_en_no)242 static inline uint32_t npcx_pupd_en_offset(uint32_t pupd_en_no)
243 {
244 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
245 return 0x28 + pupd_en_no;
246 } else { /* NPCX4 and later series */
247 return 0x2b + pupd_en_no;
248 }
249 }
250
npcx_lv_gpio_ctl_offset(uint32_t ctl_no)251 static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
252 {
253 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7) || IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
254 if (ctl_no < 5) {
255 return 0x02a + ctl_no;
256 } else {
257 return 0x026 + ctl_no - 5;
258 }
259 } else { /* NPCX4 and later series */
260 return 0x150 + ctl_no;
261 }
262 }
263
264 /* Macro functions for SCFG multi-registers */
265 #define NPCX_DEV_CTL(base, n) (*(volatile uint8_t *)(base + n))
266 #define NPCX_DEVALT(base, n) (*(volatile uint8_t *)(base + \
267 npcx_devalt_offset(n)))
268 #define NPCX_DEVALT_LK(base, n) (*(volatile uint8_t *)(base + \
269 npcx_devalt_lk_offset(n)))
270 #define NPCX_PUPD_EN(base, n) (*(volatile uint8_t *)(base + \
271 npcx_pupd_en_offset(n)))
272 #define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + \
273 npcx_lv_gpio_ctl_offset(n)))
274
275 /* SCFG register fields */
276 #define NPCX_DEVCNT_F_SPI_TRIS 6
277 #define NPCX_DEVCNT_HIF_TYP_SEL_FIELD FIELD(2, 2)
278 #define NPCX_DEVCNT_JEN1_HEN 5
279 #define NPCX_DEVCNT_JEN0_HEN 4
280 #define NPCX_STRPST_TRIST 1
281 #define NPCX_STRPST_TEST 2
282 #define NPCX_STRPST_JEN1 4
283 #define NPCX_STRPST_JEN0 5
284 #define NPCX_STRPST_SPI_COMP 7
285 #define NPCX_RSTCTL_VCC1_RST_STS 0
286 #define NPCX_RSTCTL_DBGRST_STS 1
287 #define NPCX_RSTCTL_VCC1_RST_SCRATCH 3
288 #define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
289 #define NPCX_RSTCTL_HIPRST_MODE 6
290 #define NPCX_DEV_CTL4_F_SPI_SLLK 2
291 #define NPCX_DEV_CTL4_SPI_SP_SEL 4
292 #define NPCX_DEV_CTL4_WP_IF 5
293 #define NPCX_DEV_CTL4_VCC1_RST_LK 6
294 #define NPCX_DEVPU0_I2C0_0_PUE 0
295 #define NPCX_DEVPU0_I2C0_1_PUE 1
296 #define NPCX_DEVPU0_I2C1_0_PUE 2
297 #define NPCX_DEVPU0_I2C2_0_PUE 4
298 #define NPCX_DEVPU0_I2C3_0_PUE 6
299 #define NPCX_DEVPU1_F_SPI_PUD_EN 7
300
301 /* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
302 enum npcx_hif_type {
303 NPCX_HIF_TYPE_NONE,
304 NPCX_HIF_TYPE_LPC,
305 NPCX_HIF_TYPE_ESPI_SHI,
306 };
307
308 /*
309 * System Glue (GLUE) device registers
310 */
311 struct glue_reg {
312 volatile uint8_t reserved1[2];
313 /* 0x002: SMBus Start Bit Detection */
314 volatile uint8_t SMB_SBD;
315 /* 0x003: SMBus Event Enable */
316 volatile uint8_t SMB_EEN;
317 volatile uint8_t reserved2[12];
318 /* 0x010: Simple Debug Port Data 0 */
319 volatile uint8_t SDPD0;
320 volatile uint8_t reserved3;
321 /* 0x012: Simple Debug Port Data 1 */
322 volatile uint8_t SDPD1;
323 volatile uint8_t reserved4;
324 /* 0x014: Simple Debug Port Control and Status */
325 volatile uint8_t SDP_CTS;
326 volatile uint8_t reserved5[12];
327 /* 0x021: SMBus Bus Select */
328 volatile uint8_t SMB_SEL;
329 volatile uint8_t reserved6[5];
330 /* 0x027: PSL Control and Status */
331 volatile uint8_t PSL_CTS;
332 };
333
334 /* GLUE register fields */
335 /* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
336 #define NPCX_PSL_CTS_MODE_BIT(bit) BIT(bit + 4)
337 /* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
338 #define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
339
340 /*
341 * Universal Asynchronous Receiver-Transmitter (UART) device registers
342 */
343 struct uart_reg {
344 /* 0x000: Transmit Data Buffer */
345 volatile uint8_t UTBUF;
346 volatile uint8_t reserved1;
347 /* 0x002: Receive Data Buffer */
348 volatile uint8_t URBUF;
349 volatile uint8_t reserved2;
350 /* 0x004: Interrupt Control */
351 volatile uint8_t UICTRL;
352 volatile uint8_t reserved3;
353 /* 0x006: Status */
354 volatile uint8_t USTAT;
355 volatile uint8_t reserved4;
356 /* 0x008: Frame Select */
357 volatile uint8_t UFRS;
358 volatile uint8_t reserved5;
359 /* 0x00A: Mode Select */
360 volatile uint8_t UMDSL;
361 volatile uint8_t reserved6;
362 /* 0x00C: Baud Rate Divisor */
363 volatile uint8_t UBAUD;
364 volatile uint8_t reserved7;
365 /* 0x00E: Baud Rate Prescaler */
366 volatile uint8_t UPSR;
367 volatile uint8_t reserved8[17];
368 /* 0x020: FIFO Mode Transmit Status */
369 volatile uint8_t UFTSTS;
370 volatile uint8_t reserved9;
371 /* 0x022: FIFO Mode Receive Status */
372 volatile uint8_t UFRSTS;
373 volatile uint8_t reserved10;
374 /* 0x024: FIFO Mode Transmit Control */
375 volatile uint8_t UFTCTL;
376 volatile uint8_t reserved11;
377 /* 0x026: FIFO Mode Receive Control */
378 volatile uint8_t UFRCTL;
379 };
380
381 /* UART register fields */
382 #define NPCX_UICTRL_TBE 0
383 #define NPCX_UICTRL_RBF 1
384 #define NPCX_UICTRL_ETI 5
385 #define NPCX_UICTRL_ERI 6
386 #define NPCX_UICTRL_EEI 7
387 #define NPCX_USTAT_PE 0
388 #define NPCX_USTAT_FE 1
389 #define NPCX_USTAT_DOE 2
390 #define NPCX_USTAT_ERR 3
391 #define NPCX_USTAT_BKD 4
392 #define NPCX_USTAT_RB9 5
393 #define NPCX_USTAT_XMIP 6
394 #define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
395 #define NPCX_UFRS_STP 2
396 #define NPCX_UFRS_XB9 3
397 #define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
398 #define NPCX_UFRS_PEN 6
399 #define NPCX_UMDSL_FIFO_MD 0
400 #define NPCX_UFTSTS_TEMPTY_LVL FIELD(0, 5)
401 #define NPCX_UFTSTS_TEMPTY_LVL_STS 5
402 #define NPCX_UFTSTS_TFIFO_EMPTY_STS 6
403 #define NPCX_UFTSTS_NXMIP 7
404 #define NPCX_UFRSTS_RFULL_LVL_STS 5
405 #define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
406 #define NPCX_UFRSTS_ERR 7
407 #define NPCX_UFTCTL_TEMPTY_LVL_SEL FIELD(0, 5)
408 #define NPCX_UFTCTL_TEMPTY_LVL_EN 5
409 #define NPCX_UFTCTL_TEMPTY_EN 6
410 #define NPCX_UFTCTL_NXMIP_EN 7
411 #define NPCX_UFRCTL_RFULL_LVL_SEL FIELD(0, 5)
412 #define NPCX_UFRCTL_RFULL_LVL_EN 5
413 #define NPCX_UFRCTL_RNEMPTY_EN 6
414 #define NPCX_UFRCTL_ERR_EN 7
415
416 /*
417 * Multi-Input Wake-Up Unit (MIWU) device registers
418 */
419
420 /* MIWU internal inline functions for multi-registers */
npcx_wkedg_offset(uint32_t group)421 static inline uint32_t npcx_wkedg_offset(uint32_t group)
422 {
423 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
424 return 0x000 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
425 } else { /* NPCX9 and later series */
426 return 0x000 + group * 0x10UL;
427 }
428 }
429
npcx_wkaedg_offset(uint32_t group)430 static inline uint32_t npcx_wkaedg_offset(uint32_t group)
431 {
432 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
433 return 0x001 + (group * 2ul) + (group < 5 ? 0 : 0x1e);
434 } else { /* NPCX9 and later series */
435 return 0x001 + group * 0x10ul;
436 }
437 }
438
npcx_wkmod_offset(uint32_t group)439 static inline uint32_t npcx_wkmod_offset(uint32_t group)
440 {
441 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
442 return 0x070 + group;
443 } else { /* NPCX9 and later series */
444 return 0x002 + group * 0x10ul;
445 }
446 }
447
npcx_wkpnd_offset(uint32_t group)448 static inline uint32_t npcx_wkpnd_offset(uint32_t group)
449 {
450 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
451 return 0x00a + (group * 4ul) + (group < 5 ? 0 : 0x10);
452 } else { /* NPCX9 and later series */
453 return 0x003 + group * 0x10ul;
454 }
455 }
456
npcx_wkpcl_offset(uint32_t group)457 static inline uint32_t npcx_wkpcl_offset(uint32_t group)
458 {
459 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
460 return 0x00c + (group * 4ul) + (group < 5 ? 0 : 0x10);
461 } else { /* NPCX9 and later series */
462 return 0x004 + group * 0x10ul;
463 }
464 }
465
npcx_wken_offset(uint32_t group)466 static inline uint32_t npcx_wken_offset(uint32_t group)
467 {
468 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
469 return 0x01e + (group * 2ul) + (group < 5 ? 0 : 0x12);
470 } else { /* NPCX9 and later series */
471 return 0x005 + group * 0x10ul;
472 }
473 }
474
npcx_wkst_offset(uint32_t group)475 static inline uint32_t npcx_wkst_offset(uint32_t group)
476 {
477 /* NPCX9 and later series only */
478 return 0x006 + group * 0x10ul;
479 }
480
npcx_wkinen_offset(uint32_t group)481 static inline uint32_t npcx_wkinen_offset(uint32_t group)
482 {
483 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
484 return 0x01f + (group * 2ul) + (group < 5 ? 0 : 0x12);
485 } else { /* NPCX9 and later series */
486 return 0x007 + group * 0x10ul;
487 }
488 }
489
490 /* Macro functions for MIWU multi-registers */
491 #define NPCX_WKEDG(base, group) \
492 (*(volatile uint8_t *)(base + npcx_wkedg_offset(group)))
493 #define NPCX_WKAEDG(base, group) \
494 (*(volatile uint8_t *)(base + npcx_wkaedg_offset(group)))
495 #define NPCX_WKPND(base, group) \
496 (*(volatile uint8_t *)(base + npcx_wkpnd_offset(group)))
497 #define NPCX_WKPCL(base, group) \
498 (*(volatile uint8_t *)(base + npcx_wkpcl_offset(group)))
499 #define NPCX_WKEN(base, group) \
500 (*(volatile uint8_t *)(base + npcx_wken_offset(group)))
501 #define NPCX_WKINEN(base, group) \
502 (*(volatile uint8_t *)(base + npcx_wkinen_offset(group)))
503 #define NPCX_WKMOD(base, group) \
504 (*(volatile uint8_t *)(base + npcx_wkmod_offset(group)))
505
506 /*
507 * General-Purpose I/O (GPIO) device registers
508 */
509 struct gpio_reg {
510 /* 0x000: Port GPIOx Data Out */
511 volatile uint8_t PDOUT;
512 /* 0x001: Port GPIOx Data In */
513 volatile uint8_t PDIN;
514 /* 0x002: Port GPIOx Direction */
515 volatile uint8_t PDIR;
516 /* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
517 volatile uint8_t PPULL;
518 /* 0x004: Port GPIOx Pull-Up/Down Selection */
519 volatile uint8_t PPUD;
520 /* 0x005: Port GPIOx Drive Enable by VDD Present */
521 volatile uint8_t PENVDD;
522 /* 0x006: Port GPIOx Output Type */
523 volatile uint8_t PTYPE;
524 /* 0x007: Port GPIOx Lock Control */
525 volatile uint8_t PLOCK_CTL;
526 };
527
528 /*
529 * Pulse Width Modulator (PWM) device registers
530 */
531 struct pwm_reg {
532 /* 0x000: Clock Prescaler */
533 volatile uint16_t PRSC;
534 /* 0x002: Cycle Time */
535 volatile uint16_t CTR;
536 /* 0x004: PWM Control */
537 volatile uint8_t PWMCTL;
538 volatile uint8_t reserved1;
539 /* 0x006: Duty Cycle */
540 volatile uint16_t DCR;
541 volatile uint8_t reserved2[4];
542 /* 0x00C: PWM Control Extended */
543 volatile uint8_t PWMCTLEX;
544 volatile uint8_t reserved3;
545 };
546
547 /* PWM register fields */
548 #define NPCX_PWMCTL_INVP 0
549 #define NPCX_PWMCTL_CKSEL 1
550 #define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
551 #define NPCX_PWMCTL_PWR 7
552 #define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
553 #define NPCX_PWMCTLEX_OD_OUT 7
554
555 /*
556 * Analog-To-Digital Converter (ADC) device registers
557 */
558 struct adc_reg {
559 /* 0x000: ADC Status */
560 volatile uint16_t ADCSTS;
561 /* 0x002: ADC Configuration */
562 volatile uint16_t ADCCNF;
563 /* 0x004: ADC Timing Control */
564 volatile uint16_t ATCTL;
565 /* 0x006: ADC Single Channel Address */
566 volatile uint16_t ASCADD;
567 /* 0x008: ADC Scan Channels Select */
568 volatile uint16_t ADCCS;
569 /* 0x00A: ADC Scan Channels Select 2 */
570 volatile uint16_t ADCCS2;
571 volatile uint8_t reserved1[14];
572 /* 0x01A: Threshold Status */
573 volatile uint16_t THRCTS;
574 volatile uint8_t reserved2[4];
575 /* 0x020: Internal register 1 for ADC Speed */
576 volatile uint16_t ADCCNF2;
577 /* 0x022: Internal register 2 for ADC Speed */
578 volatile uint16_t GENDLY;
579 volatile uint8_t reserved3[2];
580 /* 0x026: Internal register 3 for ADC Speed */
581 volatile uint16_t MEAST;
582 };
583
584 /* ADC internal inline functions for multi-registers */
npcx_chndat_offset(uint32_t ch)585 static inline uint32_t npcx_chndat_offset(uint32_t ch)
586 {
587 return 0x40 + ch * 2;
588 }
589
npcx_thr_base(void)590 static inline uint32_t npcx_thr_base(void)
591 {
592 if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX7)) {
593 return 0x014;
594 } else if (IS_ENABLED(CONFIG_SOC_SERIES_NPCX9)) {
595 return 0x060;
596 } else { /* NPCX4 and later series */
597 return 0x080;
598 }
599 }
600
npcx_thrctl_offset(uint32_t ctrl)601 static inline uint32_t npcx_thrctl_offset(uint32_t ctrl)
602 {
603 return npcx_thr_base() + ctrl * 2;
604 }
605
606 #define CHNDAT(base, ch) (*(volatile uint16_t *)((base) + npcx_chndat_offset(ch)))
607 #define THRCTL(base, ctrl) \
608 (*(volatile uint16_t *)(base + npcx_thrctl_offset(ctrl)))
609 #ifdef CONFIG_SOC_SERIES_NPCX4
610 #define THEN(base) (*(volatile uint16_t *)(base + 0x90))
611 #endif
612
613 /* ADC register fields */
614 #define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
615 #define NPCX_ATCTL_DLY_FIELD FIELD(8, 3)
616 #define NPCX_ASCADD_SADDR_FIELD FIELD(0, 5)
617 #define NPCX_ADCSTS_EOCEV 0
618 #define NPCX_ADCSTS_EOCCEV 1
619 #define NPCX_ADCCNF_ADCEN 0
620 #define NPCX_ADCCNF_ADCMD_FIELD FIELD(1, 2)
621 #define NPCX_ADCCNF_ADCRPTC 3
622 #define NPCX_ADCCNF_START 4
623 #define NPCX_ADCCNF_ADCTTE 5
624 #define NPCX_ADCCNF_INTECEN 6
625 #define NPCX_ADCCNF_INTECCEN 7
626 #define NPCX_ADCCNF_INTETCEN 8
627 #define NPCX_ADCCNF_INTOVFEN 9
628 #define NPCX_ADCCNF_STOP 11
629 #define NPCX_CHNDAT_CHDAT_FIELD FIELD(0, 10)
630 #define NPCX_CHNDAT_NEW 15
631 #ifdef CONFIG_SOC_SERIES_NPCX4
632 #define NPCX_THRCTL_L_H 15
633 #define NPCX_THRCTL_CHNSEL FIELD(10, 5)
634 #define NPCX_THRCTL_THRVAL FIELD(0, 10)
635 #else
636 #define NPCX_THRCTL_THEN 15
637 #define NPCX_THRCTL_L_H 14
638 #define NPCX_THRCTL_CHNSEL FIELD(10, 4)
639 #define NPCX_THRCTL_THRVAL FIELD(0, 10)
640 #endif
641 #define NPCX_THRCTS_ADC_WKEN 15
642 #define NPCX_THRCTS_THR3_IEN 10
643 #define NPCX_THRCTS_THR2_IEN 9
644 #define NPCX_THRCTS_THR1_IEN 8
645 #define NPCX_THRCTS_ADC_EVENT 7
646 #define NPCX_THRCTS_THR3_STS 2
647 #define NPCX_THRCTS_THR2_STS 1
648 #define NPCX_THRCTS_THR1_STS 0
649 #define NPCX_THR_DCTL_THRD_EN 15
650 #define NPCX_THR_DCTL_THR_DVAL FIELD(0, 10)
651
652 /*
653 * Timer Watchdog (TWD) device registers
654 */
655 struct twd_reg {
656 /* 0x000: Timer and Watchdog Configuration */
657 volatile uint8_t TWCFG;
658 volatile uint8_t reserved1;
659 /* 0x002: Timer and Watchdog Clock Prescaler */
660 volatile uint8_t TWCP;
661 volatile uint8_t reserved2;
662 /* 0x004: TWD Timer 0 */
663 volatile uint16_t TWDT0;
664 /* 0x006: TWDT0 Control and Status */
665 volatile uint8_t T0CSR;
666 volatile uint8_t reserved3;
667 /* 0x008: Watchdog Count */
668 volatile uint8_t WDCNT;
669 volatile uint8_t reserved4;
670 /* 0x00A: Watchdog Service Data Match */
671 volatile uint8_t WDSDM;
672 volatile uint8_t reserved5;
673 /* 0x00C: TWD Timer 0 Counter */
674 volatile uint16_t TWMT0;
675 /* 0x00E: Watchdog Counter */
676 volatile uint8_t TWMWD;
677 volatile uint8_t reserved6;
678 /* 0x010: Watchdog Clock Prescaler */
679 volatile uint8_t WDCP;
680 volatile uint8_t reserved7;
681 };
682
683 /* TWD register fields */
684 #define NPCX_TWCFG_LTWCFG 0
685 #define NPCX_TWCFG_LTWCP 1
686 #define NPCX_TWCFG_LTWDT0 2
687 #define NPCX_TWCFG_LWDCNT 3
688 #define NPCX_TWCFG_WDCT0I 4
689 #define NPCX_TWCFG_WDSDME 5
690 #define NPCX_T0CSR_RST 0
691 #define NPCX_T0CSR_TC 1
692 #define NPCX_T0CSR_WDLTD 3
693 #define NPCX_T0CSR_WDRST_STS 4
694 #define NPCX_T0CSR_WD_RUN 5
695 #define NPCX_T0CSR_TESDIS 7
696
697 /*
698 * Enhanced Serial Peripheral Interface (eSPI) device registers
699 */
700 struct espi_reg {
701 /* 0x000: eSPI Identification */
702 volatile uint32_t ESPIID;
703 /* 0x004: eSPI Configuration */
704 volatile uint32_t ESPICFG;
705 /* 0x008: eSPI Status */
706 volatile uint32_t ESPISTS;
707 /* 0x00C: eSPI Interrupt Enable */
708 volatile uint32_t ESPIIE;
709 /* 0x010: eSPI Wake-Up Enable */
710 volatile uint32_t ESPIWE;
711 /* 0x014: Virtual Wire Register Index */
712 volatile uint32_t VWREGIDX;
713 /* 0x018: Virtual Wire Register Data */
714 volatile uint32_t VWREGDATA;
715 /* 0x01C: OOB Receive Buffer Read Head */
716 volatile uint32_t OOBRXRDHEAD;
717 /* 0x020: OOB Transmit Buffer Write Head */
718 volatile uint32_t OOBTXWRHEAD;
719 /* 0x024: OOB Channel Control */
720 volatile uint32_t OOBCTL;
721 /* 0x028: Flash Receive Buffer Read Head */
722 volatile uint32_t FLASHRXRDHEAD;
723 /* 0x02C: Flash Transmit Buffer Write Head */
724 volatile uint32_t FLASHTXWRHEAD;
725 volatile uint32_t reserved1;
726 /* 0x034: Flash Channel Configuration */
727 volatile uint32_t FLASHCFG;
728 /* 0x038: Flash Channel Control */
729 volatile uint32_t FLASHCTL;
730 /* 0x03C: eSPI Error Status */
731 volatile uint32_t ESPIERR;
732 /* 0x040: Peripheral Bus Master Receive Buffer Read Head */
733 volatile uint32_t PBMRXRDHEAD;
734 /* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
735 volatile uint32_t PBMTXWRHEAD;
736 /* 0x048: Peripheral Channel Configuration */
737 volatile uint32_t PERCFG;
738 /* 0x04C: Peripheral Channel Control */
739 volatile uint32_t PERCTL;
740 /* 0x050: Status Image Register */
741 volatile uint16_t STATUS_IMG;
742 volatile uint16_t reserved2[79];
743 /* 0x0F0: NPCX specific eSPI Register1 */
744 volatile uint8_t NPCX_ONLY_ESPI_REG1;
745 /* 0x0F1: NPCX specific eSPI Register2 */
746 volatile uint8_t NPCX_ONLY_ESPI_REG2;
747 volatile uint16_t reserved3[7];
748 /* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
749 volatile uint32_t VWEVSM[10];
750 volatile uint32_t reserved4[6];
751 /* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
752 volatile uint32_t VWEVMS[12];
753 volatile uint32_t reserved5[4];
754 /* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
755 volatile uint32_t VWGPSM[16];
756 volatile uint32_t reserved6[79];
757 /* 0x2FC: Virtual Wire Channel Control */
758 volatile uint32_t VWCTL;
759 /* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
760 volatile uint32_t OOBRXBUF[20];
761 volatile uint32_t reserved7[12];
762 /* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
763 volatile uint32_t OOBTXBUF[20];
764 volatile uint32_t reserved8[11];
765 /* 0x3FC: OOB Channel Control used in 'direct' mode */
766 volatile uint32_t OOBCTL_DIRECT;
767 /* 0x400 - 443: Flash Receive Buffer 0-16 */
768 volatile uint32_t FLASHRXBUF[17];
769 volatile uint32_t reserved9[15];
770 /* 0x480 - 497: Flash Transmit Buffer 0-5 */
771 volatile uint32_t FLASHTXBUF[6];
772 volatile uint32_t reserved10[25];
773 /* 0x4FC: Flash Channel Control used in 'direct' mode */
774 volatile uint32_t FLASHCTL_DIRECT;
775 };
776
777 /* eSPI register fields */
778 #define NPCX_ESPICFG_PCHANEN 0
779 #define NPCX_ESPICFG_VWCHANEN 1
780 #define NPCX_ESPICFG_OOBCHANEN 2
781 #define NPCX_ESPICFG_FLASHCHANEN 3
782 #define NPCX_ESPICFG_HPCHANEN 4
783 #define NPCX_ESPICFG_HVWCHANEN 5
784 #define NPCX_ESPICFG_HOOBCHANEN 6
785 #define NPCX_ESPICFG_HFLASHCHANEN 7
786 #define NPCX_ESPICFG_CHANS_FIELD FIELD(0, 4)
787 #define NPCX_ESPICFG_HCHANS_FIELD FIELD(4, 4)
788 #define NPCX_ESPICFG_IOMODE_FIELD FIELD(8, 2)
789 #define NPCX_ESPICFG_MAXFREQ_FIELD FIELD(10, 3)
790 #define NPCX_ESPICFG_PCCHN_SUPP 24
791 #define NPCX_ESPICFG_VWCHN_SUPP 25
792 #define NPCX_ESPICFG_OOBCHN_SUPP 26
793 #define NPCX_ESPICFG_FLASHCHN_SUPP 27
794 #define NPCX_ESPIIE_IBRSTIE 0
795 #define NPCX_ESPIIE_CFGUPDIE 1
796 #define NPCX_ESPIIE_BERRIE 2
797 #define NPCX_ESPIIE_OOBRXIE 3
798 #define NPCX_ESPIIE_FLASHRXIE 4
799 #define NPCX_ESPIIE_SFLASHRDIE 5
800 #define NPCX_ESPIIE_PERACCIE 6
801 #define NPCX_ESPIIE_DFRDIE 7
802 #define NPCX_ESPIIE_VWUPDIE 8
803 #define NPCX_ESPIIE_ESPIRSTIE 9
804 #define NPCX_ESPIIE_PLTRSTIE 10
805 #define NPCX_ESPIIE_AMERRIE 15
806 #define NPCX_ESPIIE_AMDONEIE 16
807 #define NPCX_ESPIIE_BMTXDONEIE 19
808 #define NPCX_ESPIIE_PBMRXIE 20
809 #define NPCX_ESPIIE_PMSGRXIE 21
810 #define NPCX_ESPIIE_BMBURSTERRIE 22
811 #define NPCX_ESPIIE_BMBURSTDONEIE 23
812 #define NPCX_ESPIWE_IBRSTWE 0
813 #define NPCX_ESPIWE_CFGUPDWE 1
814 #define NPCX_ESPIWE_BERRWE 2
815 #define NPCX_ESPIWE_OOBRXWE 3
816 #define NPCX_ESPIWE_FLASHRXWE 4
817 #define NPCX_ESPIWE_PERACCWE 6
818 #define NPCX_ESPIWE_DFRDWE 7
819 #define NPCX_ESPIWE_VWUPDWE 8
820 #define NPCX_ESPIWE_ESPIRSTWE 9
821 #define NPCX_ESPIWE_PBMRXWE 20
822 #define NPCX_ESPIWE_PMSGRXWE 21
823 #define NPCX_ESPISTS_IBRST 0
824 #define NPCX_ESPISTS_CFGUPD 1
825 #define NPCX_ESPISTS_BERR 2
826 #define NPCX_ESPISTS_OOBRX 3
827 #define NPCX_ESPISTS_FLASHRX 4
828 #define NPCX_ESPISTS_PERACC 6
829 #define NPCX_ESPISTS_DFRD 7
830 #define NPCX_ESPISTS_VWUPD 8
831 #define NPCX_ESPISTS_ESPIRST 9
832 #define NPCX_ESPISTS_PLTRST 10
833 #define NPCX_ESPISTS_AMERR 15
834 #define NPCX_ESPISTS_AMDONE 16
835 #define NPCX_ESPISTS_VWUPDW 17
836 #define NPCX_ESPISTS_BMTXDONE 19
837 #define NPCX_ESPISTS_PBMRX 20
838 #define NPCX_ESPISTS_PMSGRX 21
839 #define NPCX_ESPISTS_BMBURSTERR 22
840 #define NPCX_ESPISTS_BMBURSTDONE 23
841 #define NPCX_ESPISTS_ESPIRST_LVL 24
842 #define NPCX_VWEVMS_WIRE FIELD(0, 4)
843 #define NPCX_VWEVMS_VALID FIELD(4, 4)
844 #define NPCX_VWEVMS_IE 18
845 #define NPCX_VWEVMS_WE 20
846 #define NPCX_VWEVSM_WIRE FIELD(0, 4)
847 #define NPCX_VWEVSM_VALID FIELD(4, 4)
848 #define NPCX_VWEVSM_BIT_VALID(n) (4+n)
849 #define NPCX_VWEVSM_HW_WIRE FIELD(24, 4)
850 #define NPCX_VWGPSM_INDEX_EN 15
851 #define NPCX_OOBCTL_OOB_FREE 0
852 #define NPCX_OOBCTL_OOB_AVAIL 1
853 #define NPCX_OOBCTL_RSTBUFHEADS 2
854 #define NPCX_OOBCTL_OOBPLSIZE FIELD(10, 3)
855 #define NPCX_FLASHCFG_FLASHBLERSSIZE FIELD(7, 3)
856 #define NPCX_FLASHCFG_FLASHPLSIZE FIELD(10, 3)
857 #define NPCX_FLASHCFG_FLASHREQSIZE FIELD(13, 3)
858 #define NPCX_FLASHCTL_FLASH_NP_FREE 0
859 #define NPCX_FLASHCTL_FLASH_TX_AVAIL 1
860 #define NPCX_FLASHCTL_STRPHDR 2
861 #define NPCX_FLASHCTL_DMATHRESH FIELD(3, 2)
862 #define NPCX_FLASHCTL_AMTSIZE FIELD(5, 8)
863 #define NPCX_FLASHCTL_RSTBUFHEADS 13
864 #define NPCX_FLASHCTL_CRCEN 14
865 #define NPCX_FLASHCTL_CHKSUMSEL 15
866 #define NPCX_FLASHCTL_AMTEN 16
867
868 #define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2 0x55
869 #define NPCX_ONLY_ESPI_REG1_LOCK_REG2 0
870 #define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG 4
871 /*
872 * Mobile System Wake-Up Control (MSWC) device registers
873 */
874 struct mswc_reg {
875 /* 0x000: MSWC Control Status 1 */
876 volatile uint8_t MSWCTL1;
877 volatile uint8_t reserved1;
878 /* 0x002: MSWC Control Status 2 */
879 volatile uint8_t MSWCTL2;
880 volatile uint8_t reserved2[5];
881 /* 0x008: Host Configuration Base Address Low */
882 volatile uint8_t HCBAL;
883 volatile uint8_t reserved3;
884 /* 0x00A: Host Configuration Base Address High */
885 volatile uint8_t HCBAH;
886 volatile uint8_t reserved4;
887 /* 0X00C: MSWC INTERRUPT ENABLE 2 */
888 volatile uint8_t MSIEN2;
889 volatile uint8_t reserved5;
890 /* 0x00E: MSWC Host Event Status 0 */
891 volatile uint8_t MSHES0;
892 volatile uint8_t reserved6;
893 /* 0x010: MSWC Host Event Interrupt Enable */
894 volatile uint8_t MSHEIE0;
895 volatile uint8_t reserved7;
896 /* 0x012: Host Control */
897 volatile uint8_t HOST_CTL;
898 volatile uint8_t reserved8;
899 /* 0x014: SMI Pulse Length */
900 volatile uint8_t SMIP_LEN;
901 volatile uint8_t reserved9;
902 /* 0x016: SCI Pulse Length */
903 volatile uint8_t SCIP_LEN;
904 volatile uint8_t reserved10[5];
905 /* 0x01C: SRID Core Access */
906 volatile uint8_t SRID_CR;
907 volatile uint8_t reserved11[3];
908 /* 0x020: SID Core Access */
909 volatile uint8_t SID_CR;
910 volatile uint8_t reserved12;
911 /* 0x022: DEVICE_ID Core Access */
912 volatile uint8_t DEVICE_ID_CR;
913 volatile uint8_t reserved13[5];
914 /* 0x028: Chip Revision Core Access */
915 volatile uint8_t CHPREV_CR;
916 volatile uint8_t reserved14[5];
917 /* 0x02E: Virtual Wire Sleep States */
918 volatile uint8_t VW_SLPST1;
919 volatile uint8_t reserved15;
920 };
921
922 /* MSWC register fields */
923 #define NPCX_MSWCTL1_HRSTOB 0
924 #define NPCS_MSWCTL1_HWPRON 1
925 #define NPCX_MSWCTL1_PLTRST_ACT 2
926 #define NPCX_MSWCTL1_VHCFGA 3
927 #define NPCX_MSWCTL1_HCFGLK 4
928 #define NPCX_MSWCTL1_PWROFFB 6
929 #define NPCX_MSWCTL1_A20MB 7
930
931 /*
932 * Shared Memory (SHM) device registers
933 */
934 struct shm_reg {
935 /* 0x000: Shared Memory Core Status */
936 volatile uint8_t SMC_STS;
937 /* 0x001: Shared Memory Core Control */
938 volatile uint8_t SMC_CTL;
939 /* 0x002: Shared Memory Host Control */
940 volatile uint8_t SHM_CTL;
941 volatile uint8_t reserved1[2];
942 /* 0x005: Indirect Memory Access Window Size */
943 volatile uint8_t IMA_WIN_SIZE;
944 volatile uint8_t reserved2;
945 /* 0x007: Shared Access Windows Size */
946 volatile uint8_t WIN_SIZE;
947 /* 0x008: Shared Access Window 1, Semaphore */
948 volatile uint8_t SHAW1_SEM;
949 /* 0x009: Shared Access Window 2, Semaphore */
950 volatile uint8_t SHAW2_SEM;
951 volatile uint8_t reserved3;
952 /* 0x00B: Indirect Memory Access, Semaphore */
953 volatile uint8_t IMA_SEM;
954 volatile uint8_t reserved4[2];
955 /* 0x00E: Shared Memory Configuration */
956 volatile uint16_t SHCFG;
957 /* 0x010: Shared Access Window 1 Write Protect */
958 volatile uint8_t WIN1_WR_PROT;
959 /* 0x011: Shared Access Window 1 Read Protect */
960 volatile uint8_t WIN1_RD_PROT;
961 /* 0x012: Shared Access Window 2 Write Protect */
962 volatile uint8_t WIN2_WR_PROT;
963 /* 0x013: Shared Access Window 2 Read Protect */
964 volatile uint8_t WIN2_RD_PROT;
965 volatile uint8_t reserved5[2];
966 /* 0x016: Indirect Memory Access Write Protect */
967 volatile uint8_t IMA_WR_PROT;
968 /* 0x017: Indirect Memory Access Read Protect */
969 volatile uint8_t IMA_RD_PROT;
970 volatile uint8_t reserved6[8];
971 /* 0x020: Shared Access Window 1 Base */
972 volatile uint32_t WIN_BASE1;
973 /* 0x024: Shared Access Window 2 Base */
974 volatile uint32_t WIN_BASE2;
975 volatile uint32_t reserved7;
976 /* 0x02C: Indirect Memory Access Base */
977 volatile uint32_t IMA_BASE;
978 volatile uint8_t reserved8[10];
979 /* 0x03A: Reset Configuration */
980 volatile uint8_t RST_CFG;
981 volatile uint8_t reserved9[5];
982 /* 0x040: Debug Port 80 Buffered Data */
983 volatile uint16_t DP80BUF;
984 /* 0x042: Debug Port 80 Status */
985 volatile uint8_t DP80STS;
986 volatile uint8_t reserved10;
987 /* 0x044: Debug Port 80 Control */
988 volatile uint8_t DP80CTL;
989 volatile uint8_t reserved11[3];
990 /* 0x048: Host_Offset in Windows 1, 2 Status */
991 volatile uint8_t HOFS_STS;
992 /* 0x049: Host_Offset in Windows 1, 2 Control */
993 volatile uint8_t HOFS_CTL;
994 /* 0x04A: Core_Offset in Window 2 Address */
995 volatile uint16_t COFS2;
996 /* 0x04C: Core_Offset in Window 1 Address */
997 volatile uint16_t COFS1;
998 volatile uint16_t reserved12;
999 };
1000
1001 /* SHM register fields */
1002 #define NPCX_SMC_STS_HRERR 0
1003 #define NPCX_SMC_STS_HWERR 1
1004 #define NPCX_SMC_STS_HSEM1W 4
1005 #define NPCX_SMC_STS_HSEM2W 5
1006 #define NPCX_SMC_STS_SHM_ACC 6
1007 #define NPCX_SMC_CTL_HERR_IE 2
1008 #define NPCX_SMC_CTL_HSEM1_IE 3
1009 #define NPCX_SMC_CTL_HSEM2_IE 4
1010 #define NPCX_SMC_CTL_ACC_IE 5
1011 #define NPCX_SMC_CTL_PREF_EN 6
1012 #define NPCX_SMC_CTL_HOSTWAIT 7
1013 #define NPCX_FLASH_SIZE_STALL_HOST 6
1014 #define NPCX_FLASH_SIZE_RD_BURST 7
1015 #define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD FIELD(0, 4)
1016 #define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD FIELD(4, 4)
1017 #define NPCX_WIN_PROT_RW1L_RP 0
1018 #define NPCX_WIN_PROT_RW1L_WP 1
1019 #define NPCX_WIN_PROT_RW1H_RP 2
1020 #define NPCX_WIN_PROT_RW1H_WP 3
1021 #define NPCX_WIN_PROT_RW2L_RP 4
1022 #define NPCX_WIN_PROT_RW2L_WP 5
1023 #define NPCX_WIN_PROT_RW2H_RP 6
1024 #define NPCX_WIN_PROT_RW2H_WP 7
1025 #define NPCX_PWIN_SIZEI_RPROT 13
1026 #define NPCX_PWIN_SIZEI_WPROT 14
1027 #define NPCX_CSEM2 6
1028 #define NPCX_CSEM3 7
1029 #define NPCX_DP80STS_FWR 5
1030 #define NPCX_DP80STS_FNE 6
1031 #define NPCX_DP80STS_FOR 7
1032 #define NPCX_DP80CTL_DP80EN 0
1033 #define NPCX_DP80CTL_SYNCEN 1
1034 #define NPCX_DP80CTL_ADV 2
1035 #define NPCX_DP80CTL_RAA 3
1036 #define NPCX_DP80CTL_RFIFO 4
1037 #define NPCX_DP80CTL_CIEN 5
1038 #define NPCX_DP80CTL_DP80_HF_CFG 7
1039 #define NPCX_DP80BUF_OFFS_FIELD FIELD(8, 3)
1040
1041 /*
1042 * Keyboard and Mouse Controller (KBC) device registers
1043 */
1044 struct kbc_reg {
1045 /* 0x000h: Host Interface Control */
1046 volatile uint8_t HICTRL;
1047 volatile uint8_t reserved1;
1048 /* 0x002h: Host Interface IRQ Control */
1049 volatile uint8_t HIIRQC;
1050 volatile uint8_t reserved2;
1051 /* 0x004h: Host Interface Keyboard/Mouse Status */
1052 volatile uint8_t HIKMST;
1053 volatile uint8_t reserved3;
1054 /* 0x006h: Host Interface Keyboard Data Out Buffer */
1055 volatile uint8_t HIKDO;
1056 volatile uint8_t reserved4;
1057 /* 0x008h: Host Interface Mouse Data Out Buffer */
1058 volatile uint8_t HIMDO;
1059 volatile uint8_t reserved5;
1060 /* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
1061 volatile uint8_t HIKMDI;
1062 /* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
1063 volatile uint8_t SHIKMDI;
1064 };
1065
1066 /* KBC register field */
1067 #define NPCX_HICTRL_OBFKIE 0
1068 #define NPCX_HICTRL_OBFMIE 1
1069 #define NPCX_HICTRL_OBECIE 2
1070 #define NPCX_HICTRL_IBFCIE 3
1071 #define NPCX_HICTRL_PMIHIE 4
1072 #define NPCX_HICTRL_PMIOCIE 5
1073 #define NPCX_HICTRL_PMICIE 6
1074 #define NPCX_HICTRL_FW_OBF 7
1075 #define NPCX_HIKMST_OBF 0
1076 #define NPCX_HIKMST_IBF 1
1077 #define NPCX_HIKMST_F0 2
1078 #define NPCX_HIKMST_A2 3
1079 #define NPCX_HIKMST_ST0 4
1080 #define NPCX_HIKMST_ST1 5
1081 #define NPCX_HIKMST_ST2 6
1082 #define NPCX_HIKMST_ST3 7
1083
1084 /*
1085 * Power Management Channel (PMCH) device registers
1086 */
1087
1088 struct pmch_reg {
1089 /* 0x000: Host Interface PM Status */
1090 volatile uint8_t HIPMST;
1091 volatile uint8_t reserved1;
1092 /* 0x002: Host Interface PM Data Out Buffer */
1093 volatile uint8_t HIPMDO;
1094 volatile uint8_t reserved2;
1095 /* 0x004: Host Interface PM Data In Buffer */
1096 volatile uint8_t HIPMDI;
1097 /* 0x005: Host Interface PM Shadow Data In Buffer */
1098 volatile uint8_t SHIPMDI;
1099 /* 0x006: Host Interface PM Data Out Buffer with SCI */
1100 volatile uint8_t HIPMDOC;
1101 volatile uint8_t reserved3;
1102 /* 0x008: Host Interface PM Data Out Buffer with SMI */
1103 volatile uint8_t HIPMDOM;
1104 volatile uint8_t reserved4;
1105 /* 0x00A: Host Interface PM Data In Buffer with SCI */
1106 volatile uint8_t HIPMDIC;
1107 volatile uint8_t reserved5;
1108 /* 0x00C: Host Interface PM Control */
1109 volatile uint8_t HIPMCTL;
1110 /* 0x00D: Host Interface PM Control 2 */
1111 volatile uint8_t HIPMCTL2;
1112 /* 0x00E: Host Interface PM Interrupt Control */
1113 volatile uint8_t HIPMIC;
1114 volatile uint8_t reserved6;
1115 /* 0x010: Host Interface PM Interrupt Enable */
1116 volatile uint8_t HIPMIE;
1117 volatile uint8_t reserved7;
1118 };
1119
1120 /* PMCH register field */
1121 #define NPCX_HIPMIE_SCIE 1
1122 #define NPCX_HIPMIE_SMIE 2
1123 #define NPCX_HIPMCTL_IBFIE 0
1124 #define NPCX_HIPMCTL_OBEIE 1
1125 #define NPCX_HIPMCTL_SCIPOL 6
1126 #define NPCX_HIPMST_OBF 0
1127 #define NPCX_HIPMST_IBF 1
1128 #define NPCX_HIPMST_F0 2
1129 #define NPCX_HIPMST_CMD 3
1130 #define NPCX_HIPMST_ST0 4
1131 #define NPCX_HIPMST_ST1 5
1132 #define NPCX_HIPMST_ST2 6
1133 #define NPCX_HIPMIC_SMIB 1
1134 #define NPCX_HIPMIC_SCIB 2
1135 #define NPCX_HIPMIC_SMIPOL 6
1136
1137 /*
1138 * Core Access to Host (C2H) device registers
1139 */
1140 struct c2h_reg {
1141 /* 0x000: Indirect Host I/O Address */
1142 volatile uint16_t IHIOA;
1143 /* 0x002: Indirect Host Data */
1144 volatile uint8_t IHD;
1145 volatile uint8_t reserved1;
1146 /* 0x004: Lock Host Access */
1147 volatile uint16_t LKSIOHA;
1148 /* 0x006: Access Lock Violation */
1149 volatile uint16_t SIOLV;
1150 /* 0x008: Core-to-Host Modules Access Enable */
1151 volatile uint16_t CRSMAE;
1152 /* 0x00A: Module Control */
1153 volatile uint8_t SIBCTRL;
1154 volatile uint8_t reserved3;
1155 };
1156
1157 /* C2H register fields */
1158 #define NPCX_LKSIOHA_LKCFG 0
1159 #define NPCX_LKSIOHA_LKSPHA 2
1160 #define NPCX_LKSIOHA_LKHIKBD 11
1161 #define NPCX_CRSMAE_CFGAE 0
1162 #define NPCX_CRSMAE_HIKBDAE 11
1163 #define NPCX_SIOLV_SPLV 2
1164 #define NPCX_SIBCTRL_CSAE 0
1165 #define NPCX_SIBCTRL_CSRD 1
1166 #define NPCX_SIBCTRL_CSWR 2
1167
1168 /*
1169 * SMBUS (SMB) device registers
1170 */
1171 struct smb_reg {
1172 /* 0x000: SMB Serial Data */
1173 volatile uint8_t SMBSDA;
1174 volatile uint8_t reserved1;
1175 /* 0x002: SMB Status */
1176 volatile uint8_t SMBST;
1177 volatile uint8_t reserved2;
1178 /* 0x004: SMB Control Status */
1179 volatile uint8_t SMBCST;
1180 volatile uint8_t reserved3;
1181 /* 0x006: SMB Control 1 */
1182 volatile uint8_t SMBCTL1;
1183 volatile uint8_t reserved4;
1184 /* 0x008: SMB Own Address */
1185 volatile uint8_t SMBADDR1;
1186 volatile uint8_t reserved5;
1187 /* 0x00A: SMB Control 2 */
1188 volatile uint8_t SMBCTL2;
1189 volatile uint8_t reserved6;
1190 /* 0x00C: SMB Own Address */
1191 volatile uint8_t SMBADDR2;
1192 volatile uint8_t reserved7;
1193 /* 0x00E: SMB Control 3 */
1194 volatile uint8_t SMBCTL3;
1195 /* 0x00F: SMB Bus Timeout */
1196 volatile uint8_t SMBT_OUT;
1197 union {
1198 /* Bank 0 */
1199 struct {
1200 /* 0x010: SMB Own Address 3 */
1201 volatile uint8_t SMBADDR3;
1202 /* 0x011: SMB Own Address 7 */
1203 volatile uint8_t SMBADDR7;
1204 /* 0x012: SMB Own Address 4 */
1205 volatile uint8_t SMBADDR4;
1206 /* 0x013: SMB Own Address 8 */
1207 volatile uint8_t SMBADDR8;
1208 /* 0x014: SMB Own Address 5 */
1209 volatile uint8_t SMBADDR5;
1210 volatile uint8_t reserved8;
1211 /* 0x016: SMB Own Address 6 */
1212 volatile uint8_t SMBADDR6;
1213 volatile uint8_t reserved9;
1214 /* 0x018: SMB Control Status 2 */
1215 volatile uint8_t SMBCST2;
1216 /* 0x019: SMB Control Status 3 */
1217 volatile uint8_t SMBCST3;
1218 /* 0x01A: SMB Control 4 */
1219 volatile uint8_t SMBCTL4;
1220 volatile uint8_t reserved10;
1221 /* 0x01C: SMB SCL Low Time */
1222 volatile uint8_t SMBSCLLT;
1223 /* 0x01D: SMB FIFO Control */
1224 volatile uint8_t SMBFIF_CTL;
1225 /* 0x01E: SMB SCL High Time */
1226 volatile uint8_t SMBSCLHT;
1227 volatile uint8_t reserved11;
1228 };
1229 /* Bank 1 */
1230 struct {
1231 /* 0x010: SMB FIFO Control */
1232 volatile uint8_t SMBFIF_CTS;
1233 volatile uint8_t reserved12;
1234 /* 0x012: SMB Tx-FIFO Control */
1235 volatile uint8_t SMBTXF_CTL;
1236 volatile uint8_t reserved13;
1237 /* 0x014: SMB Bus Timeout */
1238 volatile uint8_t SMB_T_OUT;
1239 volatile uint8_t reserved14[3];
1240 /* 0x018: SMB Control Status 2 (FIFO) */
1241 volatile uint8_t SMBCST2_FIFO;
1242 /* 0x019: SMB Control Status 3 (FIFO) */
1243 volatile uint8_t SMBCST3_FIFO;
1244 /* 0x01A: SMB Tx-FIFO Status */
1245 volatile uint8_t SMBTXF_STS;
1246 volatile uint8_t reserved15;
1247 /* 0x01C: SMB Rx-FIFO Status */
1248 volatile uint8_t SMBRXF_STS;
1249 volatile uint8_t reserved16;
1250 /* 0x01E: SMB Rx-FIFO Control */
1251 volatile uint8_t SMBRXF_CTL;
1252 volatile uint8_t reserved17[1];
1253 };
1254 };
1255 };
1256
1257 /* SMB register fields */
1258 #define NPCX_SMBST_XMIT 0
1259 #define NPCX_SMBST_MASTER 1
1260 #define NPCX_SMBST_NMATCH 2
1261 #define NPCX_SMBST_STASTR 3
1262 #define NPCX_SMBST_NEGACK 4
1263 #define NPCX_SMBST_BER 5
1264 #define NPCX_SMBST_SDAST 6
1265 #define NPCX_SMBST_SLVSTP 7
1266 #define NPCX_SMBCST_BUSY 0
1267 #define NPCX_SMBCST_BB 1
1268 #define NPCX_SMBCST_MATCH 2
1269 #define NPCX_SMBCST_GCMATCH 3
1270 #define NPCX_SMBCST_TSDA 4
1271 #define NPCX_SMBCST_TGSCL 5
1272 #define NPCX_SMBCST_MATCHAF 6
1273 #define NPCX_SMBCST_ARPMATCH 7
1274 #define NPCX_SMBCST2_MATCHA1F 0
1275 #define NPCX_SMBCST2_MATCHA2F 1
1276 #define NPCX_SMBCST2_MATCHA3F 2
1277 #define NPCX_SMBCST2_MATCHA4F 3
1278 #define NPCX_SMBCST2_MATCHA5F 4
1279 #define NPCX_SMBCST2_MATCHA6F 5
1280 #define NPCX_SMBCST2_MATCHA7F 6
1281 #define NPCX_SMBCST2_INTSTS 7
1282 #define NPCX_SMBCST3_MATCHA8F 0
1283 #define NPCX_SMBCST3_MATCHA9F 1
1284 #define NPCX_SMBCST3_MATCHA10F 2
1285 #define NPCX_SMBCTL1_START 0
1286 #define NPCX_SMBCTL1_STOP 1
1287 #define NPCX_SMBCTL1_INTEN 2
1288 #define NPCX_SMBCTL1_ACK 4
1289 #define NPCX_SMBCTL1_GCMEN 5
1290 #define NPCX_SMBCTL1_NMINTE 6
1291 #define NPCX_SMBCTL1_STASTRE 7
1292 #define NPCX_SMBCTL2_ENABLE 0
1293 #define NPCX_SMBCTL2_SCLFRQ0_6_FIELD FIELD(1, 7)
1294 #define NPCX_SMBCTL3_ARPMEN 2
1295 #define NPCX_SMBCTL3_SCLFRQ7_8_FIELD FIELD(0, 2)
1296 #define NPCX_SMBCTL3_IDL_START 3
1297 #define NPCX_SMBCTL3_400K 4
1298 #define NPCX_SMBCTL3_BNK_SEL 5
1299 #define NPCX_SMBCTL3_SDA_LVL 6
1300 #define NPCX_SMBCTL3_SCL_LVL 7
1301 #define NPCX_SMBCTL4_HLDT_FIELD FIELD(0, 6)
1302 #define NPCX_SMBCTL4_LVL_WE 7
1303 #define NPCX_SMBADDR1_SAEN 7
1304 #define NPCX_SMBADDR2_SAEN 7
1305 #define NPCX_SMBADDR3_SAEN 7
1306 #define NPCX_SMBADDR4_SAEN 7
1307 #define NPCX_SMBADDR5_SAEN 7
1308 #define NPCX_SMBADDR6_SAEN 7
1309 #define NPCX_SMBADDR7_SAEN 7
1310 #define NPCX_SMBADDR8_SAEN 7
1311 #define NPCX_SMBSEL_SMB4SEL 4
1312 #define NPCX_SMBSEL_SMB5SEL 5
1313 #define NPCX_SMBSEL_SMB6SEL 6
1314 #define NPCX_SMBFIF_CTS_RXF_TXE 1
1315 #define NPCX_SMBFIF_CTS_CLR_FIFO 6
1316 #define NPCX_SMBFIF_CTL_FIFO_EN 4
1317 #define NPCX_SMBRXF_STS_RX_THST 6
1318
1319 /* RX FIFO threshold */
1320 #define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
1321 #define NPCX_SMBRXF_CTL_LAST 7
1322
1323 /*
1324 * Internal 32-bit Timer (ITIM32) device registers
1325 */
1326 struct itim32_reg {
1327 volatile uint8_t reserved1;
1328 /* 0x001: Internal 32-bit Timer Prescaler */
1329 volatile uint8_t ITPRE32;
1330 volatile uint8_t reserved2[2];
1331 /* 0x004: Internal 32-bit Timer Control and Status */
1332 volatile uint8_t ITCTS32;
1333 volatile uint8_t reserved3[3];
1334 /* 0x008: Internal 32-Bit Timer Counter */
1335 volatile uint32_t ITCNT32;
1336 };
1337
1338 /*
1339 * Internal 64-bit Timer (ITIM54) device registers
1340 */
1341 struct itim64_reg {
1342 volatile uint8_t reserved1;
1343 /* 0x001: Internal 64-bit Timer Prescaler */
1344 volatile uint8_t ITPRE64;
1345 volatile uint8_t reserved2[2];
1346 /* 0x004: Internal 64-bit Timer Control and Status */
1347 volatile uint8_t ITCTS64;
1348 volatile uint8_t reserved3[3];
1349 /* 0x008: Internal 32-Bit Timer Counter */
1350 volatile uint32_t ITCNT64L;
1351 /* 0x00C: Internal 32-Bit Timer Counter */
1352 volatile uint32_t ITCNT64H;
1353 };
1354
1355 /* ITIM register fields */
1356 #define NPCX_ITCTSXX_TO_STS 0
1357 #define NPCX_ITCTSXX_TO_IE 2
1358 #define NPCX_ITCTSXX_TO_WUE 3
1359 #define NPCX_ITCTSXX_CKSEL 4
1360 #define NPCX_ITCTSXX_ITEN 7
1361
1362 /*
1363 * Tachometer (TACH) Sensor device registers
1364 */
1365 struct tach_reg {
1366 /* 0x000: Timer/Counter 1 */
1367 volatile uint16_t TCNT1;
1368 /* 0x002: Reload/Capture A */
1369 volatile uint16_t TCRA;
1370 /* 0x004: Reload/Capture B */
1371 volatile uint16_t TCRB;
1372 /* 0x006: Timer/Counter 2 */
1373 volatile uint16_t TCNT2;
1374 /* 0x008: Clock Prescaler */
1375 volatile uint8_t TPRSC;
1376 volatile uint8_t reserved1;
1377 /* 0x00A: Clock Unit Control */
1378 volatile uint8_t TCKC;
1379 volatile uint8_t reserved2;
1380 /* 0x00C: Timer Mode Control */
1381 volatile uint8_t TMCTRL;
1382 volatile uint8_t reserved3;
1383 /* 0x00E: Timer Event Control */
1384 volatile uint8_t TECTRL;
1385 volatile uint8_t reserved4;
1386 /* 0x010: Timer Event Clear */
1387 volatile uint8_t TECLR;
1388 volatile uint8_t reserved5;
1389 /* 0x012: Timer Interrupt Enable */
1390 volatile uint8_t TIEN;
1391 volatile uint8_t reserved6;
1392 /* 0x014: Compare A */
1393 volatile uint16_t TCPA;
1394 /* 0x016: Compare B */
1395 volatile uint16_t TCPB;
1396 /* 0x018: Compare Configuration */
1397 volatile uint8_t TCPCFG;
1398 volatile uint8_t reserved7;
1399 /* 0x01A: Timer Wake-Up Enable */
1400 volatile uint8_t TWUEN;
1401 volatile uint8_t reserved8;
1402 /* 0x01C: Timer Configuration */
1403 volatile uint8_t TCFG;
1404 volatile uint8_t reserved9;
1405 };
1406
1407 /* TACH register fields */
1408 #define NPCX_TCKC_LOW_PWR 7
1409 #define NPCX_TCKC_PLS_ACC_CLK 6
1410 #define NPCX_TCKC_C1CSEL_FIELD FIELD(0, 3)
1411 #define NPCX_TCKC_C2CSEL_FIELD FIELD(3, 3)
1412 #define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
1413 #define NPCX_TMCTRL_TAEN 5
1414 #define NPCX_TMCTRL_TBEN 6
1415 #define NPCX_TMCTRL_TAEDG 3
1416 #define NPCX_TMCTRL_TBEDG 4
1417 #define NPCX_TCFG_TADBEN 6
1418 #define NPCX_TCFG_TBDBEN 7
1419 #define NPCX_TECTRL_TAPND 0
1420 #define NPCX_TECTRL_TBPND 1
1421 #define NPCX_TECTRL_TCPND 2
1422 #define NPCX_TECTRL_TDPND 3
1423 #define NPCX_TECLR_TACLR 0
1424 #define NPCX_TECLR_TBCLR 1
1425 #define NPCX_TECLR_TCCLR 2
1426 #define NPCX_TECLR_TDCLR 3
1427 #define NPCX_TIEN_TAIEN 0
1428 #define NPCX_TIEN_TBIEN 1
1429 #define NPCX_TIEN_TCIEN 2
1430 #define NPCX_TIEN_TDIEN 3
1431 #define NPCX_TWUEN_TAWEN 0
1432 #define NPCX_TWUEN_TBWEN 1
1433 #define NPCX_TWUEN_TCWEN 2
1434 #define NPCX_TWUEN_TDWEN 3
1435
1436 /* Debug Interface registers */
1437 struct dbg_reg {
1438 /* 0x000: Debug Control */
1439 volatile uint8_t DBGCTRL;
1440 volatile uint8_t reserved1;
1441 /* 0x002: Debug Freeze Enable 1 */
1442 volatile uint8_t DBGFRZEN1;
1443 /* 0x003: Debug Freeze Enable 2 */
1444 volatile uint8_t DBGFRZEN2;
1445 /* 0x004: Debug Freeze Enable 3 */
1446 volatile uint8_t DBGFRZEN3;
1447 /* 0x005: Debug Freeze Enable 4 */
1448 volatile uint8_t DBGFRZEN4;
1449 };
1450 /* Debug Interface registers fields */
1451 #define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
1452
1453 /* PS/2 Interface registers */
1454 struct ps2_reg {
1455 /* 0x000: PS/2 Data */
1456 volatile uint8_t PSDAT;
1457 volatile uint8_t reserved1;
1458 /* 0x002: PS/2 Status */
1459 volatile uint8_t PSTAT;
1460 volatile uint8_t reserved2;
1461 /* 0x004: PS/2 Control */
1462 volatile uint8_t PSCON;
1463 volatile uint8_t reserved3;
1464 /* 0x006: PS/2 Output Signal */
1465 volatile uint8_t PSOSIG;
1466 volatile uint8_t reserved4;
1467 /* 0x008: PS/2 Input Signal */
1468 volatile uint8_t PSISIG;
1469 volatile uint8_t reserved5;
1470 /* 0x00A: PS/2 Interrupt Enable */
1471 volatile uint8_t PSIEN;
1472 volatile uint8_t reserved6;
1473 };
1474
1475 /* PS/2 Interface registers fields */
1476 #define NPCX_PSTAT_SOT 0
1477 #define NPCX_PSTAT_EOT 1
1478 #define NPCX_PSTAT_PERR 2
1479 #define NPCX_PSTAT_ACH FIELD(3, 3)
1480 #define NPCX_PSTAT_RFERR 6
1481
1482 #define NPCX_PSCON_EN 0
1483 #define NPCX_PSCON_XMT 1
1484 #define NPCX_PSCON_HDRV FIELD(2, 2)
1485 #define NPCX_PSCON_IDB FIELD(4, 3)
1486 #define NPCX_PSCON_WPUED 7
1487
1488 #define NPCX_PSOSIG_WDAT0 0
1489 #define NPCX_PSOSIG_WDAT1 1
1490 #define NPCX_PSOSIG_WDAT2 2
1491 #define NPCX_PSOSIG_CLK0 3
1492 #define NPCX_PSOSIG_CLK1 4
1493 #define NPCX_PSOSIG_CLK2 5
1494 #define NPCX_PSOSIG_WDAT3 6
1495 #define NPCX_PSOSIG_CLK3 7
1496 #define NPCX_PSOSIG_CLK(n) (((n) < 3) ? ((n) + 3) : 7)
1497 #define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
1498 #define NPCX_PSOSIG_CLK_MASK_ALL \
1499 (BIT(NPCX_PSOSIG_CLK0) | \
1500 BIT(NPCX_PSOSIG_CLK1) | \
1501 BIT(NPCX_PSOSIG_CLK2) | \
1502 BIT(NPCX_PSOSIG_CLK3))
1503
1504 #define NPCX_PSIEN_SOTIE 0
1505 #define NPCX_PSIEN_EOTIE 1
1506 #define NPCX_PSIEN_PS2_WUE 4
1507 #define NPCX_PSIEN_PS2_CLK_SEL 7
1508
1509 /* Flash Interface Unit (FIU) device registers */
1510 struct fiu_reg {
1511 volatile uint8_t reserved1;
1512 /* 0x001: Burst Configuration */
1513 volatile uint8_t BURST_CFG;
1514 /* 0x002: FIU Response Configuration */
1515 volatile uint8_t RESP_CFG;
1516 volatile uint8_t reserved2[17];
1517 /* 0x014: SPI Flash Configuration */
1518 volatile uint8_t SPI_FL_CFG;
1519 volatile uint8_t reserved3;
1520 /* 0x016: UMA Code Byte */
1521 volatile uint8_t UMA_CODE;
1522 /* 0x017: UMA Address Byte 0 */
1523 volatile uint8_t UMA_AB0;
1524 /* 0x018: UMA Address Byte 1 */
1525 volatile uint8_t UMA_AB1;
1526 /* 0x019: UMA Address Byte 2 */
1527 volatile uint8_t UMA_AB2;
1528 /* 0x01A: UMA Data Byte 0 */
1529 volatile uint8_t UMA_DB0;
1530 /* 0x01B: UMA Data Byte 1 */
1531 volatile uint8_t UMA_DB1;
1532 /* 0x01C: UMA Data Byte 2 */
1533 volatile uint8_t UMA_DB2;
1534 /* 0x01D: UMA Data Byte 3 */
1535 volatile uint8_t UMA_DB3;
1536 /* 0x01E: UMA Control and Status */
1537 volatile uint8_t UMA_CTS;
1538 /* 0x01F: UMA Extended Control and Status */
1539 volatile uint8_t UMA_ECTS;
1540 /* 0x020: UMA Data Bytes 0-3 */
1541 volatile uint32_t UMA_DB0_3;
1542 volatile uint8_t reserved4[2];
1543 /* 0x026: CRC Control Register */
1544 volatile uint8_t CRCCON;
1545 /* 0x027: CRC Entry Register */
1546 volatile uint8_t CRCENT;
1547 /* 0x028: CRC Initialization and Result Register */
1548 volatile uint32_t CRCRSLT;
1549 volatile uint8_t reserved5[4];
1550 /* 0x030: FIU Read Command */
1551 volatile uint8_t FIU_RD_CMD;
1552 volatile uint8_t reserved6;
1553 /* 0x032: FIU Dummy Cycles */
1554 volatile uint8_t FIU_DMM_CYC;
1555 /* 0x033: FIU Extended Configuration */
1556 volatile uint8_t FIU_EXT_CFG;
1557 #if defined(CONFIG_SOC_SERIES_NPCX9)
1558 /* 0x034: UMA address byte 0-3 */
1559 volatile uint32_t UMA_AB0_3;
1560 /* 0x038-0x3C */
1561 volatile uint8_t reserved8[5];
1562 /* 0x03D: SPI Device */
1563 volatile uint8_t SPI1_DEV;
1564 /* 0x03E-0x3F */
1565 volatile uint8_t reserved9[2];
1566 #elif defined(CONFIG_SOC_SERIES_NPCX4)
1567 /* 0x034: UMA address byte 0-3 */
1568 volatile uint32_t UMA_AB0_3;
1569 /* 0x038-0x3B */
1570 volatile uint8_t reserved8[4];
1571 /* 0x03C: SPI Device */
1572 volatile uint8_t SPI_DEV;
1573 /* 0x03D */
1574 volatile uint8_t reserved9;
1575 /* 0x03E */
1576 volatile uint8_t SPI_DEV_SIZE;
1577 /* 0x03F */
1578 volatile uint8_t reserved10;
1579 #endif
1580 };
1581
1582 /* FIU register fields */
1583 #define NPCX_BURST_CFG_SPI_DEV_SEL FIELD(4, 2)
1584 #define NPCX_RESP_CFG_IAD_EN 0
1585 #define NPCX_RESP_CFG_DEV_SIZE_EX 2
1586 #define NPCX_RESP_CFG_QUAD_EN 3
1587 #define NPCX_SPI_FL_CFG_RD_MODE FIELD(6, 2)
1588 #define NPCX_UMA_CTS_A_SIZE 3
1589 #define NPCX_UMA_CTS_C_SIZE 4
1590 #define NPCX_UMA_CTS_RD_WR 5
1591 #define NPCX_UMA_CTS_DEV_NUM 6
1592 #define NPCX_UMA_CTS_EXEC_DONE 7
1593 #define NPCX_UMA_ECTS_SW_CS0 0
1594 #define NPCX_UMA_ECTS_SW_CS1 1
1595 #define NPCX_UMA_ECTS_SEC_CS 2
1596 #define NPCX_UMA_ECTS_UMA_LOCK 3
1597 #define NPCX_UMA_ECTS_UMA_ADDR_SIZE FIELD(4, 3)
1598 #define NPCX_SPI1_DEV_FOUR_BADDR_CS10 6
1599 #define NPCX_SPI1_DEV_FOUR_BADDR_CS11 7
1600 #define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
1601 #if defined(CONFIG_SOC_SERIES_NPCX9)
1602 #define NPCX_FIU_EXT_CFG_SPI1_2DEV 7
1603 #else
1604 #define NPCX_FIU_EXT_CFG_SPI1_2DEV 6
1605 #endif
1606 #define NPCX_FIU_EXT_CFG_SET_DMM_EN 2
1607 #define NPCX_FIU_EXT_CFG_SET_CMD_EN 1
1608 #define NPCX_SPI_DEV_NADDRB FIELD(5, 3)
1609
1610 #define NPCX_MSR_IE_CFG_UMA_BLOCK 3
1611
1612 /* UMA fields selections */
1613 #define UMA_FLD_ADDR BIT(NPCX_UMA_CTS_A_SIZE) /* 3-bytes ADR field */
1614 #define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE) /* No 1-Byte CMD field */
1615 #define UMA_FLD_WRITE BIT(NPCX_UMA_CTS_RD_WR) /* Write transaction */
1616 #define UMA_FLD_SHD_SL BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
1617 #define UMA_FLD_EXEC BIT(NPCX_UMA_CTS_EXEC_DONE)
1618
1619 #define UMA_FIELD_DATA_1 0x01
1620 #define UMA_FIELD_DATA_2 0x02
1621 #define UMA_FIELD_DATA_3 0x03
1622 #define UMA_FIELD_DATA_4 0x04
1623
1624 /* UMA code for transaction */
1625 #define UMA_CODE_CMD_ONLY (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
1626 #define UMA_CODE_CMD_ADR (UMA_FLD_EXEC | UMA_FLD_ADDR | \
1627 UMA_FLD_SHD_SL)
1628 #define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
1629 UMA_FLD_SHD_SL)
1630 #define UMA_CODE_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
1631 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1632 #define UMA_CODE_CMD_WR_ONLY (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1633 UMA_FLD_SHD_SL)
1634 #define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1635 UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
1636 #define UMA_CODE_CMD_WR_ADR (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
1637 UMA_FLD_SHD_SL)
1638
1639 #define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
1640 UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
1641 UMA_FLD_SHD_SL)
1642
1643 /* Platform Environment Control Interface (PECI) device registers */
1644 struct peci_reg {
1645 /* 0x000: PECI Control Status */
1646 volatile uint8_t PECI_CTL_STS;
1647 /* 0x001: PECI Read Length */
1648 volatile uint8_t PECI_RD_LENGTH;
1649 /* 0x002: PECI Address */
1650 volatile uint8_t PECI_ADDR;
1651 /* 0x003: PECI Command */
1652 volatile uint8_t PECI_CMD;
1653 /* 0x004: PECI Control 2 */
1654 volatile uint8_t PECI_CTL2;
1655 /* 0x005: PECI Index */
1656 volatile uint8_t PECI_INDEX;
1657 /* 0x006: PECI Index Data */
1658 volatile uint8_t PECI_IDATA;
1659 /* 0x007: PECI Write Length */
1660 volatile uint8_t PECI_WR_LENGTH;
1661 volatile uint8_t reserved1[3];
1662 /* 0x00B: PECI Write FCS */
1663 volatile uint8_t PECI_WR_FCS;
1664 /* 0x00C: PECI Read FCS */
1665 volatile uint8_t PECI_RD_FCS;
1666 /* 0x00D: PECI Assured Write FCS */
1667 volatile uint8_t PECI_AW_FCS;
1668 volatile uint8_t reserved2;
1669 /* 0x00F: PECI Transfer Rate */
1670 volatile uint8_t PECI_RATE;
1671 /* 0x010 - 0x04F: PECI Data In/Out */
1672 union {
1673 volatile uint8_t PECI_DATA_IN[64];
1674 volatile uint8_t PECI_DATA_OUT[64];
1675 };
1676 };
1677
1678 /* PECI register fields */
1679 #define NPCX_PECI_CTL_STS_START_BUSY 0
1680 #define NPCX_PECI_CTL_STS_DONE 1
1681 #define NPCX_PECI_CTL_STS_CRC_ERR 3
1682 #define NPCX_PECI_CTL_STS_ABRT_ERR 4
1683 #define NPCX_PECI_CTL_STS_AWFCS_EB 5
1684 #define NPCX_PECI_CTL_STS_DONE_EN 6
1685 #define NPCX_PECI_RATE_MAX_BIT_RATE FIELD(0, 5)
1686 #define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
1687 /* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
1688 #define PECI_MAX_BIT_RATE_VALID_MIN 0x05
1689 #define PECI_HIGH_SPEED_MIN_VAL 0x07
1690
1691 #define NPCX_PECI_RATE_EHSP 6
1692
1693 /* KBS (Keyboard Scan) device registers */
1694 struct kbs_reg {
1695 volatile uint8_t reserved1[4];
1696 /* 0x004: Keyboard Scan In */
1697 volatile uint8_t KBSIN;
1698 /* 0x005: Keyboard Scan In Pull-Up Enable */
1699 volatile uint8_t KBSINPU;
1700 /* 0x006: Keyboard Scan Out 0 */
1701 volatile uint16_t KBSOUT0;
1702 /* 0x008: Keyboard Scan Out 1 */
1703 volatile uint16_t KBSOUT1;
1704 /* 0x00A: Keyboard Scan Buffer Index */
1705 volatile uint8_t KBS_BUF_INDX;
1706 /* 0x00B: Keyboard Scan Buffer Data */
1707 volatile uint8_t KBS_BUF_DATA;
1708 /* 0x00C: Keyboard Scan Event */
1709 volatile uint8_t KBSEVT;
1710 /* 0x00D: Keyboard Scan Control */
1711 volatile uint8_t KBSCTL;
1712 /* 0x00E: Keyboard Scan Configuration Index */
1713 volatile uint8_t KBS_CFG_INDX;
1714 /* 0x00F: Keyboard Scan Configuration Data */
1715 volatile uint8_t KBS_CFG_DATA;
1716 };
1717
1718 /* KBS register fields */
1719 #define NPCX_KBSBUFINDX 0
1720 #define NPCX_KBSEVT_KBSDONE 0
1721 #define NPCX_KBSEVT_KBSERR 1
1722 #define NPCX_KBSCTL_START 0
1723 #define NPCX_KBSCTL_KBSMODE 1
1724 #define NPCX_KBSCTL_KBSIEN 2
1725 #define NPCX_KBSCTL_KBSINC 3
1726 #define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
1727 #define NPCX_KBSCFGINDX 0
1728 /* Index of 'Automatic Scan' configuration register */
1729 #define KBS_CFG_INDX_DLY1 0 /* Keyboard Scan Delay T1 Byte */
1730 #define KBS_CFG_INDX_DLY2 1 /* Keyboard Scan Delay T2 Byte */
1731 #define KBS_CFG_INDX_RTYTO 2 /* Keyboard Scan Retry Timeout */
1732 #define KBS_CFG_INDX_CNUM 3 /* Keyboard Scan Columns Number */
1733 #define KBS_CFG_INDX_CDIV 4 /* Keyboard Scan Clock Divisor */
1734
1735 /* SHI (Serial Host Interface) registers */
1736 struct shi_reg {
1737 volatile uint8_t reserved1;
1738 /* 0x001: SHI Configuration 1 */
1739 volatile uint8_t SHICFG1;
1740 /* 0x002: SHI Configuration 2 */
1741 volatile uint8_t SHICFG2;
1742 volatile uint8_t reserved2[2];
1743 /* 0x005: Event Enable */
1744 volatile uint8_t EVENABLE;
1745 /* 0x006: Event Status */
1746 volatile uint8_t EVSTAT;
1747 /* 0x007: SHI Capabilities */
1748 volatile uint8_t CAPABILITY;
1749 /* 0x008: Status */
1750 volatile uint8_t STATUS;
1751 volatile uint8_t reserved3;
1752 /* 0x00A: Input Buffer Status */
1753 volatile uint8_t IBUFSTAT;
1754 /* 0x00B: Output Buffer Status */
1755 volatile uint8_t OBUFSTAT;
1756 /* 0x00C: SHI Configuration 3 */
1757 volatile uint8_t SHICFG3;
1758 /* 0x00D: SHI Configuration 4 */
1759 volatile uint8_t SHICFG4;
1760 /* 0x00E: SHI Configuration 5 */
1761 volatile uint8_t SHICFG5;
1762 /* 0x00F: Event Status 2 */
1763 volatile uint8_t EVSTAT2;
1764 /* 0x010: Event Enable 2 */
1765 volatile uint8_t EVENABLE2;
1766 volatile uint8_t reserved4[15];
1767 /* 0x20~0x9F: Output Buffer */
1768 volatile uint8_t OBUF[128];
1769 /* 0xA0~0x11F: Input Buffer */
1770 volatile uint8_t IBUF[128];
1771 };
1772
1773 /* SHI register fields */
1774 #define NPCX_SHICFG1_EN 0
1775 #define NPCX_SHICFG1_MODE 1
1776 #define NPCX_SHICFG1_WEN 2
1777 #define NPCX_SHICFG1_AUTIBF 3
1778 #define NPCX_SHICFG1_AUTOBE 4
1779 #define NPCX_SHICFG1_DAS 5
1780 #define NPCX_SHICFG1_CPOL 6
1781 #define NPCX_SHICFG1_IWRAP 7
1782 #define NPCX_SHICFG2_SIMUL 0
1783 #define NPCX_SHICFG2_BUSY 1
1784 #define NPCX_SHICFG2_ONESHOT 2
1785 #define NPCX_SHICFG2_SLWU 3
1786 #define NPCX_SHICFG2_REEN 4
1787 #define NPCX_SHICFG2_RESTART 5
1788 #define NPCX_SHICFG2_REEVEN 6
1789 #define NPCX_EVENABLE_OBEEN 0
1790 #define NPCX_EVENABLE_OBHEEN 1
1791 #define NPCX_EVENABLE_IBFEN 2
1792 #define NPCX_EVENABLE_IBHFEN 3
1793 #define NPCX_EVENABLE_EOREN 4
1794 #define NPCX_EVENABLE_EOWEN 5
1795 #define NPCX_EVENABLE_STSREN 6
1796 #define NPCX_EVENABLE_IBOREN 7
1797 #define NPCX_EVSTAT_OBE 0
1798 #define NPCX_EVSTAT_OBHE 1
1799 #define NPCX_EVSTAT_IBF 2
1800 #define NPCX_EVSTAT_IBHF 3
1801 #define NPCX_EVSTAT_EOR 4
1802 #define NPCX_EVSTAT_EOW 5
1803 #define NPCX_EVSTAT_STSR 6
1804 #define NPCX_EVSTAT_IBOR 7
1805 #define NPCX_STATUS_OBES 6
1806 #define NPCX_STATUS_IBFS 7
1807 #define NPCX_SHICFG3_OBUFLVLDIS 7
1808 #define NPCX_SHICFG4_IBUFLVLDIS 7
1809 #define NPCX_SHICFG5_IBUFLVL2 FIELD(0, 6)
1810 #define NPCX_SHICFG5_IBUFLVL2DIS 7
1811 #define NPCX_EVSTAT2_IBHF2 0
1812 #define NPCX_EVSTAT2_CSNRE 1
1813 #define NPCX_EVSTAT2_CSNFE 2
1814 #define NPCX_EVENABLE2_IBHF2EN 0
1815 #define NPCX_EVENABLE2_CSNREEN 1
1816 #define NPCX_EVENABLE2_CSNFEEN 2
1817
1818 #endif /* _NUVOTON_NPCX_REG_DEF_H */
1819
