1 /* 2 * Copyright 2022-2024 NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_SOC_NXP_S32_S32ZE_PINCTRL_SOC_H_ 8 #define ZEPHYR_SOC_NXP_S32_S32ZE_PINCTRL_SOC_H_ 9 10 #include <zephyr/dt-bindings/pinctrl/nxp-s32-pinctrl.h> 11 #include <zephyr/sys/util.h> 12 13 #include "../common/siul2_pinctrl.h" 14 15 /* SIUL2 Multiplexed Signal Configuration */ 16 #define SIUL2_MSCR_SSS_MASK GENMASK(2, 0) 17 #define SIUL2_MSCR_SSS(v) FIELD_PREP(SIUL2_MSCR_SSS_MASK, (v)) 18 #define SIUL2_MSCR_SMC_MASK GENMASK(7, 4) 19 #define SIUL2_MSCR_SMC(v) FIELD_PREP(SIUL2_MSCR_SMC_MASK, (v)) 20 #define SIUL2_MSCR_TRC_MASK BIT(8) 21 #define SIUL2_MSCR_TRC(v) FIELD_PREP(SIUL2_MSCR_TRC_MASK, (v)) 22 #define SIUL2_MSCR_RCVR_MASK BIT(10) 23 #define SIUL2_MSCR_RCVR(v) FIELD_PREP(SIUL2_MSCR_RCVR_MASK, (v)) 24 #define SIUL2_MSCR_CREF_MASK BIT(11) 25 #define SIUL2_MSCR_CREF(v) FIELD_PREP(SIUL2_MSCR_CREF_MASK, (v)) 26 #define SIUL2_MSCR_PUS_MASK BIT(12) 27 #define SIUL2_MSCR_PUS(v) FIELD_PREP(SIUL2_MSCR_PUS_MASK, (v)) 28 #define SIUL2_MSCR_PUE_MASK BIT(13) 29 #define SIUL2_MSCR_PUE(v) FIELD_PREP(SIUL2_MSCR_PUE_MASK, (v)) 30 #define SIUL2_MSCR_SRE_MASK GENMASK(16, 14) 31 #define SIUL2_MSCR_SRE(v) FIELD_PREP(SIUL2_MSCR_SRE_MASK, (v)) 32 #define SIUL2_MSCR_RXCB_MASK BIT(17) 33 #define SIUL2_MSCR_RXCB(v) FIELD_PREP(SIUL2_MSCR_RXCB_MASK, (v)) 34 #define SIUL2_MSCR_IBE_MASK BIT(19) 35 #define SIUL2_MSCR_IBE(v) FIELD_PREP(SIUL2_MSCR_IBE_MASK, (v)) 36 #define SIUL2_MSCR_ODE_MASK BIT(20) 37 #define SIUL2_MSCR_ODE(v) FIELD_PREP(SIUL2_MSCR_ODE_MASK, (v)) 38 #define SIUL2_MSCR_OBE_MASK BIT(21) 39 #define SIUL2_MSCR_OBE(v) FIELD_PREP(SIUL2_MSCR_OBE_MASK, (v)) 40 /* SIUL2 Input Multiplexed Signal Configuration */ 41 #define SIUL2_IMCR_SSS_MASK GENMASK(2, 0) 42 #define SIUL2_IMCR_SSS(v) FIELD_PREP(SIUL2_IMCR_SSS_MASK, (v)) 43 44 #define NXP_S32_PINMUX_INIT(group, value) \ 45 .mscr = { \ 46 .inst = NXP_S32_PINMUX_GET_MSCR_SIUL2_IDX(value), \ 47 .idx = NXP_S32_PINMUX_GET_MSCR_IDX(value), \ 48 .val = SIUL2_MSCR_SSS(NXP_S32_PINMUX_GET_MSCR_SSS(value)) | \ 49 SIUL2_MSCR_OBE(DT_PROP(group, output_enable)) | \ 50 SIUL2_MSCR_IBE(DT_PROP(group, input_enable)) | \ 51 SIUL2_MSCR_PUE(DT_PROP(group, bias_pull_up) || \ 52 DT_PROP(group, bias_pull_down)) | \ 53 SIUL2_MSCR_PUS(DT_PROP(group, bias_pull_up)) | \ 54 SIUL2_MSCR_SRE(DT_PROP(group, slew_rate)) | \ 55 SIUL2_MSCR_ODE(DT_PROP(group, drive_open_drain) && \ 56 DT_PROP(group, output_enable)) | \ 57 SIUL2_MSCR_TRC(DT_PROP(group, nxp_termination_resistor)) | \ 58 SIUL2_MSCR_CREF(DT_PROP(group, nxp_current_reference_control)) | \ 59 SIUL2_MSCR_RXCB(DT_PROP(group, nxp_rx_current_boost)) \ 60 }, \ 61 .imcr = { \ 62 .inst = NXP_S32_PINMUX_GET_IMCR_SIUL2_IDX(value), \ 63 .idx = NXP_S32_PINMUX_GET_IMCR_IDX(value), \ 64 .val = SIUL2_IMCR_SSS(NXP_S32_PINMUX_GET_IMCR_SSS(value)), \ 65 } 66 67 #endif /* ZEPHYR_SOC_NXP_S32_S32ZE_PINCTRL_SOC_H_ */ 68
