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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h28467 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h30974 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h36466 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h36449 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h39658 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h38017 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h42283 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h40545 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h43068 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h44739 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h44733 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN3/
DMIMX8MN3_cm7.h48279 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN2/
DMIMX8MN2_cm7.h48277 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN1/
DMIMX8MN1_cm7.h48279 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN6/
DMIMX8MN6_ca53.h48291 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
DMIMX8MN6_cm7.h48277 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN5/
DMIMX8MN5_cm7.h48279 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MN4/
DMIMX8MN4_cm7.h48277 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ7/
DMIMX8MQ7_cm4.h52479 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ5/
DMIMX8MQ5_cm4.h50306 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MQ6/
DMIMX8MQ6_cm4.h52479 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD6/
DMIMX8MD6_cm4.h52479 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8MD7/
DMIMX8MD7_cm4.h52479 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member
/hal_nxp-3.5.0/imx/devices/MCIMX6X/
DMCIMX6X_M4.h33789 …__I uint32_t SIS; /**< InterruptStat Register,offset: … member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1165/
DMIMXRT1165_cm4.h71689 __I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */ member

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