1 /*
2 * Copyright 2022-2024 NXP
3 *
4 * All rights reserved.
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_SINC_H_
9 #define FSL_SINC_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup sinc
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief lower_component_name driver version 2.1.4. */
25 #define FSL_SINC_DRIVER_VERSION (MAKE_VERSION(2, 1, 4))
26 /*! @} */
27 #if defined(FSL_FEATURE_SINC_CHANNEL_COUNT)
28 #define SINC_CHANNEL_COUNT (FSL_FEATURE_SINC_CHANNEL_COUNT)
29 #else
30 #error "The definition of FSL_FEATURE_SINC_CHANNEL_COUNT is missing!"
31 #endif
32 #define SINC_NORMAL_INT_REG_ID (0ULL)
33 #define SINC_NORMAL_INT_NAME_COCIE (0ULL)
34 #define SINC_NORMAL_INT_NAME_CHFIE (1ULL)
35 #define SINC_NORMAL_INT_NAME_ZCDIE (2ULL)
36
37 #define SINC_ERROR_INT_REG_ID (1ULL)
38 #define SINC_ERROR_INT_NAME_SCDIE (0ULL)
39 #define SINC_ERROR_INT_NAME_WLMTIE (1ULL)
40 #define SINC_ERROR_INT_NAME_LLMTIE (2ULL)
41 #define SINC_ERROR_INT_NAME_HLMTIE (3ULL)
42
43 #define SINC_FIFO_CAD_INT_REG_ID (2ULL)
44 #define SINC_FIFO_CAD_INT_FUNFIE (0ULL)
45 #define SINC_FIFO_CAD_INT_FOVFIE (1ULL)
46 #define SINC_FIFO_CAD_INT_CADIE (2ULL)
47 #define SINC_FIFO_CAD_INT_SATIE (3ULL)
48
49 #define SINC_ENCODE_INTERRUPT(regId, name, channelId) \
50 ((((1ULL << (uint64_t)(channelId))) << ((uint64_t)(name) * (uint64_t)(SINC_CHANNEL_COUNT))) \
51 << (uint64_t)(regId)*20ULL)
52
53 #define SINC_DECODE_INTERRUPT(interruptMask) \
54 normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \
55 errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \
56 fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL))
57
58 #define SINC_FIND_INT_FIELD_VALUE(mask, name) \
59 ((((uint32_t)(mask) >> ((uint32_t)(name) * ((uint32_t)SINC_CHANNEL_COUNT))) & \
60 ((1UL << ((uint32_t)SINC_CHANNEL_COUNT)) - 1UL)) \
61 << (8UL * (uint32_t)(name)))
62
63 #define SINC_FIND_STATUS_FIELD_VALUE(statusValue, name) \
64 (((uint64_t)(statusValue) & (0xFFUL << ((uint64_t)(name)*8UL))) >> \
65 ((uint64_t)(name) * (8UL - ((uint64_t)SINC_CHANNEL_COUNT))))
66 /*!
67 * @brief The enumeration of SINC module's interrupts.
68 * @anchor sinc_interrupt_enable_t
69 */
70 enum _sinc_interrupt_enable
71 {
72 /* Normal interrupts enable. */
73 /* Enable the conversion complete interrupt for channel 0. */
74 kSINC_CH0ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 0ULL),
75 /* Enable the conversion complete interrupt for channel 1. */
76 kSINC_CH1ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 1ULL),
77 /* Enable the conversion complete interrupt for channel 2. */
78 kSINC_CH2ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 2ULL),
79 /* Enable the conversion complete interrupt for channel 3. */
80 kSINC_CH3ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 3ULL),
81 #if (SINC_CHANNEL_COUNT >= 5UL)
82 /* Enable the conversion complete interrupt for channel 4. */
83 kSINC_CH4ConvCompleteIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 4ULL),
84 #endif
85
86 /* Enable the data output ready interrupt for channel 0. */
87 kSINC_CH0DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 0ULL),
88 /* Enable the data output ready interrupt for channel 1. */
89 kSINC_CH1DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 1ULL),
90 /* Enable the data output ready interrupt for channel 2. */
91 kSINC_CH2DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 2ULL),
92 /* Enable the data output ready interrupt for channel 3. */
93 kSINC_CH3DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 3ULL),
94 #if (SINC_CHANNEL_COUNT >= 5UL)
95 /* Enable the data output ready interrupt for channel 4. */
96 kSINC_CH4DataReadyIntEnable = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 4ULL),
97 #endif
98
99 /* Enable the zero cross detected interrupt for channel 0. */
100 kSINC_CH0ZeroCrossDetectedIntEnable =
101 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 0ULL),
102 /* Enable the zero cross detected interrupt for channel 1. */
103 kSINC_CH1ZeroCrossDetectedIntEnable =
104 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 1ULL),
105 /* Enable the zero cross detected interrupt for channel 2. */
106 kSINC_CH2ZeroCrossDetectedIntEnable =
107 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 2ULL),
108 /* Enable the zero cross detected interrupt for channel 3. */
109 kSINC_CH3ZeroCrossDetectedIntEnable =
110 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 3ULL),
111 #if (SINC_CHANNEL_COUNT >= 5UL)
112 /* Enable the zero cross detected interrupt for channel 4. */
113 kSINC_CH4ZeroCrossDetectedIntEnable =
114 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 4ULL),
115 #endif
116
117 /* Error interrupts enable. */
118 /* Enable the short circuit detected interrupt for channel 0. */
119 kSINC_CH0SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 0ULL),
120 /* Enable the short circuit detected interrupt for channel 1. */
121 kSINC_CH1SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 1ULL),
122 /* Enable the short circuit detected interrupt for channel 2. */
123 kSINC_CH2SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 2ULL),
124 /* Enable the short circuit detected interrupt for channel 3. */
125 kSINC_CH3SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 3ULL),
126 #if (SINC_CHANNEL_COUNT >= 5UL)
127 /* Enable the short circuit detected interrupt for channel 4. */
128 kSINC_CH4SCDIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 4ULL),
129 #endif
130
131 /* Enable the window limit interrupt for channel 0. */
132 kSINC_CH0WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 0ULL),
133 /* Enable the window limit interrupt for channel 1. */
134 kSINC_CH1WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 1ULL),
135 /* Enable the window limit interrupt for channel 2. */
136 kSINC_CH2WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 2ULL),
137 /* Enable the window limit interrupt for channel 3. */
138 kSINC_CH3WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 3ULL),
139 #if (SINC_CHANNEL_COUNT >= 5UL)
140 /* Enable the window limit interrupt for channel 4. */
141 kSINC_CH4WindowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 4ULL),
142 #endif
143
144 /* Enable the low limit interrupt for channel 0. */
145 kSINC_CH0LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 0ULL),
146 /* Enable the low limit interrupt for channel 1. */
147 kSINC_CH1LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 1ULL),
148 /* Enable the low limit interrupt for channel 2. */
149 kSINC_CH2LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 2ULL),
150 /* Enable the low limit interrupt for channel 3. */
151 kSINC_CH3LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 3ULL),
152 #if (SINC_CHANNEL_COUNT >= 5UL)
153 /* Enable the low limit interrupt for channel 4. */
154 kSINC_CH4LowLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 4ULL),
155 #endif
156
157 /* Enable the high limit interrupt for channel 0. */
158 kSINC_CH0HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 0ULL),
159 /* Enable the high limit interrupt for channel 1. */
160 kSINC_CH1HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 1ULL),
161 /* Enable the high limit interrupt for channel 2. */
162 kSINC_CH2HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 2ULL),
163 /* Enable the high limit interrupt for channel 3. */
164 kSINC_CH3HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 3ULL),
165 #if (SINC_CHANNEL_COUNT >= 5UL)
166 /* Enable the high limit interrupt for channel 4. */
167 kSINC_CH4HighLimitIntEnable = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 4ULL),
168 #endif
169
170 /* FIFO and CAD(clock-absence detector) Error interrupts enable. */
171 /* Enable the FIFO underflow interrupt for channel 0. */
172 kSINC_CH0FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 0ULL),
173 /* Enable the FIFO underflow interrupt for channel 1. */
174 kSINC_CH1FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 1ULL),
175 /* Enable the FIFO underflow interrupt for channel 2. */
176 kSINC_CH2FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 2ULL),
177 /* Enable the FIFO underflow interrupt for channel 3. */
178 kSINC_CH3FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 3ULL),
179 #if (SINC_CHANNEL_COUNT >= 5UL)
180 /* Enable the FIFO underflow interrupt for channel 4. */
181 kSINC_CH4FifoUnderflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 4ULL),
182 #endif
183
184 /* Enable the FIFO overflow interrupt for channel 0. */
185 kSINC_CH0FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 0ULL),
186 /* Enable the FIFO overflow interrupt for channel 1. */
187 kSINC_CH1FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 1ULL),
188 /* Enable the FIFO overflow interrupt for channel 2. */
189 kSINC_CH2FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 2ULL),
190 /* Enable the FIFO overflow interrupt for channel 3. */
191 kSINC_CH3FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 3ULL),
192 #if (SINC_CHANNEL_COUNT >= 5UL)
193 /* Enable the FIFO overflow interrupt for channel 4. */
194 kSINC_CH4FifoOverflowIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 4ULL),
195 #endif
196
197 /* Enable the clock absence interrupt for channel 0. */
198 kSINC_CH0CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 0ULL),
199 /* Enable the clock absence interrupt for channel 1. */
200 kSINC_CH1CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 1ULL),
201 /* Enable the clock absence interrupt for channel 2. */
202 kSINC_CH2CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 2ULL),
203 /* Enable the clock absence interrupt for channel 3. */
204 kSINC_CH3CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 3ULL),
205 #if (SINC_CHANNEL_COUNT >= 5UL)
206 /* Enable the clock absence interrupt for channel 4. */
207 kSINC_CH4CADIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 4ULL),
208 #endif
209
210 /* Enable the saturation interrupt for channel 0. */
211 kSINC_CH0SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 0ULL),
212 /* Enable the saturation interrupt for channel 1. */
213 kSINC_CH1SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 1ULL),
214 /* Enable the saturation interrupt for channel 2. */
215 kSINC_CH2SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 2ULL),
216 /* Enable the saturation interrupt for channel 3. */
217 kSINC_CH3SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 3ULL),
218 #if (SINC_CHANNEL_COUNT >= 5UL)
219 /* Enable the saturation interrupt for channel 4. */
220 kSINC_CH4SaturationIntEnable = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 4ULL),
221 #endif
222 };
223
224 /*!
225 * @brief The enumeration of SINC interrupt status flags.
226 * @anchor sinc_interrupt_status_t
227 */
228 enum _sinc_interrupt_status
229 {
230 /* Normal interrupts status. */
231 /* One conversion has finished and data is available in channel 0. */
232 kSINC_CH0ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 0ULL),
233 /* One conversion has finished and data is available in channel 1. */
234 kSINC_CH1ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 1ULL),
235 /* One conversion has finished and data is available in channel 2. */
236 kSINC_CH2ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 2ULL),
237 /* One conversion has finished and data is available in channel 3. */
238 kSINC_CH3ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 3ULL),
239 #if (SINC_CHANNEL_COUNT >= 5UL)
240 /* One conversion has finished and data is available in channel 4. */
241 kSINC_CH4ConvCompleteIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_COCIE, 4ULL),
242 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
243
244 /* The FIFO of channel 0 has exceeded its watermark level and the data is available in channel 0 result register. */
245 kSINC_CH0DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 0ULL),
246 /* The FIFO of channel 1 has exceeded its watermark level and the data is available in channel 1 result register. */
247 kSINC_CH1DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 1ULL),
248 /* The FIFO of channel 2 has exceeded its watermark level and the data is available in channel 2 result register. */
249 kSINC_CH2DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 2ULL),
250 /* The FIFO of channel 3 has exceeded its watermark level and the data is available in channel 3 result register. */
251 kSINC_CH3DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 3ULL),
252 #if (SINC_CHANNEL_COUNT >= 5UL)
253 /* The FIFO of channel 4 has exceeded its watermark level and the data is available in channel 4 result register. */
254 kSINC_CH4DataReadyIntStatus = SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_CHFIE, 4ULL),
255 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
256
257 /* The resulting data on channel 0 crossed zero and changed sign. */
258 kSINC_CH0ZeroCrossDetectedIntStatus =
259 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 0ULL),
260 /* The resulting data on channel 1 crossed zero and changed sign. */
261 kSINC_CH1ZeroCrossDetectedIntStatus =
262 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 1ULL),
263 /* The resulting data on channel 2 crossed zero and changed sign. */
264 kSINC_CH2ZeroCrossDetectedIntStatus =
265 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 2ULL),
266 /* The resulting data on channel 3 crossed zero and changed sign. */
267 kSINC_CH3ZeroCrossDetectedIntStatus =
268 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 3ULL),
269 #if (SINC_CHANNEL_COUNT >= 5UL)
270 /* The resulting data on channel 4 crossed zero and changed sign. */
271 kSINC_CH4ZeroCrossDetectedIntStatus =
272 SINC_ENCODE_INTERRUPT(SINC_NORMAL_INT_REG_ID, SINC_NORMAL_INT_NAME_ZCDIE, 4ULL),
273 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
274
275 /* Error interrupts Status. */
276 /* SINC detected a short circuit on channel 0. */
277 kSINC_CH0SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 0ULL),
278 /* SINC detected a short circuit on channel 1. */
279 kSINC_CH1SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 1ULL),
280 /* SINC detected a short circuit on channel 2. */
281 kSINC_CH2SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 2ULL),
282 /* SINC detected a short circuit on channel 3. */
283 kSINC_CH3SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 3ULL),
284 #if (SINC_CHANNEL_COUNT >= 5UL)
285 /* SINC detected a short circuit on channel 4. */
286 kSINC_CH4SCDIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_SCDIE, 4ULL),
287 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
288
289 /* Indicates channel 0 exceeded its window limit. */
290 kSINC_CH0WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 0ULL),
291 /* Indicates channel 1 exceeded its window limit. */
292 kSINC_CH1WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 1ULL),
293 /* Indicates channel 2 exceeded its window limit. */
294 kSINC_CH2WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 2ULL),
295 /* Indicates channel 3 exceeded its window limit. */
296 kSINC_CH3WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 3ULL),
297 #if (SINC_CHANNEL_COUNT >= 5UL)
298 /* Indicates channel 4 exceeded its window limit. */
299 kSINC_CH4WindowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_WLMTIE, 4ULL),
300 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
301
302 /* Indicates channel 0 exceeded its low limit. */
303 kSINC_CH0LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 0ULL),
304 /* Indicates channel 1 exceeded its window limit. */
305 kSINC_CH1LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 1ULL),
306 /* Indicates channel 2 exceeded its window limit. */
307 kSINC_CH2LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 2ULL),
308 /* Indicates channel 3 exceeded its window limit. */
309 kSINC_CH3LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 3ULL),
310 #if (SINC_CHANNEL_COUNT >= 5UL)
311 /* Indicates channel 4 exceeded its window limit. */
312 kSINC_CH4LowLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_LLMTIE, 4ULL),
313 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
314
315 /* Indicates channel 0 exceeded its high limit. */
316 kSINC_CH0HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 0ULL),
317 /* Indicates channel 1 exceeded its high limit. */
318 kSINC_CH1HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 1ULL),
319 /* Indicates channel 2 exceeded its high limit. */
320 kSINC_CH2HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 2ULL),
321 /* Indicates channel 3 exceeded its high limit. */
322 kSINC_CH3HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 3ULL),
323 #if (SINC_CHANNEL_COUNT >= 5UL)
324 /* Indicates channel 4 exceeded its high limit. */
325 kSINC_CH4HighLimitIntStatus = SINC_ENCODE_INTERRUPT(SINC_ERROR_INT_REG_ID, SINC_ERROR_INT_NAME_HLMTIE, 4ULL),
326 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
327
328 /* FIFO and CAD(clock-absence detector) Error interrupts Status. */
329 /* A FIFO underflow occurred on channel 0. */
330 kSINC_CH0FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 0ULL),
331 /* A FIFO underflow occurred on channel 1. */
332 kSINC_CH1FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 1ULL),
333 /* A FIFO underflow occurred on channel 2. */
334 kSINC_CH2FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 2ULL),
335 /* A FIFO underflow occurred on channel 3. */
336 kSINC_CH3FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 3ULL),
337 #if (SINC_CHANNEL_COUNT >= 5UL)
338 /* A FIFO underflow occurred on channel 4. */
339 kSINC_CH4FifoUnderflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FUNFIE, 4ULL),
340 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
341
342 /* A FIFO overflow occurred on channel 0. */
343 kSINC_CH0FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 0ULL),
344 /* A FIFO overflow occurred on channel 1. */
345 kSINC_CH1FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 1ULL),
346 /* A FIFO overflow occurred on channel 2. */
347 kSINC_CH2FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 2ULL),
348 /* A FIFO overflow occurred on channel 3. */
349 kSINC_CH3FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 3ULL),
350 #if (SINC_CHANNEL_COUNT >= 5UL)
351 /* A FIFO overflow occurred on channel 4. */
352 kSINC_CH4FifoOverflowIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_FOVFIE, 4ULL),
353 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
354
355 /* SINC detected the absence of a clock on channel 0. */
356 kSINC_CH0CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 0ULL),
357 /* SINC detected the absence of a clock on channel 1. */
358 kSINC_CH1CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 1ULL),
359 /* SINC detected the absence of a clock on channel 2. */
360 kSINC_CH2CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 2ULL),
361 /* SINC detected the absence of a clock on channel 3. */
362 kSINC_CH3CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 3ULL),
363 #if (SINC_CHANNEL_COUNT >= 5UL)
364 /* SINC detected the absence of a clock on channel 4. */
365 kSINC_CH4CADIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_CADIE, 4ULL),
366 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
367
368 /* Channel 0 is saturated. */
369 kSINC_CH0SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 0ULL),
370 /* Channel 1 is saturated. */
371 kSINC_CH1SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 1ULL),
372 /* Channel 2 is saturated. */
373 kSINC_CH2SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 2ULL),
374 /* Channel 3 is saturated. */
375 kSINC_CH3SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 3ULL),
376 #if (SINC_CHANNEL_COUNT >= 5UL)
377 /* Channel 4 is saturated. */
378 kSINC_CH4SaturationIntStatus = SINC_ENCODE_INTERRUPT(SINC_FIFO_CAD_INT_REG_ID, SINC_FIFO_CAD_INT_SATIE, 4ULL),
379 #endif /* (SINC_CHANNEL_COUNT >= 5UL) */
380 };
381
382 /*!
383 * @brief The enumeration of channel id, the sinc module contains 4 channels.
384 */
385 typedef enum _sinc_channel_id
386 {
387 kSINC_Channel0 = 0U, /*!< Channel 0. */
388 kSINC_Channel1, /*!< Channel 1. */
389 kSINC_Channel2, /*!< Channel 2. */
390 kSINC_Channel3, /*!< Channel 3. */
391 } sinc_channel_id_t;
392
393 /*!
394 * @brief The enumeration of modulator clock name.
395 * @anchor _sinc_modulator_clock
396 */
397 enum _sinc_modulator_clock
398 {
399 kSINC_ModClk0 = 1UL, /*!< Modulator Clock 0 output. */
400 kSINC_ModClk1 = 2UL, /*!< Modulator Clock 1 output. */
401 kSINC_ModClk2 = 4UL, /*!< Modulator Clock 2 output. */
402 };
403
404 /*!
405 * @brief The enumeration of input clock.
406 */
407 typedef enum _sinc_inputClk_source
408 {
409 kSINC_InputClk_SourceMclkOut0 = 0U, /*!< MCLK_OUT0 with internal routeback. */
410 kSINC_InputClk_SourceMclkOut1 = 1U, /*!< MCLK_OUT1 with internal routeback. */
411 kSINC_InputClk_SourceMclkOut2 = 2U, /*!< MCLK_OUT2 with internal routeback. */
412 kSINC_InputClk_SourceExternalModulatorClk = 3U, /*!< External modulator clock dedicated to the selected channel. */
413 kSINC_InputClk_SourceAdjacentChannelClk = 7U, /*!< Grouped clock shared with an adjacent channel. */
414 } sinc_inputClk_source_t;
415
416 /*!
417 * @brief The enumeration of clock edge.
418 */
419 typedef enum _sinc_inputClk_edge
420 {
421 kSINC_InputClk_EdgePositive = 1U, /*!< Positive edge. */
422 kSINC_InputClk_EdgeNegative, /*!< Negative edge. */
423 kSINC_InputClk_EdgeBoth, /*!< Both edges. */
424 kSINC_InputClk_EdgeOddPositive, /*!< Every other odd positive edge. */
425 kSINC_InputClk_EdgeEvenPositive, /*!< Every other even positive edge. */
426 kSINC_InputClk_EdgeOddNegative, /*!< Every other odd negative edge. */
427 kSINC_InputClk_EdgeEvenNegative, /*!< Every other even negative edge. */
428 } sinc_inputClk_edge_t;
429
430 /*!
431 * @brief The enumeration of input bit format.
432 */
433 typedef enum _sinc_inputBit_format
434 {
435 kSINC_InputBit_FormatExternalBitstream = 0U, /*!< External bitstream from the MBIT[n] signal. */
436 kSINC_InputBit_FormatExternalManchesterCode, /*!< External Manchester code. */
437 kSINC_InputBit_FormatInternal16bitParallelData, /*!< Internal 16-bit parallel data from MPDATA register. */
438 kSINC_InputBit_FormatInternal32bitSerialData, /*!< Internal 32-bit serial data from MPDATA. */
439 } sinc_inputBit_format_t;
440
441 /*!
442 * @brief The enumeration of input bit source.
443 */
444 typedef enum _sinc_inputBit_source
445 {
446 kSINC_InputBit_SourceExternalBitstream = 0U, /*!< External bitstream from the MBIT[n] signal. */
447 kSINC_InputBit_SourceInternalBitstream = 1U, /*!< Alternate internal bitstream from the INP[n] signal. */
448 kSINC_InputBit_SourceAdjacentChannel = 3U, /*!< Grouped bitstream shared with an adjacent chanel. */
449 } sinc_inputBit_source_t;
450
451 /*!
452 * @brief The enumeration of trigger source.
453 */
454 typedef enum _sinc_conv_trigger_source
455 {
456 kSINC_ConvTrig_SoftPosEdge = 0x0U, /*!< Positive edge software trigger. */
457 kSINC_ConvTrig_SoftHighLevel = 0x4U, /*!< High level software trigger. */
458 kSINC_ConvTrig_HardPosEdge = 0x1U, /*!< Positive edge hardware trigger. */
459 kSINC_ConvTrig_HardHighLevel = 0x5U, /*!< High level hardware trigger. */
460 kSINC_ConvTrig_AdjacentChannel = 0x3U, /*!< Grouped hardware trigger shared with an adjacent channel. */
461 } sinc_conv_trigger_source_t;
462
463 /*!
464 * @brief The enumeration of conversion mode.
465 */
466 typedef enum _sinc_conv_mode
467 {
468 kSINC_ConvMode_Single = 0U, /*!< One conversion that follows an edge or level trigger event. */
469 kSINC_ConvMode_Continuous, /*!< Multiple conversions that follow a triggering event, a new triggering event
470 cancels and restarts conversion. */
471 kSINC_ConvMode_Always, /*!< Multiple conversions that follow the first triggering event, SINC ignores the
472 next triggering event. */
473 kSINC_ConvMode_FixedNumber, /*!< Fixed number conversions that follow the first triggering event, a new
474 triggering event cancels and restarts conversion. */
475 } sinc_conv_mode_t;
476
477 /*!
478 * @brief The enumeration of pulse trigger mux.
479 */
480 typedef enum _sinc_pulse_trigger_mux
481 {
482 kSINC_PulseTrigger_Disabled = 0U, /*!< Disable pulse trigger output. */
483 kSINC_PulseTrigger_MuxHighLimitLevelSignal, /*!< Select high limit level signal for pulse trigger output. */
484 kSINC_PulseTrigger_MuxLowLimitLevelSignal, /*!< Select low limit level signal for pulse trigger output. */
485 kSINC_PulseTrigger_MuxHighLowLimitLevelSignal, /*!< Select low or high limit level signal for pulse trigger output.
486 */
487 kSINC_PulseTrigger_MuxWindowLimitLevelSignal, /*!< Select window limit level signal for pulse trigger output. */
488 kSINC_PulseTrigger_MuxZeroCrossRisingLevelSignal, /*!< Select zero cross rising level signal for pulse trigger
489 output. */
490 kSINC_PulseTrigger_MuxZeroCrossFallingLevelSignal, /*!< Select zero cross falling level signal for pulse trigger
491 output. */
492 kSINC_PulseTrigger_MuxRsLimHighLevelSignal, /*!< Select level signal that indicates a high level from an RS
493 flip-flop or a schmitt trigger for pulse trigger output. */
494 kSINC_PulseTrigger_MuxRsLimLowLevelSignal, /*!< Select level signal that indicates a low level from an RS flip-flop
495 or a schmitt trigger for pulse trigger output. */
496 kSINC_PulseTrigger_MuxChannelRawInputModBitStream, /*!< Select channel raw input modulator bitstream for pulse
497 trigger output. */
498 kSINC_PulseTrigger_MuxChannelRawInputModClock, /*!< Select channel raw input modulator clock for pulse trigger
499 output. */
500 kSINC_PulseTrigger_MuxChannelRecoveredModBitStream, /*!< Select channel output recovered modulator bitstream for
501 pulse trigger output. */
502 kSINC_PulseTrigger_MuxChannelRecoveredModClock, /*!< Select channel output recovered modulator clock for pulse
503 trigger output. */
504 kSINC_PulseTrigger_MuxHighLimitPulseSignal, /*!< Select high limit pulse signal for pulse trigger output. */
505 kSINC_PulseTrigger_MuxLowLimitPulseSignal, /*!< Select low limit pulse signal for pulse trigger output. */
506 kSINC_PulseTrigger_MuxLimitPulseSignal, /*!< Select the pulse signal that indicates a high/low/window limit for
507 pulse trigger output. */
508 kSINC_PulseTrigger_MuxWindowLimitPulseSignal, /*!< Select window limit pulse signal for pulse trigger output. */
509 kSINC_PulseTrigger_MuxHighLowLimitPulseSignal, /*!< Select the pulse signal that indicates a high or low limit for
510 pulse trigger output. */
511 kSINC_PulseTrigger_MuxZeroCrossRisePulseSignal, /*!< Select zero cross rise pulse signal for trigger output. */
512 kSINC_PulseTrigger_MuxZeroCrossFallPulseSignal, /*!< Select zero cross fall pulse signal for trigger output. */
513 kSINC_PulseTrigger_MuxZeroCrossRiseFallPulseSignal, /*!< Select zero cross rise/fall pulse signal for trigger
514 output. */
515 kSINC_PulseTrigger_MuxFifoWatermarkOkPulseSignal, /*!< Select FIFO watermark OK pulse signal for trigger output. */
516 kSINC_PulseTrigger_MuxFifoOverflowPulseSignal, /*!< Select FIFO overflow pulse signal. */
517 kSINC_PulseTrigger_MuxFifoUnderflowPulseSignal, /*!< Select FIFO underflow pulse signal. */
518 kSINC_PulseTrigger_MuxFifoEmptyPulseSignal, /*!< Select FIFO empty pulse signal. */
519 kSINC_PulseTrigger_MuxClockMonitorAssertPulseSignal, /*!< Select clock monitor assert pulse signal. */
520 kSINC_PulseTrigger_MuxShortCircuitAssertPulseSignal, /*!< Select short circuit assert pulse signal. */
521 kSINC_PulseTrigger_MuxSaturationPulseSignal, /*!< Select saturation pulse signal. */
522 kSINC_PulseTrigger_MuxConversionCompletePulseSignal, /*!< Select conversion complete pulse signal. */
523 } sinc_pulse_trigger_mux_t;
524
525 /*!
526 * @brief The enumeration of zero cross detector operate mode.
527 */
528 typedef enum _sinc_zero_cross_operate_mode
529 {
530 kSINC_ZCD_BothRiseAndFall = 0U, /*!< Zero cross detector operate on both rise and fall. */
531 kSINC_ZCD_OnlyFall, /*!< Zero cross detector operate on fall edge. */
532 kSINC_ZCD_OnlyRise, /*!< Zero cross detector operate on rise edge. */
533 kSINC_ZCD_Disabled = 0xFU, /*!< Zero cross detector disabled. */
534 } sinc_zero_cross_operate_mode_t;
535
536 /*!
537 * @brief The enumeration of primary filter order.
538 */
539 typedef enum _sinc_primary_filter_order
540 {
541 kSINC_PF_FastSinc = 0U, /*!< Fast sinc filter, ORD is 4. */
542 kSINC_PF_FirstOrder, /*!< First order filter, ORD is 1. */
543 kSINC_PF_SecondOrder, /*!< Second order filter, ORD is 2. */
544 kSINC_PF_ThirdOrder, /*!< Third order filter, ORD is 3. */
545 } sinc_primary_filter_order_t;
546
547 /*!
548 * @brief The enumeration of clock prescale that specify the clock divider ratio for the modulator clock.
549 */
550 typedef enum _sinc_clock_prescale
551 {
552 kSINC_ClkPrescale1 = 0UL, /*!< No prescale. */
553 kSINC_ClkPrescale2, /*!< Modulator clock divider ratio is 2. */
554 kSINC_ClkPrescale4, /*!< Modulator clock divider ratio is 4. */
555 kSINC_ClkPrescale8, /*!< Modulator clock divider ratio is 8. */
556 } sinc_clock_prescale_t;
557
558 /*!
559 * @brief The enumeration of primary filter shift direction.
560 */
561 typedef enum _sinc_primary_filter_shift_direction
562 {
563 kSINC_PF_ShiftRight = 0U, /*!< Right shift the raw data. */
564 kSINC_PF_ShiftLeft = 1U << 4U, /*!< Left shift the raw data. */
565 } sinc_primary_filter_shift_direction_t;
566
567 /*!
568 * @brief The enumeration of primary filer bias sign.
569 */
570 typedef enum _sinc_primary_filter_bias_sign
571 {
572 kSINC_PF_BiasPositive = 0UL, /*!< The bias sign is positive. */
573 kSINC_PF_BiasNegative, /*!< The bias sign is negative. */
574 } sinc_primary_filter_bias_sign_t;
575
576 /*!
577 * @brief The enumeration of HPF DC remover Alpha coefficient.
578 */
579 typedef enum _sinc_primary_filter_hpf_alpha_coeff
580 {
581 kSINC_PF_HPFAlphaCoeff0 = 0UL, /*!< Disabled HPF. */
582 kSINC_PF_HPFAlphaCoeff1, /*!< Alpha coefficient = 1 - (2^-5) */
583 kSINC_PF_HPFAlphaCoeff2, /*!< Alpha coefficient = 1 - (2^-6) */
584 kSINC_PF_HPFAlphaCoeff3, /*!< Alpha coefficient = 1 - (2^-7) */
585 kSINC_PF_HPFAlphaCoeff4, /*!< Alpha coefficient = 1 - (2^-8) */
586 kSINC_PF_HPFAlphaCoeff5, /*!< Alpha coefficient = 1 - (2^-9) */
587 kSINC_PF_HPFAlphaCoeff6, /*!< Alpha coefficient = 1 - (2^-10) */
588 kSINC_PF_HPFAlphaCoeff7, /*!< Alpha coefficient = 1 - (2^-11) */
589 kSINC_PF_HPFAlphaCoeff8, /*!< Alpha coefficient = 1 - (2^-12) */
590 kSINC_PF_HPFAlphaCoeff9, /*!< Alpha coefficient = 1 - (2^-13) */
591 kSINC_PF_HPFAlphaCoeff10, /*!< Alpha coefficient = 1 - (2^-14) */
592 kSINC_PF_HPFAlphaCoeff11, /*!< Alpha coefficient = 1 - (2^-15) */
593 kSINC_PF_HPFAlphaCoeff12, /*!< Alpha coefficient = 1 - (2^-16) */
594 kSINC_PF_HPFAlphaCoeff13, /*!< Alpha coefficient = 1 - (2^-17) */
595 kSINC_PF_HPFAlphaCoeff14, /*!< Alpha coefficient = 1 - (2^-18) */
596 kSINC_PF_HPFAlphaCoeff15, /*!< Alpha coefficient = 1 - (2^-19) */
597 } sin_primary_filter_hpf_alpha_coeff_t;
598
599 /*!
600 * @brief The enumeration of input bit delay.
601 */
602 typedef enum _sinc_inputBit_delay
603 {
604 kSINC_InputBit_DelayDisabled = 0U, /*!< Input modulator bitstream delay disabled. */
605 kSINC_InputBit_Delay1ClkCycle, /*!< Input modulator bitstream delay 1 PRE_CLK cycle. */
606 kSINC_InputBit_Delay2ClkCycle, /*!< Input modulator bitstream delay 2 PRE_CLK cycle. */
607 kSINC_InputBit_Delay3ClkCycle, /*!< Input modulator bitstream delay 3 PRE_CLK cycle. */
608 kSINC_InputBit_Delay4ClkCycle, /*!< Input modulator bitstream delay 4 PRE_CLK cycle. */
609 kSINC_InputBit_Delay5ClkCycle, /*!< Input modulator bitstream delay 5 PRE_CLK cycle. */
610 kSINC_InputBit_Delay6ClkCycle, /*!< Input modulator bitstream delay 6 PRE_CLK cycle. */
611 kSINC_InputBit_Delay7ClkCycle, /*!< Input modulator bitstream delay 7 PRE_CLK cycle. */
612 kSINC_InputBit_Delay8ClkCycle, /*!< Input modulator bitstream delay 8 PRE_CLK cycle. */
613 kSINC_InputBit_Delay9ClkCycle, /*!< Input modulator bitstream delay 9 PRE_CLK cycle. */
614 kSINC_InputBit_Delay10ClkCycle, /*!< Input modulator bitstream delay 10 PRE_CLK cycle. */
615 kSINC_InputBit_Delay11ClkCycle, /*!< Input modulator bitstream delay 11 PRE_CLK cycle. */
616 kSINC_InputBit_Delay12ClkCycle, /*!< Input modulator bitstream delay 12 PRE_CLK cycle. */
617 kSINC_InputBit_Delay13ClkCycle, /*!< Input modulator bitstream delay 13 PRE_CLK cycle. */
618 kSINC_InputBit_Delay14ClkCycle, /*!< Input modulator bitstream delay 14 PRE_CLK cycle. */
619 kSINC_InputBit_Delay15ClkCycle, /*!< Input modulator bitstream delay 15 PRE_CLK cycle. */
620 } sinc_inputBit_delay_t;
621
622 /*!
623 * @brief The enumeration of short-circuit detector operate mode.
624 */
625 typedef enum _sinc_scd_operate_mode
626 {
627 kSINC_Scd_OperateAtChannelEnabled = 0U, /*!< SCD operates when the channel is enabled. */
628 kSINC_Scd_OperateAtConversion, /*!< SCD operates when the PF is performing a conversion. */
629 kSINC_Scd_OperateDisabled = 0xFU, /*!< Short circuit detect is disabled. */
630 } sinc_scd_operate_mode_t;
631
632 /*!
633 * @brief The enumeration of short-circuit detector option.
634 */
635 typedef enum _sinc_scd_option
636 {
637 kSINC_Scd_DetectRepeating0And1 = 0U, /*!< Both repeating 0 and 1 increment the SCD counter. */
638 kSINC_Scd_DetectRepeatingOnly1, /*!< Only repeating 1 increment the SCD counter. */
639 kSINC_Scd_DetectRepeatingOnly0, /*!< Only repeating 1 increment the SCD counter. */
640 } sinc_scd_option_t;
641
642 /*!
643 * @brief The mode of limit detector.
644 *
645 * @note The value of each limit detector contains lot of information:
646 * bit[1:0]: limit detection options,
647 * bit[2]: low limit break signal.
648 * bit[3]: window limit break signal.
649 * bit[4]: High limit break signal.
650 * bit[7]: Enable/disable limit detector.
651 */
652 typedef enum _sinc_limit_detector_mode
653 {
654 kSINC_Lmt_BothHighAndLowLimit = 0x94U, /*!< Limit detector is enabled, and compare the filter sample value to high
655 and low limit, if the value larger than high limit will trigger
656 interrupt or break, and if the value lower than low limit will trigger
657 interrupt or break. */
658 kSINC_Lmt_OnlyHighLimit = 0x91U, /*!< Limit detector is enabled, and compare the filter sample value to high limit,
659 if the value larger than high limit will trigger interrupt or break. */
660 kSINC_Lmt_OnlyLowLimit = 0x86U, /*!< Limit detector is enabled, and compare the filter sample value to low limit, if
661 the value lower than low limit will trigger interrupt or break. */
662 kSINC_Lmt_WindowedValue = 0x8BU, /*!< Limit detector is enabled, and compare the filter sample value to high and low
663 limit, if the value higher than low limit and lower than high limit will trigger
664 interrupt or break. */
665 kSINC_Lmt_Disabled = 0x0U, /*!< Limit detector is disabled. */
666
667 } sinc_limit_detector_mode_t;
668
669 /*!
670 * @brief The enumeration of clock-absence threshold.
671 */
672 typedef enum _sinc_cad_threshold
673 {
674 kSINC_Cad_Disabled = 0U, /*!< Clock absence detector is disabled. */
675 kSINC_Cad_Count1ClkCycle, /*!< Clock absence detector threshold is 1 clock cycle. */
676 kSINC_Cad_Count2ClkCycle, /*!< Clock absence detector threshold is 2 clock cycle. */
677 kSINC_Cad_Count3ClkCycle, /*!< Clock absence detector threshold is 3 clock cycle. */
678 kSINC_Cad_Count4ClkCycle, /*!< Clock absence detector threshold is 4 clock cycle. */
679 kSINC_Cad_Count5ClkCycle, /*!< Clock absence detector threshold is 5 clock cycle. */
680 kSINC_Cad_Count6ClkCycle, /*!< Clock absence detector threshold is 6 clock cycle. */
681 kSINC_Cad_Count7ClkCycle, /*!< Clock absence detector threshold is 7 clock cycle. */
682 kSINC_Cad_Count8ClkCycle, /*!< Clock absence detector threshold is 8 clock cycle. */
683 kSINC_Cad_Count9ClkCycle, /*!< Clock absence detector threshold is 9 clock cycle. */
684 kSINC_Cad_Count10ClkCycle, /*!< Clock absence detector threshold is 10 clock cycle. */
685 kSINC_Cad_Count11ClkCycle, /*!< Clock absence detector threshold is 11 clock cycle. */
686 kSINC_Cad_Count12ClkCycle, /*!< Clock absence detector threshold is 12 clock cycle. */
687 kSINC_Cad_Count13ClkCycle, /*!< Clock absence detector threshold is 13 clock cycle. */
688 kSINC_Cad_Count14ClkCycle, /*!< Clock absence detector threshold is 14 clock cycle. */
689 kSINC_Cad_Count15ClkCycle, /*!< Clock absence detector threshold is 15 clock cycle. */
690 } sinc_cad_threshold_t;
691
692 #if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL)
693 /*!
694 * @brief The enumeration of alternate DMA source.
695 */
696 typedef enum _sinc_alternate_dma_source
697 {
698 kSINC_AltDma_Disabled = 0U, /*!< Alternate DMA disabled. */
699 kSINC_AltDma_PfConvComplete, /*!< Select PF conversion complete for alternate DMA. */
700 kSINC_AltDma_PfDataOutputReady, /*!< Select PF data output ready for alternate DMA. */
701 kSINC_AltDma_ZeroCrossDetected, /*!< Select zero crossing detected for alternate DMA. */
702 kSINC_AltDma_ShortCircuitDetected, /*!< Select short circuit detected for alternate DMA. */
703 kSINC_AltDma_WindowLimitDetected, /*!< Select window limit detected for alternate DMA. */
704 kSINC_AltDma_LowLimitDetected, /*!< Select low limit detected for alternate DMA. */
705 kSINC_AltDma_HighLimitDetected, /*!< Select high limit detected for alternate DMA. */
706 kSINC_AltDma_FifoUnderflow, /*!< Select FIFO underflow detected for alternate DMA. */
707 kSINC_AltDma_FifoOverflow, /*!< Select FIFO overflow detected for alternate DMA. */
708 kSINC_AltDma_ClockAbsence, /*!< Select clock absence detected for alternate DMA. */
709 kSINC_AltDma_Saturation, /*!< Select channel saturation for alternate DMA. */
710 } sinc_alternate_dma_source_t;
711 #endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */
712
713 /*!
714 * @brief The enumeration of result data format.
715 */
716 typedef enum _sinc_result_data_format
717 {
718 kSINC_LeftJustifiedSigned = 0U, /*!< Left justified, signed. */
719 kSINC_LeftJustifiedUnsigned, /*!< Left justified, unsigned. */
720 } sinc_result_data_format_t;
721
722 /*!
723 * @brief The enumeration of debug output.
724 */
725 typedef enum _sinc_debug_output
726 {
727 kSINC_Debug_PfFinalData = 0U, /*!< Final data from PF(24 bits). */
728 kSINC_Debug_OffsetData, /*!< Offset data(24 bits). */
729 kSINC_Debug_PfShiftedData, /*!< Shifted data from the PF(24 bits). */
730 kSINC_Debug_HpfData, /*!< DC remover(HPF) data(32 bits). */
731 kSINC_Debug_CicRawData, /*!< Raw data from the PF's CIC filter. */
732 kSINC_Debug_ScdHistoricalData, /*!< Historical data from SCD. */
733 kSINC_Debug_ManchesterDecoderData, /*!< Data from the Manchester decoder. */
734 kSINC_Debug_CadData, /*!< Data from CAD. */
735 kSINC_Debug_FifoEntriesNum, /*!< Number of available entries in the FIFO. */
736 kSINC_Debug_ParallelSerialConverterStatus, /*!< Status of the parallel or serial data converter. */
737 } sinc_debug_output_t;
738
739 /*!
740 * @brief The structure of channel input options, including input bit settings and input clock settings.
741 */
742 typedef struct _sinc_channel_input_option
743 {
744 sinc_inputBit_format_t inputBitFormat; /*!< Specify input bit format, please refer
745 to @ref sinc_inputBit_format_t. */
746 sinc_inputBit_source_t inputBitSource; /*!< Specify input bit source, please refer
747 to @ref sinc_inputBit_source_t. */
748 sinc_inputBit_delay_t inputBitDelay; /*!< Specify input bit delay, please refer to @ref sinc_inputBit_delay_t. */
749
750 sinc_inputClk_source_t inputClkSource; /*!< Specify input clock source, please refer
751 to @ref sinc_inputClk_source_t. */
752 sinc_inputClk_edge_t inputClkEdge; /*!< Specify input clock edge, please refer to @ref sinc_inputClk_edge_t. */
753 } sinc_channel_input_option_t;
754
755 /*!
756 * @brief The structure of channel conversion options, including CIC filter settings, HPF settings, shift settings,
757 * bias settings and so on.
758 */
759 typedef struct _sinc_channel_conv_option
760 {
761 sinc_conv_mode_t convMode; /*!< Specify conversion mode, please refer to @ref sinc_conv_mode_t. */
762 sinc_conv_trigger_source_t convTriggerSource; /*!< Specify conversion trigger source, please
763 refer to @ref sinc_conv_trigger_source_t. */
764
765 bool enableChPrimaryFilter; /*!< Enable/disable channel's primary filter. */
766 sinc_primary_filter_order_t pfOrder; /*!< Specify the order of primary filter, please
767 refer to @ref sinc_primary_filter_order_t. */
768 uint16_t u16pfOverSampleRatio; /*!< Control primary filter's OSR, the minimum permissible value is 3,
769 low value produce unpredictable result, the maximum permissible value depend on
770 PF order and the desired data format, if PF order is third order and data format
771 is signed, the maximum OSR value is 1289, if PF order is third order and data
772 format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR
773 value is 2047. Please note that the OSR for equation is
774 u16pfOverSampleRatio + 1*/
775
776 sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff; /*!< Specify HPF's alpha coeff, please
777 refer to @ref sin_primary_filter_hpf_alpha_coeff_t. */
778
779 sinc_primary_filter_shift_direction_t pfShiftDirection; /*!< Select shift direction, right or left. */
780 uint8_t u8pfShiftBitsNum; /*!< Specify the number of bits to shift the data, ranges from 0 to 15. */
781
782 sinc_primary_filter_bias_sign_t pfBiasSign; /*!< Select bias sign, please refer
783 to @ref sinc_primary_filter_bias_sign_t. */
784 uint32_t u32pfBiasValue; /*!< Range from 0 to 0x7FFFFFUL. */
785 } sinc_channel_conv_option_t;
786
787 /*!
788 * @brief The structure of channel protection options, including limit check settings, short-circuit settings,
789 * clock-absence settings, and zero-crossing settings.
790 */
791 typedef struct _sinc_channel_protection_option
792 {
793 sinc_limit_detector_mode_t limitDetectorMode; /*!< Specify limit detector mode, please
794 refer to @ref sinc_limit_detector_mode_t. */
795 bool bEnableLmtBreakSignal; /*!< Enable/disable limit break signal,
796 the details of break signal is depended on detector mode. */
797 uint32_t u32LowLimitThreshold; /*!< Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL. */
798 uint32_t u32HighLimitThreshold; /*!< Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL. */
799
800 sinc_scd_operate_mode_t scdOperateMode; /*!< Enable/disable scd, and set SCD operate timming. */
801 uint8_t u8ScdLimitThreshold; /*!< Range from 2 to 255, 0 and 1 are prohibited. */
802 sinc_scd_option_t scdOption; /*!< Specify SCD options, please refer to @ref sinc_scd_option_t. */
803 bool bEnableScdBreakSignal; /*!< Enable/disable SCD break signal. */
804
805 sinc_cad_threshold_t cadLimitThreshold; /*!< Specify the threshold value for the CAD counter. */
806 bool bEnableCadBreakSignal; /*!< Enable/disable CAD break signal. */
807
808 sinc_zero_cross_operate_mode_t zcdOperateMode; /*!< Specify zero cross detector operate mode. */
809 } sinc_channel_protection_option_t;
810
811 /*!
812 * @brief The structure of channel configurations, including channel input option, channel conversion options, channel
813 * protection options, and so on.
814 */
815 typedef struct _sinc_channel_config
816 {
817 bool bEnableChannel; /*!< Enable/disable channel. */
818 bool bEnableFifo; /*!< Enable/disable channel's FIFO. */
819 uint8_t u8FifoWaterMark; /*!< Specify the fifo watermark, range from 0 to 15. */
820 bool bEnablePrimaryDma; /*!< Used to enable/disable primary DMA. */
821 #if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL)
822 sinc_alternate_dma_source_t altDmaSource; /*!< Set channel's alternate DMA source, please refer
823 to @ref sinc_alternate_dma_source_t. */
824 #endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */
825 sinc_result_data_format_t dataFormat; /*!< Set channel's result data format, please refer
826 to @ref sinc_result_data_format_t. */
827
828 sinc_channel_input_option_t *chInputOption; /*!< The pointer to @ref sinc_channel_input_option_t that contains
829 channel input options. */
830 sinc_channel_conv_option_t *chConvOption; /*!< The pointer to @ref sinc_channel_conv_option_t that contains
831 channel conversion options. */
832 sinc_channel_protection_option_t *chProtectionOption; /*!< The pointer to @ref sinc_channel_protection_option_t
833 that contains channel protection options. */
834 } sinc_channel_config_t;
835
836 /*!
837 * @brief The structure of sinc configurations, including clock settings anc channels' settings.
838 */
839 typedef struct _sinc_config
840 {
841 sinc_clock_prescale_t clockPreDivider; /*!< Specify modulator clock pre divider, please
842 refer to @ref sinc_clock_prescale_t. */
843 uint32_t modClkDivider; /*!< Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in
844 the MCLK output, write an even value to*/
845 bool disableModClk0Output; /*!< Disable/enable modulator clock0 output. */
846 bool disableModClk1Output; /*!< Disable/enable modulator clock1 output. */
847 bool disableModClk2Output; /*!< Disable/enable modulator clock2 output. */
848
849 sinc_channel_config_t *channelsConfigArray[SINC_CHANNEL_COUNT]; /*!< The array that contains 4 elements, and the
850 type of each element is \b sinc_channel_config_t *,
851 channelsConfigArray[0] corresponding to channel0,
852 channelsConfigArray[1] corresponding to channel1,
853 channelsConfigArray[2] corresponding to channel2,
854 channelsConfigArray[3] corresponding to channel3, if some channels
855 are not used, the corresponding elements should be set as NULL. */
856
857 bool disableDozeMode; /*!< Disable/enable SINC module when the chip enters Doze or stop mode. */
858 bool enableMaster; /*!< Enable/disable all function blocks of SINC module. */
859 } sinc_config_t;
860
861 /*******************************************************************************
862 * API
863 ******************************************************************************/
864
865 /*!
866 * @name SINC Generic Functional Control APIs
867 * @{
868 */
869
870 /*!
871 * @brief Initialize selected SINC instance, including clock options and channel options.
872 *
873 * @param base SINC peripheral base address.
874 * @param config The pointer to @ref sinc_config_t structure.
875 */
876 void SINC_Init(SINC_Type *base, const sinc_config_t *config);
877
878 /*!
879 * @brief De-initialize selected SINC instance.
880 *
881 * @param base SINC peripheral base address.
882 */
883 void SINC_Deinit(SINC_Type *base);
884
885 /*!
886 * @brief Get default configuration.
887 *
888 * @code {.c}
889 * config->clockPreDivider = kSINC_ClkPrescale1;
890 * config->modClkDivider = 2UL;
891 * config->disableModClk0Output = false;
892 * config->disableModClk1Output = false;
893 * config->disableModClk2Output = false;
894 *
895 * config->channelsConfigArray[4] = {NULL, NULL, NULL, NULL};
896 *
897 * config->disableDozeMode = false;
898 * config->enableMaster = false;
899 * @endcode
900 *
901 *
902 * @param config The pointer to @ref sinc_config_t structure, must not be NULL.
903 */
904 void SINC_GetDefaultConfig(sinc_config_t *config);
905
906 /*! @} */
907
908 /*!
909 * @name SINC Generic Low Level Control APIs
910 * @{
911 */
912
913 /*!
914 * @brief Enable/disable all function blocks enabled in their respective registers.
915 *
916 * @param base SINC peripheral base address.
917 * @param enable Used to enable/disable all function blocks:
918 * - \b true Enable all function blocks, please note that clock must be configured previously;
919 * - \b false Disable all function blocks.
920 */
SINC_EnableMaster(SINC_Type * base,bool enable)921 static inline void SINC_EnableMaster(SINC_Type *base, bool enable)
922 {
923 if (enable)
924 {
925 base->MCR |= SINC_MCR_MEN_MASK;
926 }
927 else
928 {
929 base->MCR &= ~SINC_MCR_MEN_MASK;
930 }
931 }
932
933 /*!
934 * @brief Reset all function blocks(except for the clock blocks), interrupt statuses.
935 *
936 * @param base SINC peripheral base address.
937 */
SINC_DoSoftwareReset(SINC_Type * base)938 static inline void SINC_DoSoftwareReset(SINC_Type *base)
939 {
940 base->MCR |= SINC_MCR_RST_MASK;
941 base->MCR &= ~SINC_MCR_RST_MASK;
942 }
943
944 /*!
945 * @brief Disable/enable SINC module when the chip enters Doze or Stop mode.
946 *
947 * @param base SINC peripheral base address.
948 * @param disable Used to control if module functional when the chip enters Doze and Stop mode:
949 * - \b true Disable SINC when the chip enters Doze or Stop mode;
950 * - \b false Enable SINC when the chip enters Doze or stop mode.
951 */
SINC_DisableDozeMode(SINC_Type * base,bool disable)952 static inline void SINC_DisableDozeMode(SINC_Type *base, bool disable)
953 {
954 if (disable)
955 {
956 base->MCR |= SINC_MCR_DOZEN_MASK;
957 }
958 else
959 {
960 base->MCR &= ~SINC_MCR_DOZEN_MASK;
961 }
962 }
963
964 /*! @} */
965
966 /*!
967 * @name Clock Control APIs
968 * @{
969 */
970
971 /*!
972 * @brief Check whether selected modulator clocks are ready.
973 *
974 * @note The result of this APIs means all selected modulator clocks are (not) ready.
975 *
976 * @param base SINC peripheral base address.
977 * @param modClkMasks The mask of modulator clocks, please refer to @ref _sinc_modulator_clock.
978 *
979 * @retval true The input mask of modulator clocks are ready.
980 * @retval false The input mask of modulator clocks are not ready.
981 */
SINC_CheckModulatorClockReady(SINC_Type * base,uint32_t modClkMasks)982 static inline bool SINC_CheckModulatorClockReady(SINC_Type *base, uint32_t modClkMasks)
983 {
984 return ((base->SR & (modClkMasks << SINC_SR_MCLKRDY0_SHIFT)) != 0UL);
985 }
986
987 /*!
988 * @brief Disable/enable modulator clocks' output.
989 *
990 * @note By default, modulator clock's output is enabled.
991 *
992 * @param base SINC peripheral base address.
993 * @param modClkMasks The mask of modulator clocks, please refer to @ref _sinc_modulator_clock.
994 * @param disable Used to enable/disable clock output:
995 * - \b true Disable modulator clocks' output;
996 * - \b false Enable modulator clocks' output.
997 */
SINC_DisableModulatorClockOutput(SINC_Type * base,uint32_t modClkMasks,bool disable)998 static inline void SINC_DisableModulatorClockOutput(SINC_Type *base, uint32_t modClkMasks, bool disable)
999 {
1000 if (disable)
1001 {
1002 base->MCR |= (modClkMasks << SINC_MCR_MCLK0DIS_SHIFT);
1003 }
1004 else
1005 {
1006 base->MCR &= ~(modClkMasks << SINC_MCR_MCLK0DIS_SHIFT);
1007 }
1008 }
1009
1010 /*!
1011 * @brief Set the clock divider ratio for the modulator clock.
1012 *
1013 * @param base SINC peripheral base address.
1014 * @param clkPrescale Clock prescale value, please refer to @ref sinc_clock_prescale_t.
1015 */
SINC_SetClkPrescale(SINC_Type * base,sinc_clock_prescale_t clkPrescale)1016 static inline void SINC_SetClkPrescale(SINC_Type *base, sinc_clock_prescale_t clkPrescale)
1017 {
1018 base->MCR = (((base->MCR) & (~SINC_MCR_PRESCALE_MASK)) | SINC_MCR_PRESCALE(clkPrescale));
1019 }
1020
1021 /*!
1022 * @brief Set modulator clock divider value.
1023 *
1024 * @note IMCLK0 = PRE_CLK / modClkDivider, the minimum clock divider ration is 2.
1025 *
1026 * @param base SINC peripheral base address.
1027 * @param modClkDivider Range from 2 to 256, 0 and 1 are prohibited, to obtain a 50% duty cycle in the MCLK output,
1028 * write an even value to \b modClkDivider .
1029 */
SINC_SetModulatorClockDivider(SINC_Type * base,uint32_t modClkDivider)1030 static inline void SINC_SetModulatorClockDivider(SINC_Type *base, uint32_t modClkDivider)
1031 {
1032 assert(modClkDivider != 0UL);
1033 assert(modClkDivider != 1UL);
1034
1035 base->MCR = (((base->MCR) & (~SINC_MCR_MCLKDIV_MASK)) | SINC_MCR_MCLKDIV((modClkDivider - 1UL)));
1036 }
1037
1038 /* !} */
1039
1040 /*!
1041 * @name Channel Functional Control APIs
1042 * @{
1043 */
1044
1045 /*!
1046 * @brief Set channel configurations, including input options, conversion options and protection options.
1047 *
1048 * @param base SINC peripheral base address.
1049 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1050 * @param chConfig Pointer to @ref sinc_channel_config_t structure, must not be NULL.
1051 */
1052 void SINC_SetChannelConfig(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_config_t *chConfig);
1053
1054 /*!
1055 * @brief Set channel input options, including input bit format, input bit source, input bit delay, input clock source,
1056 * input clock edge.
1057 *
1058 * @param base SINC peripheral base address.
1059 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1060 * @param chInputOption Pointer to @ref sinc_channel_input_option_t structure, must not be NULL.
1061 */
1062 void SINC_SetChannelInputOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_input_option_t *chInputOption);
1063
1064 /*!
1065 * @brief Set channel conversion options, including conversion mode, trigger source, and primary filter settings.
1066 *
1067 * @param base SINC peripheral base address.
1068 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1069 * @param chConvOption Pointer to @ref sinc_channel_conv_option_t structure, must not be NULL.
1070 */
1071 void SINC_SetChannelConversionOption(SINC_Type *base, sinc_channel_id_t chId, sinc_channel_conv_option_t *chConvOption);
1072
1073 /*!
1074 * @brief Set channel protection options, including limit check, short-circuit detector, clock-absence detector, and
1075 * zero-crossing detector.
1076 *
1077 * @param base SINC peripheral base address.
1078 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1079 * @param chProtection Pointer to @ref sinc_channel_protection_option_t, must not be NULL.
1080 */
1081 void SINC_SetChannelProtectionOption(SINC_Type *base,
1082 sinc_channel_id_t chId,
1083 sinc_channel_protection_option_t *chProtection);
1084
1085 /*! @} */
1086
1087 /*!
1088 * @name Channel Result/FIFO Low Level Control APIs
1089 * @{
1090 */
1091
1092 /*!
1093 * @brief Read selected channel's result data.
1094 *
1095 * @param base SINC peripheral base address.
1096 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1097 *
1098 * @return Result data of the selected channel, 24 bits width.
1099 */
SINC_ReadChannelResultData(SINC_Type * base,sinc_channel_id_t chId)1100 static inline uint32_t SINC_ReadChannelResultData(SINC_Type *base, sinc_channel_id_t chId)
1101 {
1102 return ((base->CHANNEL[(uint8_t)chId].CRDATA & SINC_CRDATA_RDATA_MASK) >> SINC_CRDATA_RDATA_SHIFT);
1103 }
1104
1105 /*!
1106 * @brief Enable/disable FIFO transfers for the primary filter.
1107 *
1108 * @param base SINC peripheral base address.
1109 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1110 * @param enable Used to enable/disable channl FIFO:
1111 * - \b true Enable channel FIFO.
1112 * - \b false Disable channle FIFO.
1113 */
SINC_EnableChannelFIFO(SINC_Type * base,sinc_channel_id_t chId,bool enable)1114 static inline void SINC_EnableChannelFIFO(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1115 {
1116 if (enable)
1117 {
1118 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_FIFOEN_MASK;
1119 }
1120 else
1121 {
1122 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_FIFOEN_MASK;
1123 }
1124 }
1125
1126 /*!
1127 * @brief Set the FIFO watermark.
1128 *
1129 * @param base SINC peripheral base address.
1130 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1131 * @param fifoWaterMark Specify the fifo watermark, range from 0 to 15.
1132 */
SINC_SetChannelFifoWatermark(SINC_Type * base,sinc_channel_id_t chId,uint8_t fifoWaterMark)1133 static inline void SINC_SetChannelFifoWatermark(SINC_Type *base, sinc_channel_id_t chId, uint8_t fifoWaterMark)
1134 {
1135 base->CHANNEL[(uint8_t)chId].CCFR =
1136 ((base->CHANNEL[(uint8_t)chId].CCFR) & (~SINC_CCFR_FIFOWMK_MASK)) | (SINC_CCFR_FIFOWMK(fifoWaterMark));
1137 }
1138
1139 /*!
1140 * @brief Enable/disable selected channel.
1141 *
1142 * @param base SINC peripheral base address.
1143 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1144 * @param enable Used to enable/disable selected channel:
1145 * - \b true Enable selected channel;
1146 * - \b false Disable selected channel.
1147 */
SINC_EnableChannel(SINC_Type * base,sinc_channel_id_t chId,bool enable)1148 static inline void SINC_EnableChannel(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1149 {
1150 if (enable)
1151 {
1152 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_CHEN_MASK;
1153 }
1154 else
1155 {
1156 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_CHEN_MASK;
1157 }
1158 }
1159
1160 /*!
1161 * @brief Enable/disable selected channel's primary DMA transfers when the channel's FIFO exceeds its watermark.
1162 *
1163 * @param base SINC peripheral base address.
1164 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1165 * @param enable Used to enable/disable primary DMA :
1166 * - \b true Enable primary DMA;
1167 * - \b false Disable primary DMA.
1168 */
SINC_EnableChannelPrimaryDma(SINC_Type * base,sinc_channel_id_t chId,bool enable)1169 static inline void SINC_EnableChannelPrimaryDma(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1170 {
1171 if (enable)
1172 {
1173 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_DMAEN_MASK;
1174 }
1175 else
1176 {
1177 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_DMAEN_MASK;
1178 }
1179 }
1180
1181 #if (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL)
1182 /*!
1183 * @brief Set selected channel's alternate DMA source selection.
1184 *
1185 * @param base SINC peripheral base address.
1186 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1187 * @param altDmaSource Specify the trigger source for alternate DMA, please refer to @ref sinc_alternate_dma_source_t.
1188 */
SINC_SetChannelAltDmaSource(SINC_Type * base,sinc_channel_id_t chId,sinc_alternate_dma_source_t altDmaSource)1189 static inline void SINC_SetChannelAltDmaSource(SINC_Type *base,
1190 sinc_channel_id_t chId,
1191 sinc_alternate_dma_source_t altDmaSource)
1192 {
1193 base->CHANNEL[(uint8_t)chId].CACFR =
1194 ((base->CHANNEL[(uint8_t)chId].CACFR & ~SINC_CACFR_ADMASEL_MASK) | SINC_CACFR_ADMASEL(altDmaSource));
1195 }
1196 #endif /* (defined(FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) && FSL_FEATURE_SINC_CACFR_HAS_ADMASEL) */
1197
1198 /*!
1199 * @brief Set selected channel's result data format.
1200 *
1201 * @param base SINC peripheral base address.
1202 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1203 * @param dataFormat Specify the result data format, please refer to @ref sinc_result_data_format_t.
1204 */
SINC_SetChannelResultDataFormat(SINC_Type * base,sinc_channel_id_t chId,sinc_result_data_format_t dataFormat)1205 static inline void SINC_SetChannelResultDataFormat(SINC_Type *base,
1206 sinc_channel_id_t chId,
1207 sinc_result_data_format_t dataFormat)
1208 {
1209 if (dataFormat == kSINC_LeftJustifiedSigned)
1210 {
1211 base->CHANNEL[(uint8_t)chId].CCFR &= ~SINC_CCFR_RDFMT_MASK;
1212 }
1213 else
1214 {
1215 base->CHANNEL[(uint8_t)chId].CCFR |= SINC_CCFR_RDFMT_MASK;
1216 }
1217 }
1218
1219 /*!
1220 * @brief Get the number of remaining data entries in the FIFO.
1221 *
1222 * @param base SINC peripheral base address.
1223 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1224 *
1225 * @return The number of remaining data entries in the FIFO.
1226 */
SINC_GetChannelFifoCount(SINC_Type * base,sinc_channel_id_t chId)1227 static inline uint8_t SINC_GetChannelFifoCount(SINC_Type *base, sinc_channel_id_t chId)
1228 {
1229 return (uint8_t)(base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_FIFOAVIL_MASK);
1230 }
1231
1232 /*!
1233 * @brief Check whether the data in selected channel's result data register is stable when FIFO is disabled.
1234 *
1235 * @param base SINC peripheral base address.
1236 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1237 *
1238 * @retval true Data in selected channel's result data regiter is stable.
1239 * @retval false Data in selected channel's result data register is not stable.
1240 */
SINC_CheckChannelResultDataReady(SINC_Type * base,sinc_channel_id_t chId)1241 static inline bool SINC_CheckChannelResultDataReady(SINC_Type *base, sinc_channel_id_t chId)
1242 {
1243 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_RDRS_MASK) != SINC_CSR_RDRS_MASK);
1244 }
1245
1246 /*!
1247 * @brief Check whether selected channel's FIFO is empty.
1248 *
1249 * @param base SINC peripheral base address.
1250 * @param chId The id of sinc channel to check.
1251 *
1252 * @retval true Selected channel's FIFO is empty.
1253 * @retval false Selected channel's FIFO is not empty.
1254 */
SINC_CheckChannelFifoEmpty(SINC_Type * base,sinc_channel_id_t chId)1255 static inline bool SINC_CheckChannelFifoEmpty(SINC_Type *base, sinc_channel_id_t chId)
1256 {
1257 return ((base->SR & (SINC_SR_FIFOEMPTY0_MASK << (uint32_t)chId)) != 0UL);
1258 }
1259
1260 /*! @} */
1261
1262 /*!
1263 * @name Channel Conversion Low Level Control APIs
1264 * @{
1265 */
1266
1267 /*!
1268 * @brief Trigger selected channel's conversion.
1269 *
1270 * @param base SINC peripheral base address.
1271 * @param chMask The mask of channels to trigger.
1272 */
SINC_AffirmChannelSoftwareTrigger(SINC_Type * base,uint32_t chMask)1273 static inline void SINC_AffirmChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask)
1274 {
1275 base->MCR |= chMask;
1276 }
1277
1278 /*!
1279 * @brief Negate the trigger of selected channel.
1280 *
1281 * @param base SINC peripheral base address.
1282 * @param chMask The mask of channels.
1283 */
SINC_NegateChannelSoftwareTrigger(SINC_Type * base,uint32_t chMask)1284 static inline void SINC_NegateChannelSoftwareTrigger(SINC_Type *base, uint32_t chMask)
1285 {
1286 base->MCR &= ~chMask;
1287 }
1288
1289 /*!
1290 * @brief Set selected channel's conversion mode.
1291 *
1292 * @param base SINC peripheral base address.
1293 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1294 * @param mode The conversion mode to set, please refer to @ref sinc_conv_mode_t.
1295 */
SINC_SetChannelConversionMode(SINC_Type * base,sinc_channel_id_t chId,sinc_conv_mode_t mode)1296 static inline void SINC_SetChannelConversionMode(SINC_Type *base, sinc_channel_id_t chId, sinc_conv_mode_t mode)
1297 {
1298 base->CHANNEL[(uint8_t)chId].CDR = ((base->CHANNEL[(uint8_t)chId].CDR & ~SINC_CDR_PFCM_MASK) | SINC_CDR_PFCM(mode));
1299 }
1300
1301 /*!
1302 * @brief Set selected channel's trigger source.
1303 *
1304 * @param base SINC peripheral base address.
1305 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1306 * @param triggerSource Trigger source to set, please refer to @ref sinc_conv_trigger_source_t.
1307 */
SINC_SetChannelTriggerSource(SINC_Type * base,sinc_channel_id_t chId,sinc_conv_trigger_source_t triggerSource)1308 static inline void SINC_SetChannelTriggerSource(SINC_Type *base,
1309 sinc_channel_id_t chId,
1310 sinc_conv_trigger_source_t triggerSource)
1311 {
1312 base->CHANNEL[(uint8_t)chId].CCFR =
1313 (((base->CHANNEL[(uint8_t)chId].CCFR) & ~(SINC_CCFR_ITLVL_MASK | SINC_CCFR_ITSEL_MASK)) |
1314 SINC_CCFR_ITLVL((((uint32_t)triggerSource) & 0x4UL) >> 2UL) |
1315 SINC_CCFR_ITSEL((uint32_t)triggerSource & 0x3UL));
1316 }
1317
1318 /*!
1319 * @brief Set multipurpose data to selected channel.
1320 *
1321 * @note If input bit format is set as ManchesterCode, multipurpose data indicates the Manchester decoder threshold
1322 * value and is 11 bits width; if input bit format is set as parallel, multipurpose data indicates the parallel 16-bit
1323 * data and is 16 bits width; if input bit format is set as serial, multipurpose data indicates the serial data and is
1324 * 32 bits width.
1325 *
1326 * @param base SINC peripheral base address.
1327 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1328 * @param data Multipurpose data to set.
1329 */
SINC_SetChannelMultipurposeData(SINC_Type * base,sinc_channel_id_t chId,uint32_t data)1330 static inline void SINC_SetChannelMultipurposeData(SINC_Type *base, sinc_channel_id_t chId, uint32_t data)
1331 {
1332 base->CHANNEL[(uint8_t)chId].CMPDATA = SINC_CMPDATA_MPDATA(data);
1333 }
1334
1335 /*!
1336 * @brief Set selected channel's PF order.
1337 *
1338 * @param base SINC peripheral base address.
1339 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1340 * @param pfOrder Primary filter order to set, please refer to @ref sinc_primary_filter_order_t
1341 */
SINC_SetChannelPfOrder(SINC_Type * base,sinc_channel_id_t chId,sinc_primary_filter_order_t pfOrder)1342 static inline void SINC_SetChannelPfOrder(SINC_Type *base, sinc_channel_id_t chId, sinc_primary_filter_order_t pfOrder)
1343 {
1344 base->CHANNEL[(uint8_t)chId].CDR =
1345 ((base->CHANNEL[(uint8_t)chId].CDR) & (~SINC_CDR_PFORD_MASK)) | (SINC_CDR_PFORD(pfOrder));
1346 }
1347
1348 /*!
1349 * @brief Set selected channel's PF over sample rate.
1350 *
1351 * @note If PF order is third order and data format is signed, the maximum OSR value is 1289, if PF order is third
1352 * order and data format is unsigned, the maximum OSR value is 1624, otherwise the maximum OSR value is 2047.
1353 *
1354 * @param base SINC peripheral base address.
1355 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1356 * @param pfOsr Control the channel's PF OSR, the minimum permissible value is 3, low value produce unpredictable
1357 * result, the maximum permissible value depend on PF order and the desired data format.
1358 */
SINC_SetChannelPfOsr(SINC_Type * base,sinc_channel_id_t chId,uint16_t pfOsr)1359 static inline void SINC_SetChannelPfOsr(SINC_Type *base, sinc_channel_id_t chId, uint16_t pfOsr)
1360 {
1361 base->CHANNEL[(uint8_t)chId].CDR =
1362 ((base->CHANNEL[(uint8_t)chId].CDR) & (~SINC_CDR_PFOSR_MASK)) | (SINC_CDR_PFOSR(pfOsr));
1363 }
1364
1365 /*!
1366 * @brief set selected channel's HPF DC remover Alpha coefficient.
1367 *
1368 * @param base SINC peripheral base address.
1369 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1370 * @param pfHpfAlphaCoeff Specify the HPF alpha coefficient or disable HPF as described in @ref
1371 * sin_primary_filter_hpf_alpha_coeff_t.
1372 */
SINC_SetChannelPfHpfAlphaCoeff(SINC_Type * base,sinc_channel_id_t chId,sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff)1373 static inline void SINC_SetChannelPfHpfAlphaCoeff(SINC_Type *base,
1374 sinc_channel_id_t chId,
1375 sin_primary_filter_hpf_alpha_coeff_t pfHpfAlphaCoeff)
1376 {
1377 base->CHANNEL[(uint8_t)chId].CACFR =
1378 ((base->CHANNEL[(uint8_t)chId].CACFR) & (~SINC_CACFR_HPFA_MASK)) | (SINC_CACFR_HPFA(pfHpfAlphaCoeff));
1379 }
1380
1381 /*!
1382 * @brief Set the value that shifts the PF data for the correct 24-bit precision.
1383 *
1384 * @param base SINC peripheral base address.
1385 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1386 * @param pfShiftDirection Specify the PF shift direction, including right and left.
1387 * @param pfShiftBitsNum Specify the PF shift value, range from 0 to 15.
1388 */
SINC_SetChannelPfShiftConfig(SINC_Type * base,sinc_channel_id_t chId,sinc_primary_filter_shift_direction_t pfShiftDirection,uint8_t pfShiftBitsNum)1389 static inline void SINC_SetChannelPfShiftConfig(SINC_Type *base,
1390 sinc_channel_id_t chId,
1391 sinc_primary_filter_shift_direction_t pfShiftDirection,
1392 uint8_t pfShiftBitsNum)
1393 {
1394 base->CHANNEL[(uint8_t)chId].CCFR = ((base->CHANNEL[(uint8_t)chId].CCFR) & (~SINC_CCFR_PFSFT_MASK)) |
1395 (SINC_CCFR_PFSFT((uint32_t)pfShiftDirection | (uint32_t)pfShiftBitsNum));
1396 }
1397
1398 /*!
1399 * @brief Set the bias offset for the selected channel's PF.
1400 *
1401 * @param base SINC peripheral base address.
1402 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1403 * @param pfBiasSign Specify the bias sign, please refer to @ref sinc_primary_filter_bias_sign_t for details.
1404 * @param pfBiasValue The bias value to subtracted from the output of PF shift block, range from 0 to 0x7FFFFFUL.
1405 */
SINC_SetChannelPfBiasConfig(SINC_Type * base,sinc_channel_id_t chId,sinc_primary_filter_bias_sign_t pfBiasSign,uint32_t pfBiasValue)1406 static inline void SINC_SetChannelPfBiasConfig(SINC_Type *base,
1407 sinc_channel_id_t chId,
1408 sinc_primary_filter_bias_sign_t pfBiasSign,
1409 uint32_t pfBiasValue)
1410 {
1411 base->CHANNEL[(uint8_t)chId].CBIAS = (uint32_t)pfBiasSign << 31UL | pfBiasValue << SINC_CBIAS_BIAS_SHIFT;
1412 }
1413
1414 /*!
1415 * @brief Enable/disable selected channel's primary filter.
1416 *
1417 * @param base SINC peripheral base address.
1418 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1419 * @param enable Used to enable primary filter:
1420 * - \b true Enable channel's PF;
1421 * - \b false Disable channel's PF.
1422 */
SINC_EnableChannelPrimaryFilter(SINC_Type * base,sinc_channel_id_t chId,bool enable)1423 static inline void SINC_EnableChannelPrimaryFilter(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1424 {
1425 if (enable)
1426 {
1427 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_PFEN_MASK;
1428 }
1429 else
1430 {
1431 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_PFEN_MASK;
1432 }
1433 }
1434
1435 /*!
1436 * @brief Check whether selected channel's multipurpose data is ready to write parallel or serial data.
1437 *
1438 * @param base SINC peripheral base address.
1439 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1440 *
1441 * @retval true Selected channel's multipurpose data is ready to write parallel or serial data.
1442 * @retval false Selected channel's multipurpose data is not ready to write parallel or serial data.
1443 */
SINC_CheckChannelParallelSerialDataReady(SINC_Type * base,sinc_channel_id_t chId)1444 static inline bool SINC_CheckChannelParallelSerialDataReady(SINC_Type *base, sinc_channel_id_t chId)
1445 {
1446 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_PSRDY_MASK) == SINC_CSR_PSRDY_MASK);
1447 }
1448
1449 /*!
1450 * @brief Check whether primary CIC filter saturation occurred.
1451 *
1452 * @param base SINC peripheral base address.
1453 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1454 *
1455 * @retval true Selected channel's primary CIC filter saturation occurred.
1456 * @retval false Selected channel's primary CIC filter saturation did not occurred.
1457 */
SINC_CheckChannelPrimaryCICSaturation(SINC_Type * base,sinc_channel_id_t chId)1458 static inline bool SINC_CheckChannelPrimaryCICSaturation(SINC_Type *base, sinc_channel_id_t chId)
1459 {
1460 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_PFSAT_MASK) == SINC_CSR_PFSAT_MASK);
1461 }
1462
1463 /*!
1464 * @brief Check whether HPF saturation occurred.
1465 *
1466 * @param base SINC peripheral base address.
1467 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1468 *
1469 * @retval true Selected channel's HPF saturation occurred.
1470 * @retval false Selected channel's HPF saturation did not occurred.
1471 */
SINC_CheckChannelHPFSaturation(SINC_Type * base,sinc_channel_id_t chId)1472 static inline bool SINC_CheckChannelHPFSaturation(SINC_Type *base, sinc_channel_id_t chId)
1473 {
1474 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_HPFSAT_MASK) == SINC_CSR_HPFSAT_MASK);
1475 }
1476
1477 /*!
1478 * @brief Check whether Shift saturation occurred.
1479 *
1480 * @param base SINC peripheral base address.
1481 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1482 *
1483 * @retval true Selected channel's shift saturation occurred.
1484 * @retval false Selected channel's shift saturation did not occurred.
1485 */
SINC_CheckChannelShiftSaturation(SINC_Type * base,sinc_channel_id_t chId)1486 static inline bool SINC_CheckChannelShiftSaturation(SINC_Type *base, sinc_channel_id_t chId)
1487 {
1488 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_SFTSAT_MASK) == SINC_CSR_SFTSAT_MASK);
1489 }
1490
1491 /*!
1492 * @brief Check whether bias saturation occurred.
1493 *
1494 * @param base SINC peripheral base address.
1495 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1496 *
1497 * @retval true Selected channel's bias saturation occurred.
1498 * @retval false Selected channel's bias saturation did not occurred.
1499 */
SINC_CheckChannelBiasSaturation(SINC_Type * base,sinc_channel_id_t chId)1500 static inline bool SINC_CheckChannelBiasSaturation(SINC_Type *base, sinc_channel_id_t chId)
1501 {
1502 return ((base->CHANNEL[(uint8_t)chId].CSR & SINC_CSR_BIASSAT_MASK) == SINC_CSR_BIASSAT_MASK);
1503 }
1504
1505 /*!
1506 * @brief Get selected channel's number of conversions.
1507 *
1508 * @param base SINC peripheral base address.
1509 * @param chId Selected channel id, refer to @ref sinc_channel_id_t for details.
1510 * @return uint8_t Selected channel's number of conversions.
1511 */
1512 uint8_t SINC_GetChannelConversionCount(SINC_Type *base, sinc_channel_id_t chId);
1513
1514 /*!
1515 * @brief Check whether the selected channel is in conversion.
1516 *
1517 * @param base SINC peripheral base address.
1518 * @param chId The id of sinc channel to check.
1519 *
1520 * @retval false Selected channel conversion not in progress.
1521 * @retval true Selected channel conversion in progress.
1522 */
SINC_CheckChannelConvProgress(SINC_Type * base,sinc_channel_id_t chId)1523 static inline bool SINC_CheckChannelConvProgress(SINC_Type *base, sinc_channel_id_t chId)
1524 {
1525 return ((base->SR & (((uint32_t)SINC_SR_CIP0_MASK) << (uint32_t)chId)) != 0UL);
1526 }
1527
1528 /*!
1529 * @brief Check whether the selected channel is ready for conversion.
1530 *
1531 * @param base SINC peripheral base address.
1532 * @param chId The id of sinc channel to check.
1533 *
1534 * @retval true Selected channel is ready for conversion.
1535 * @retval false Selected channel is not ready for conversion.
1536 */
SINC_CheckChannelReadyForConv(SINC_Type * base,sinc_channel_id_t chId)1537 static inline bool SINC_CheckChannelReadyForConv(SINC_Type *base, sinc_channel_id_t chId)
1538 {
1539 return ((base->SR & (((uint32_t)SINC_SR_CHRDY0_MASK) << (uint32_t)chId)) != 0UL);
1540 }
1541
1542 /*! @} */
1543
1544 /*!
1545 * @name Channel Protection Low Level Control APIs
1546 * @{
1547 */
1548
1549 /*!
1550 * @brief Set selected channel's low-limit threshold value.
1551 *
1552 * @note When the data exceeds the low-limit threshold value, a low-limit event occurs, and the limit threshold format
1553 * is determines by channel's result data format @ref sinc_result_data_format_t.
1554 *
1555 * @note Low limit value must lower than high limit value, otherwise the low-limit threshold does not work.
1556 *
1557 * @param base SINC peripheral base address.
1558 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1559 * @param lowLimitThreshold Specify the low-limit threshold value, range from 0 to 0xFFFFFFUL.
1560 */
SINC_SetChannelLowLimitThreshold(SINC_Type * base,sinc_channel_id_t chId,uint32_t lowLimitThreshold)1561 static inline void SINC_SetChannelLowLimitThreshold(SINC_Type *base, sinc_channel_id_t chId, uint32_t lowLimitThreshold)
1562 {
1563 base->CHANNEL[(uint8_t)chId].CLOLMT = SINC_CLOLMT_LOLMT(lowLimitThreshold);
1564 }
1565
1566 /*!
1567 * @brief Set selected channel's high-limit threshold value.
1568 *
1569 * @note When the data exceeds the high-limit threshold value, a high-limit event occurs, and the limit threshold format
1570 * is determines by channel's result data format @ref sinc_result_data_format_t.
1571 *
1572 * @param base SINC peripheral base address.
1573 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1574 * @param highLimitThreshold Specify the high-limit threshold value, range from 0 to 0xFFFFFFUL.
1575 */
SINC_SetChannelHighLimitThreshold(SINC_Type * base,sinc_channel_id_t chId,uint32_t highLimitThreshold)1576 static inline void SINC_SetChannelHighLimitThreshold(SINC_Type *base,
1577 sinc_channel_id_t chId,
1578 uint32_t highLimitThreshold)
1579 {
1580 base->CHANNEL[(uint8_t)chId].CHILMT = SINC_CHILMT_HILMT(highLimitThreshold);
1581 }
1582
1583 /*!
1584 * @brief Set selected channel's limit detector mode.
1585 *
1586 * @param base SINC peripheral base address.
1587 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1588 * @param mode Specify the mode of limit detector, please refer to @ref sinc_limit_detector_mode_t.
1589 */
SINC_SetChannelLimitDetectorMode(SINC_Type * base,sinc_channel_id_t chId,sinc_limit_detector_mode_t mode)1590 static inline void SINC_SetChannelLimitDetectorMode(SINC_Type *base,
1591 sinc_channel_id_t chId,
1592 sinc_limit_detector_mode_t mode)
1593 {
1594 if (mode == kSINC_Lmt_Disabled)
1595 {
1596 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_LMTEN_MASK;
1597 }
1598 else
1599 {
1600 base->CHANNEL[(uint8_t)chId].CPROT =
1601 (base->CHANNEL[(uint8_t)chId].CPROT & ~SINC_CPROT_LMTOP_MASK) | SINC_CPROT_LMTOP((uint32_t)mode & 0x3UL);
1602 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_LMTEN_MASK;
1603 }
1604 }
1605
1606 /*!
1607 * @brief Enable/disable selected channel's high limit break signal.
1608 *
1609 * @param base SINC peripheral base address.
1610 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1611 * @param enable Used to enable/disable high limit break signal:
1612 * - \b true Enable the automatic assertion of the BREAK_HIGH signal when SINC detects a high-limit event on
1613 * the selected channel.
1614 * - \b false Disable high limit break signal.
1615 */
SINC_EnableChannelHighLimitBreakSignal(SINC_Type * base,sinc_channel_id_t chId,bool enable)1616 static inline void SINC_EnableChannelHighLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1617 {
1618 if (enable)
1619 {
1620 base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_HLMTBK_MASK;
1621 }
1622 else
1623 {
1624 base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_HLMTBK_MASK;
1625 }
1626 }
1627
1628 /*!
1629 * @brief Enable/disable selected channel's window limit break signal.
1630 *
1631 * @param base SINC peripheral base address.
1632 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1633 * @param enable Used to enable/disable window limit break signal:
1634 * - \b true Enable the automatic assertion of the BREAK_WIN signal when SINC detects a window-limit event on
1635 * the selected channel.
1636 * - \b false Disable window limit break signal.
1637 */
SINC_EnableChannelWindowLimitBreakSignal(SINC_Type * base,sinc_channel_id_t chId,bool enable)1638 static inline void SINC_EnableChannelWindowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1639 {
1640 if (enable)
1641 {
1642 base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_WLMTBK_MASK;
1643 }
1644 else
1645 {
1646 base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_WLMTBK_MASK;
1647 }
1648 }
1649
1650 /*!
1651 * @brief Enable/disable selected channel's low limit break signal.
1652 *
1653 * @param base SINC peripheral base address.
1654 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1655 * @param enable Used to enable/disable low limit break signal:
1656 * - \b true Enable the automatic assertion of the BREAK_LOW signal when SINC detects a low-limit event on
1657 * the selected channel.
1658 * - \b false Disable low limit break signal.
1659 */
SINC_EnableChannelLowLimitBreakSignal(SINC_Type * base,sinc_channel_id_t chId,bool enable)1660 static inline void SINC_EnableChannelLowLimitBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1661 {
1662 if (enable)
1663 {
1664 base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_HLMTBK_MASK;
1665 }
1666 else
1667 {
1668 base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_HLMTBK_MASK;
1669 }
1670 }
1671
1672 /*!
1673 * @brief Set selected channel's short-circuit detector operate mode.
1674 *
1675 * @param base SINC peripheral base address.
1676 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1677 * @param opMode Specify the operate mode to set, please refer to @ref sinc_scd_operate_mode_t.
1678 */
SINC_SetChannelScdOperateMode(SINC_Type * base,sinc_channel_id_t chId,sinc_scd_operate_mode_t opMode)1679 static inline void SINC_SetChannelScdOperateMode(SINC_Type *base,
1680 sinc_channel_id_t chId,
1681 sinc_scd_operate_mode_t opMode)
1682 {
1683 if (opMode == kSINC_Scd_OperateDisabled)
1684 {
1685 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_SCDEN_MASK;
1686 }
1687 else
1688 {
1689 base->CHANNEL[(uint8_t)chId].CPROT =
1690 ((base->CHANNEL[(uint8_t)chId].CPROT & ~SINC_CPROT_SCDCM_MASK) | SINC_CPROT_SCDCM(opMode));
1691 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_SCDEN_MASK;
1692 }
1693 }
1694
1695 /*!
1696 * @brief Set selected channel's Scd limit threshold.
1697 *
1698 * @note The SCD counter tracks the number of received bits with the same repeating value(always 0 or always 1, set by
1699 * SINC_SetChannelScdOption()), if that
1700 * number exceeds the scdLimitThreshold, an SCD event occurs on the associated channel.
1701 *
1702 * @param base SINC peripheral base address.
1703 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1704 * @param u8ScdLimitThreshold Specify the threshold value for the SCD counter, range from 2 to 255.
1705 */
SINC_SetChannelScdLimitThreshold(SINC_Type * base,sinc_channel_id_t chId,uint8_t u8ScdLimitThreshold)1706 static inline void SINC_SetChannelScdLimitThreshold(SINC_Type *base,
1707 sinc_channel_id_t chId,
1708 uint8_t u8ScdLimitThreshold)
1709 {
1710 assert(u8ScdLimitThreshold != 0U);
1711 assert(u8ScdLimitThreshold != 1U);
1712
1713 base->CHANNEL[(uint8_t)chId].CPROT =
1714 ((base->CHANNEL[(uint8_t)chId].CPROT) & (~SINC_CPROT_SCDLMT_MASK)) | (SINC_CPROT_SCDLMT(u8ScdLimitThreshold));
1715 }
1716
1717 /*!
1718 * @brief Set selected channel's SDC option.
1719 *
1720 * @param base SINC peripheral base address.
1721 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1722 * @param option Specify which repeating bit value increments the SCD counter.
1723 */
SINC_SetChannelScdOption(SINC_Type * base,sinc_channel_id_t chId,sinc_scd_option_t option)1724 static inline void SINC_SetChannelScdOption(SINC_Type *base, sinc_channel_id_t chId, sinc_scd_option_t option)
1725 {
1726 base->CHANNEL[(uint8_t)chId].CPROT =
1727 ((base->CHANNEL[(uint8_t)chId].CPROT) & (~SINC_CPROT_SCDOP_MASK)) | (SINC_CPROT_SCDOP(option));
1728 }
1729
1730 /*!
1731 * @brief Enable/disable the automatic assertion of the BREAK_SCD signal when SINC detects an SCD event on the selected
1732 * channel.
1733 *
1734 * @param base SINC peripheral base address.
1735 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1736 * @param enable Used to enable/disable SCD break signal:
1737 * - \b true Enable SCD break signal.
1738 * - \b false Disable SCD break signal.
1739 */
SINC_EnableChannelScdBreakSignal(SINC_Type * base,sinc_channel_id_t chId,bool enable)1740 static inline void SINC_EnableChannelScdBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1741 {
1742 if (enable)
1743 {
1744 base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_SCDBK_MASK;
1745 }
1746 else
1747 {
1748 base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_SCDBK_MASK;
1749 }
1750 }
1751
1752 /*!
1753 * @brief Set the threshold value for the CAD counter.
1754 *
1755 * @note The CAD counter tracks the number of clock cycles during which SINC does not detect a clock, if that number
1756 * exceeds the threshold value, a CAD event occurs on the selected channel.
1757 *
1758 * @param base SINC peripheral base address.
1759 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1760 * @param cadLimitThreshold Specify the threshold value for the CAD counter, please refer to @ref sinc_cad_threshold_t.
1761 */
SINC_SetChannelCadLimitThreshold(SINC_Type * base,sinc_channel_id_t chId,sinc_cad_threshold_t cadLimitThreshold)1762 static inline void SINC_SetChannelCadLimitThreshold(SINC_Type *base,
1763 sinc_channel_id_t chId,
1764 sinc_cad_threshold_t cadLimitThreshold)
1765 {
1766 base->CHANNEL[(uint8_t)chId].CPROT =
1767 ((base->CHANNEL[(uint8_t)chId].CPROT) & (~SINC_CPROT_CADLMT_MASK)) | (SINC_CPROT_CADLMT(cadLimitThreshold));
1768 if (cadLimitThreshold == kSINC_Cad_Disabled)
1769 {
1770 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_CADEN_MASK;
1771 }
1772 else
1773 {
1774 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_CADEN_MASK;
1775 }
1776 }
1777
1778 /*!
1779 * @brief Enable/disable the automatic assertion of the BREAK_CAD signal when SINC detects a CAD event on the assoicated
1780 * channel.
1781 *
1782 * @param base SINC peripheral base address.
1783 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1784 * @param enable Used to enable/disble CAD break signal:
1785 * - \b true Enable selected channel's CAD break signal;
1786 * - \b false Disable selected channel's CAD break signal.
1787 */
SINC_EnableChannelCadBreakSignal(SINC_Type * base,sinc_channel_id_t chId,bool enable)1788 static inline void SINC_EnableChannelCadBreakSignal(SINC_Type *base, sinc_channel_id_t chId, bool enable)
1789 {
1790 if (enable)
1791 {
1792 base->CHANNEL[(uint8_t)chId].CPROT |= SINC_CPROT_CADBK_MASK;
1793 }
1794 else
1795 {
1796 base->CHANNEL[(uint8_t)chId].CPROT &= ~SINC_CPROT_CADBK_MASK;
1797 }
1798 }
1799
1800 /*!
1801 * @brief Set selected channel's zero-crossing detector operate mode.
1802 *
1803 * @param base SINC peripheral base address.
1804 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1805 * @param opMode Specify the operate mode, please refer to @ref sinc_zero_cross_operate_mode_t.
1806 */
SINC_SetChannelZcdOperateMode(SINC_Type * base,sinc_channel_id_t chId,sinc_zero_cross_operate_mode_t opMode)1807 static inline void SINC_SetChannelZcdOperateMode(SINC_Type *base,
1808 sinc_channel_id_t chId,
1809 sinc_zero_cross_operate_mode_t opMode)
1810 {
1811 if (opMode == kSINC_ZCD_Disabled)
1812 {
1813 base->CHANNEL[(uint8_t)chId].CCR &= ~SINC_CCR_ZCDEN_MASK;
1814 }
1815 else
1816 {
1817 base->CHANNEL[(uint8_t)chId].CCFR =
1818 ((base->CHANNEL[(uint8_t)chId].CCFR) & (~SINC_CCFR_ZCOP_MASK)) | (SINC_CCFR_ZCOP(opMode));
1819 base->CHANNEL[(uint8_t)chId].CCR |= SINC_CCR_ZCDEN_MASK;
1820 }
1821 }
1822
1823 /*! @} */
1824
1825 /*!
1826 * @name Channel Debug Low Level Control APIs
1827 * @{
1828 */
1829
1830 #if !((defined(FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX) && FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX))
1831 /*!
1832 * @brief Set selected channel's pulse trigger mux.
1833 *
1834 * @param base SINC peripheral base address.
1835 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1836 * @param pulseTrigMux Used to selected the signal for pulse-trigger output.
1837 */
SINC_SetChannelPulseTriggerMux(SINC_Type * base,sinc_channel_id_t chId,sinc_pulse_trigger_mux_t pulseTrigMux)1838 static inline void SINC_SetChannelPulseTriggerMux(SINC_Type *base,
1839 sinc_channel_id_t chId,
1840 sinc_pulse_trigger_mux_t pulseTrigMux)
1841 {
1842 base->CHANNEL[(uint8_t)chId].CACFR =
1843 ((base->CHANNEL[(uint8_t)chId].CACFR & ~SINC_CACFR_PTMUX_MASK) | SINC_CACFR_PTMUX(pulseTrigMux));
1844 }
1845 #endif /* !(defined(FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX) && FSL_FEATURE_SINC_CACFR_HAS_NO_PTMUX) */
1846
1847 /*!
1848 * @brief Set selected channel's debug output.
1849 *
1850 * @param base SINC peripheral base address.
1851 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1852 * @param debugOutput Used to select debug output, please refer to @ref sinc_debug_output_t.
1853 */
SINC_SetChannelDebugOutput(SINC_Type * base,sinc_channel_id_t chId,sinc_debug_output_t debugOutput)1854 static inline void SINC_SetChannelDebugOutput(SINC_Type *base, sinc_channel_id_t chId, sinc_debug_output_t debugOutput)
1855 {
1856 base->CHANNEL[(uint8_t)chId].CCR =
1857 ((base->CHANNEL[(uint8_t)chId].CCR & ~SINC_CCR_DBGSEL_MASK) | SINC_CCR_DBGSEL(debugOutput));
1858 }
1859
1860 /*!
1861 * @brief Start selected channel's debug data latch proceduce.
1862 *
1863 * @param base SINC peripheral base address.
1864 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1865 */
SINC_LatchChannelDebugProceduce(SINC_Type * base,sinc_channel_id_t chId)1866 static inline void SINC_LatchChannelDebugProceduce(SINC_Type *base, sinc_channel_id_t chId)
1867 {
1868 base->CHANNEL[(uint8_t)chId].CSR |= SINC_CSR_SRDS_MASK;
1869 }
1870
1871 /*!
1872 * @brief Check if the selected channel's debug data is valid.
1873 *
1874 * @param base SINC peripheral base address.
1875 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1876 *
1877 * @retval true Data is valid.
1878 * @retval false Data is invalid.
1879 */
SINC_CheckChannelDebugDataValid(SINC_Type * base,sinc_channel_id_t chId)1880 static inline bool SINC_CheckChannelDebugDataValid(SINC_Type *base, sinc_channel_id_t chId)
1881 {
1882 return ((base->CHANNEL[(uint8_t)chId].CSR & (SINC_CSR_SRDS_MASK | SINC_CSR_DBGRS_MASK)) == 0UL);
1883 }
1884
1885 /*!
1886 * @brief Return selected channel's the debug data that requested by SINC_SetChannelDebugOutput().
1887 *
1888 * @param base SINC peripheral base address.
1889 * @param chId Selected channel id, please refer to @ref sinc_channel_id_t.
1890 *
1891 * @return Selected channel's debug data.
1892 */
SINC_GetChannelDebugData(SINC_Type * base,sinc_channel_id_t chId)1893 static inline uint32_t SINC_GetChannelDebugData(SINC_Type *base, sinc_channel_id_t chId)
1894 {
1895 return base->CHANNEL[(uint8_t)chId].CDBGR;
1896 }
1897
1898 /*! @} */
1899
1900 /*!
1901 * @name Interrupt Control APIs
1902 * @{
1903 */
1904
1905 /*!
1906 * @brief Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on.
1907 *
1908 * @param base SINC peripheral base address.
1909 * @param interruptMasks Mask of interrupts to enable, should be the OR'ed value of @ref sinc_interrupt_enable_t.
1910 */
SINC_EnableInterrupts(SINC_Type * base,uint64_t interruptMasks)1911 static inline void SINC_EnableInterrupts(SINC_Type *base, uint64_t interruptMasks)
1912 {
1913 uint32_t normalIntMask;
1914 uint32_t errorIntMask;
1915 uint32_t fifoCadIntMask;
1916
1917 /*
1918 * #define SINC_DECODE_INTERRUPT(interruptMask) \
1919 * normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \
1920 * errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \
1921 * fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL))
1922 */
1923 SINC_DECODE_INTERRUPT(interruptMasks);
1924
1925 base->NIE |= SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_COCIE) |
1926 SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_CHFIE) |
1927 SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_ZCDIE);
1928
1929 base->EIE |= SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_SCDIE) |
1930 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_WLMTIE) |
1931 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_LLMTIE) |
1932 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_HLMTIE);
1933
1934 base->FIFOIE |= SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FUNFIE) |
1935 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FOVFIE) |
1936 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_CADIE) |
1937 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_SATIE);
1938 }
1939
1940 /*!
1941 * @brief Enable the mask of interrupts, such as channel data ready interrupt, channel limit detect interrupt and so on.
1942 *
1943 * @param base SINC peripheral base address.
1944 * @param interruptMasks Mask of interrupts to disable, should be the OR'ed value of @ref sinc_interrupt_enable_t.
1945 */
SINC_DisableInterrupts(SINC_Type * base,uint64_t interruptMasks)1946 static inline void SINC_DisableInterrupts(SINC_Type *base, uint64_t interruptMasks)
1947 {
1948 uint32_t normalIntMask;
1949 uint32_t errorIntMask;
1950 uint32_t fifoCadIntMask;
1951
1952 /*
1953 * #define SINC_DECODE_INTERRUPT(interruptMask) \
1954 * normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \
1955 * errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \
1956 * fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL))
1957 */
1958 SINC_DECODE_INTERRUPT(interruptMasks);
1959
1960 base->NIE &= ~(SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_COCIE) |
1961 SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_CHFIE) |
1962 SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_ZCDIE));
1963
1964 base->EIE &= ~(SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_SCDIE) |
1965 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_WLMTIE) |
1966 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_LLMTIE) |
1967 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_HLMTIE));
1968
1969 base->FIFOIE &= ~(SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FUNFIE) |
1970 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FOVFIE) |
1971 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_CADIE) |
1972 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_SATIE));
1973 }
1974
1975 /*!
1976 * @brief Get interrupt status flags.
1977 *
1978 * @param base SINC peripheral base address.
1979 *
1980 * @return SINC module's interrupt status flags, the OR'ed value of @ref sinc_interrupt_status_t.
1981 */
SINC_GetInterruptStatus(SINC_Type * base)1982 static inline uint64_t SINC_GetInterruptStatus(SINC_Type *base)
1983 {
1984 uint64_t allIntStatusValue = 0ULL;
1985 uint32_t normalIntStatusValue = base->NIS;
1986 uint32_t errorIntStatusValue = base->EIS;
1987 uint32_t fifoCadIntStatusValue = base->FIFOIS;
1988
1989 allIntStatusValue |= ((uint64_t)SINC_FIND_STATUS_FIELD_VALUE(normalIntStatusValue, SINC_NORMAL_INT_NAME_COCIE) |
1990 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(normalIntStatusValue, SINC_NORMAL_INT_NAME_CHFIE) |
1991 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(normalIntStatusValue, SINC_NORMAL_INT_NAME_ZCDIE));
1992
1993 allIntStatusValue |= (((uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_SCDIE) |
1994 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_WLMTIE) |
1995 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_LLMTIE) |
1996 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(errorIntStatusValue, SINC_ERROR_INT_NAME_HLMTIE))
1997 << 20ULL);
1998
1999 allIntStatusValue |= (((uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_FUNFIE) |
2000 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_FOVFIE) |
2001 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_CADIE) |
2002 (uint64_t)SINC_FIND_STATUS_FIELD_VALUE(fifoCadIntStatusValue, SINC_FIFO_CAD_INT_SATIE))
2003 << 40ULL);
2004
2005 return (uint64_t)allIntStatusValue;
2006 }
2007
2008 /*!
2009 * @brief Clear selected mask of interrupt status flags.
2010 *
2011 * @param base SINC peripheral base address.
2012 * @param statusMasks The mask of interrupt status flags to clear, should be the OR'ed
2013 * value of @ref sinc_interrupt_status_t.
2014 */
SINC_ClearInterruptStatus(SINC_Type * base,uint64_t statusMasks)2015 static inline void SINC_ClearInterruptStatus(SINC_Type *base, uint64_t statusMasks)
2016 {
2017 uint32_t normalIntMask;
2018 uint32_t errorIntMask;
2019 uint32_t fifoCadIntMask;
2020
2021 /*
2022 * #define SINC_DECODE_INTERRUPT(interruptMask) \
2023 * normalIntMask = ((uint32_t)(interruptMask) & (0xFFFFFUL)); \
2024 * errorIntMask = ((uint32_t)((interruptMask) >> 20ULL) & (0xFFFFFUL)); \
2025 * fifoCadIntMask = ((uint32_t)((interruptMask) >> 40ULL) & (0xFFFFFUL))
2026 */
2027 SINC_DECODE_INTERRUPT(statusMasks);
2028
2029 base->EIS = (SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_SCDIE) |
2030 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_WLMTIE) |
2031 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_LLMTIE) |
2032 SINC_FIND_INT_FIELD_VALUE(errorIntMask, SINC_ERROR_INT_NAME_HLMTIE));
2033
2034 base->FIFOIS = (SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FUNFIE) |
2035 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_FOVFIE) |
2036 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_CADIE) |
2037 SINC_FIND_INT_FIELD_VALUE(fifoCadIntMask, SINC_FIFO_CAD_INT_SATIE));
2038
2039 base->NIS = (SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_COCIE) |
2040 SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_CHFIE) |
2041 SINC_FIND_INT_FIELD_VALUE(normalIntMask, SINC_NORMAL_INT_NAME_ZCDIE));
2042 }
2043
2044 /*! @} */
2045
2046 #if defined(__cplusplus)
2047 extern "C" {
2048 #endif
2049
2050 #if defined(__cplusplus)
2051 }
2052 #endif
2053
2054 /*!
2055 * @}
2056 */
2057 #endif /* FSL_SINC_H__ */
2058
