1 /* 2 ** ################################################################### 3 ** Processors: MKE06Z128VLD4 4 ** MKE06Z128VLH4 5 ** MKE06Z128VLK4 6 ** MKE06Z128VQH4 7 ** MKE06Z64VLD4 8 ** MKE06Z64VLH4 9 ** MKE06Z64VLK4 10 ** MKE06Z64VQH4 11 ** 12 ** Compilers: Keil ARM C/C++ Compiler 13 ** Freescale C/C++ for Embedded ARM 14 ** GNU C Compiler 15 ** IAR ANSI C/C++ Compiler for ARM 16 ** MCUXpresso Compiler 17 ** 18 ** Reference manual: MKE06P80M48SF0RM Rev 4 19 ** Version: rev. 1.0, 2017-05-19 20 ** Build: b180802 21 ** 22 ** Abstract: 23 ** CMSIS Peripheral Access Layer for MKE06Z4 24 ** 25 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 26 ** Copyright 2016-2018 NXP 27 ** 28 ** SPDX-License-Identifier: BSD-3-Clause 29 ** 30 ** http: www.nxp.com 31 ** mail: support@nxp.com 32 ** 33 ** Revisions: 34 ** - rev. 1.0 (2017-05-19) 35 ** Initial version. 36 ** 37 ** ################################################################### 38 */ 39 40 /*! 41 * @file MKE06Z4.h 42 * @version 1.0 43 * @date 2017-05-19 44 * @brief CMSIS Peripheral Access Layer for MKE06Z4 45 * 46 * CMSIS Peripheral Access Layer for MKE06Z4 47 */ 48 49 #ifndef _MKE06Z4_H_ 50 #define _MKE06Z4_H_ /**< Symbol preventing repeated inclusion */ 51 52 /** Memory map major version (memory maps with equal major version number are 53 * compatible) */ 54 #define MCU_MEM_MAP_VERSION 0x0100U 55 /** Memory map minor version */ 56 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 57 58 59 /* ---------------------------------------------------------------------------- 60 -- Interrupt vector numbers 61 ---------------------------------------------------------------------------- */ 62 63 /*! 64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 65 * @{ 66 */ 67 68 /** Interrupt Number Definitions */ 69 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 70 71 typedef enum IRQn { 72 /* Auxiliary constants */ 73 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 74 75 /* Core interrupts */ 76 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 77 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 78 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 79 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 80 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 81 82 /* Device specific interrupts */ 83 Reserved16_IRQn = 0, /**< Reserved interrupt */ 84 Reserved17_IRQn = 1, /**< Reserved interrupt */ 85 Reserved18_IRQn = 2, /**< Reserved interrupt */ 86 Reserved19_IRQn = 3, /**< Reserved interrupt */ 87 Reserved20_IRQn = 4, /**< Reserved interrupt */ 88 FTMRE_IRQn = 5, /**< Command complete */ 89 PMC_IRQn = 6, /**< Low-voltage warning */ 90 IRQ_IRQn = 7, /**< External interrupt */ 91 I2C0_IRQn = 8, /**< Single interrupt vector for all sources */ 92 I2C1_IRQn = 9, /**< Single interrupt vector for all sources */ 93 SPI0_IRQn = 10, /**< Single interrupt vector for all sources */ 94 SPI1_IRQn = 11, /**< Single interrupt vector for all sources */ 95 UART0_IRQn = 12, /**< Status and error */ 96 UART1_IRQn = 13, /**< Status and error */ 97 UART2_IRQn = 14, /**< Status and error */ 98 ADC_IRQn = 15, /**< ADC conversion complete interrupt */ 99 ACMP0_IRQn = 16, /**< Analog comparator 0 interrupt */ 100 FTM0_IRQn = 17, /**< FTM0 single interrupt vector for all sources */ 101 FTM1_IRQn = 18, /**< FTM1 single interrupt vector for all sources */ 102 FTM2_IRQn = 19, /**< FTM2 single interrupt vector for all sources */ 103 RTC_IRQn = 20, /**< RTC overflow */ 104 ACMP1_IRQn = 21, /**< Analog comparator 1 interrupt */ 105 PIT_CH0_IRQn = 22, /**< PIT CH0 overflow */ 106 PIT_CH1_IRQn = 23, /**< PIT CH1 overflow */ 107 KBI0_IRQn = 24, /**< Keyboard interrupt0 */ 108 KBI1_IRQn = 25, /**< Keyboard interrupt1 */ 109 Reserved42_IRQn = 26, /**< Reserved interrupt */ 110 ICS_IRQn = 27, /**< Clock loss of lock */ 111 WDOG_IRQn = 28, /**< Watchdog timeout */ 112 PWT_IRQn = 29, /**< Single interrupt vector for all sources */ 113 MSCAN_1_IRQn = 30, /**< MSCAN Rx Interrupt */ 114 MSCAN_2_IRQn = 31 /**< MSCAN Tx, Err and Wake-up interrupt */ 115 } IRQn_Type; 116 117 /*! 118 * @} 119 */ /* end of group Interrupt_vector_numbers */ 120 121 122 /* ---------------------------------------------------------------------------- 123 -- Cortex M0 Core Configuration 124 ---------------------------------------------------------------------------- */ 125 126 /*! 127 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 128 * @{ 129 */ 130 131 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 132 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 133 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 134 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 135 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 136 137 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 138 #include "system_MKE06Z4.h" /* Device specific configuration file */ 139 140 /*! 141 * @} 142 */ /* end of group Cortex_Core_Configuration */ 143 144 145 /* ---------------------------------------------------------------------------- 146 -- Device Peripheral Access Layer 147 ---------------------------------------------------------------------------- */ 148 149 /*! 150 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 151 * @{ 152 */ 153 154 155 /* 156 ** Start of section using anonymous unions 157 */ 158 159 #if defined(__ARMCC_VERSION) 160 #if (__ARMCC_VERSION >= 6010050) 161 #pragma clang diagnostic push 162 #else 163 #pragma push 164 #pragma anon_unions 165 #endif 166 #elif defined(__CWCC__) 167 #pragma push 168 #pragma cpp_extensions on 169 #elif defined(__GNUC__) 170 /* anonymous unions are enabled by default */ 171 #elif defined(__IAR_SYSTEMS_ICC__) 172 #pragma language=extended 173 #else 174 #error Not supported compiler type 175 #endif 176 177 /* ---------------------------------------------------------------------------- 178 -- ACMP Peripheral Access Layer 179 ---------------------------------------------------------------------------- */ 180 181 /*! 182 * @addtogroup ACMP_Peripheral_Access_Layer ACMP Peripheral Access Layer 183 * @{ 184 */ 185 186 /** ACMP - Register Layout Typedef */ 187 typedef struct { 188 __IO uint8_t CS; /**< ACMP Control and Status Register, offset: 0x0 */ 189 __IO uint8_t C0; /**< ACMP Control Register 0, offset: 0x1 */ 190 __IO uint8_t C1; /**< ACMP Control Register 1, offset: 0x2 */ 191 __IO uint8_t C2; /**< ACMP Control Register 2, offset: 0x3 */ 192 } ACMP_Type; 193 194 /* ---------------------------------------------------------------------------- 195 -- ACMP Register Masks 196 ---------------------------------------------------------------------------- */ 197 198 /*! 199 * @addtogroup ACMP_Register_Masks ACMP Register Masks 200 * @{ 201 */ 202 203 /*! @name CS - ACMP Control and Status Register */ 204 /*! @{ */ 205 #define ACMP_CS_ACMOD_MASK (0x3U) 206 #define ACMP_CS_ACMOD_SHIFT (0U) 207 /*! ACMOD - ACMP MOD 208 * 0b00..ACMP interrupt on output falling edge. 209 * 0b01..ACMP interrupt on output rising edge. 210 * 0b10..ACMP interrupt on output falling edge. 211 * 0b11..ACMP interrupt on output falling or rising edge. 212 */ 213 #define ACMP_CS_ACMOD(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACMOD_SHIFT)) & ACMP_CS_ACMOD_MASK) 214 #define ACMP_CS_ACOPE_MASK (0x4U) 215 #define ACMP_CS_ACOPE_SHIFT (2U) 216 /*! ACOPE - ACMP Output Pin Enable 217 * 0b0..ACMP output cannot be placed onto external pin. 218 * 0b1..ACMP output can be placed onto external pin. 219 */ 220 #define ACMP_CS_ACOPE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACOPE_SHIFT)) & ACMP_CS_ACOPE_MASK) 221 #define ACMP_CS_ACO_MASK (0x8U) 222 #define ACMP_CS_ACO_SHIFT (3U) 223 #define ACMP_CS_ACO(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACO_SHIFT)) & ACMP_CS_ACO_MASK) 224 #define ACMP_CS_ACIE_MASK (0x10U) 225 #define ACMP_CS_ACIE_SHIFT (4U) 226 /*! ACIE - ACMP Interrupt Enable 227 * 0b0..Disable the ACMP Interrupt. 228 * 0b1..Enable the ACMP Interrupt. 229 */ 230 #define ACMP_CS_ACIE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACIE_SHIFT)) & ACMP_CS_ACIE_MASK) 231 #define ACMP_CS_ACF_MASK (0x20U) 232 #define ACMP_CS_ACF_SHIFT (5U) 233 #define ACMP_CS_ACF(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACF_SHIFT)) & ACMP_CS_ACF_MASK) 234 #define ACMP_CS_HYST_MASK (0x40U) 235 #define ACMP_CS_HYST_SHIFT (6U) 236 /*! HYST - Analog Comparator Hysterisis Selection 237 * 0b0..20 mV. 238 * 0b1..30 mV. 239 */ 240 #define ACMP_CS_HYST(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_HYST_SHIFT)) & ACMP_CS_HYST_MASK) 241 #define ACMP_CS_ACE_MASK (0x80U) 242 #define ACMP_CS_ACE_SHIFT (7U) 243 /*! ACE - Analog Comparator Enable 244 * 0b0..The ACMP is disabled. 245 * 0b1..The ACMP is enabled. 246 */ 247 #define ACMP_CS_ACE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_CS_ACE_SHIFT)) & ACMP_CS_ACE_MASK) 248 /*! @} */ 249 250 /*! @name C0 - ACMP Control Register 0 */ 251 /*! @{ */ 252 #define ACMP_C0_ACNSEL_MASK (0x3U) 253 #define ACMP_C0_ACNSEL_SHIFT (0U) 254 /*! ACNSEL - ACMP Negative Input Select 255 * 0b00..External reference 0 256 * 0b01..External reference 1 257 * 0b10..External reference 2 258 * 0b11..DAC output 259 */ 260 #define ACMP_C0_ACNSEL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C0_ACNSEL_SHIFT)) & ACMP_C0_ACNSEL_MASK) 261 #define ACMP_C0_ACPSEL_MASK (0x30U) 262 #define ACMP_C0_ACPSEL_SHIFT (4U) 263 /*! ACPSEL - ACMP Positive Input Select 264 * 0b00..External reference 0 265 * 0b01..External reference 1 266 * 0b10..External reference 2 267 * 0b11..DAC output 268 */ 269 #define ACMP_C0_ACPSEL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C0_ACPSEL_SHIFT)) & ACMP_C0_ACPSEL_MASK) 270 /*! @} */ 271 272 /*! @name C1 - ACMP Control Register 1 */ 273 /*! @{ */ 274 #define ACMP_C1_DACVAL_MASK (0x3FU) 275 #define ACMP_C1_DACVAL_SHIFT (0U) 276 #define ACMP_C1_DACVAL(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACVAL_SHIFT)) & ACMP_C1_DACVAL_MASK) 277 #define ACMP_C1_DACREF_MASK (0x40U) 278 #define ACMP_C1_DACREF_SHIFT (6U) 279 /*! DACREF - DAC Reference Select 280 * 0b0..The DAC selects Bandgap as the reference. 281 * 0b1..The DAC selects VDDA as the reference. 282 */ 283 #define ACMP_C1_DACREF(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACREF_SHIFT)) & ACMP_C1_DACREF_MASK) 284 #define ACMP_C1_DACEN_MASK (0x80U) 285 #define ACMP_C1_DACEN_SHIFT (7U) 286 /*! DACEN - DAC Enable 287 * 0b0..The DAC is disabled. 288 * 0b1..The DAC is enabled. 289 */ 290 #define ACMP_C1_DACEN(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C1_DACEN_SHIFT)) & ACMP_C1_DACEN_MASK) 291 /*! @} */ 292 293 /*! @name C2 - ACMP Control Register 2 */ 294 /*! @{ */ 295 #define ACMP_C2_ACIPE_MASK (0x7U) 296 #define ACMP_C2_ACIPE_SHIFT (0U) 297 /*! ACIPE - ACMP Input Pin Enable 298 * 0b000..The corresponding external analog input is not allowed. 299 * 0b001..The corresponding external analog input is allowed. 300 */ 301 #define ACMP_C2_ACIPE(x) (((uint8_t)(((uint8_t)(x)) << ACMP_C2_ACIPE_SHIFT)) & ACMP_C2_ACIPE_MASK) 302 /*! @} */ 303 304 305 /*! 306 * @} 307 */ /* end of group ACMP_Register_Masks */ 308 309 310 /* ACMP - Peripheral instance base addresses */ 311 /** Peripheral ACMP0 base address */ 312 #define ACMP0_BASE (0x40073000u) 313 /** Peripheral ACMP0 base pointer */ 314 #define ACMP0 ((ACMP_Type *)ACMP0_BASE) 315 /** Peripheral ACMP1 base address */ 316 #define ACMP1_BASE (0x40074000u) 317 /** Peripheral ACMP1 base pointer */ 318 #define ACMP1 ((ACMP_Type *)ACMP1_BASE) 319 /** Array initializer of ACMP peripheral base addresses */ 320 #define ACMP_BASE_ADDRS { ACMP0_BASE, ACMP1_BASE } 321 /** Array initializer of ACMP peripheral base pointers */ 322 #define ACMP_BASE_PTRS { ACMP0, ACMP1 } 323 /** Interrupt vectors for the ACMP peripheral type */ 324 #define ACMP_IRQS { ACMP0_IRQn, ACMP1_IRQn } 325 326 /*! 327 * @} 328 */ /* end of group ACMP_Peripheral_Access_Layer */ 329 330 331 /* ---------------------------------------------------------------------------- 332 -- ADC Peripheral Access Layer 333 ---------------------------------------------------------------------------- */ 334 335 /*! 336 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 337 * @{ 338 */ 339 340 /** ADC - Register Layout Typedef */ 341 typedef struct { 342 __IO uint32_t SC1; /**< Status and Control Register 1, offset: 0x0 */ 343 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x4 */ 344 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x8 */ 345 __IO uint32_t SC4; /**< Status and Control Register 4, offset: 0xC */ 346 __I uint32_t R; /**< Conversion Result Register, offset: 0x10 */ 347 __IO uint32_t CV; /**< Compare Value Register, offset: 0x14 */ 348 __IO uint32_t APCTL1; /**< Pin Control 1 Register, offset: 0x18 */ 349 __IO uint32_t SC5; /**< Status and Control Register 5, offset: 0x1C */ 350 } ADC_Type; 351 352 /* ---------------------------------------------------------------------------- 353 -- ADC Register Masks 354 ---------------------------------------------------------------------------- */ 355 356 /*! 357 * @addtogroup ADC_Register_Masks ADC Register Masks 358 * @{ 359 */ 360 361 /*! @name SC1 - Status and Control Register 1 */ 362 /*! @{ */ 363 #define ADC_SC1_ADCH_MASK (0x1FU) 364 #define ADC_SC1_ADCH_SHIFT (0U) 365 /*! ADCH - Input Channel Select 366 * 0b10110..Temperature Sensor 367 * 0b10111..Bandgap 368 * 0b11101..VREFH 369 * 0b11110..VREFL 370 * 0b11111..Module disabled Reset FIFO in FIFO mode. 371 */ 372 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 373 #define ADC_SC1_ADCO_MASK (0x20U) 374 #define ADC_SC1_ADCO_SHIFT (5U) 375 /*! ADCO - Continuous Conversion Enable 376 * 0b0..One conversion following a write to the ADC_SC1 when software triggered operation is selected, or one conversion following assertion of ADHWT when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversion are triggered when ADC_SC2[ADTRG]=0 or both ADC_SC2[ADTRG]=1 and ADC_SC4[HTRGME]=1. 377 * 0b1..Continuous conversions are initiated following a write to ADC_SC1 when software triggered operation is selected. Continuous conversions are initiated by an ADHWT event when hardware triggered operation is selected. When the FIFO function is enabled (AFDEP > 0), a set of conversions are loop triggered. 378 */ 379 #define ADC_SC1_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCO_SHIFT)) & ADC_SC1_ADCO_MASK) 380 #define ADC_SC1_AIEN_MASK (0x40U) 381 #define ADC_SC1_AIEN_SHIFT (6U) 382 /*! AIEN - Interrupt Enable 383 * 0b0..Conversion complete interrupt disabled. 384 * 0b1..Conversion complete interrupt enabled. 385 */ 386 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 387 #define ADC_SC1_COCO_MASK (0x80U) 388 #define ADC_SC1_COCO_SHIFT (7U) 389 /*! COCO - Conversion Complete Flag 390 * 0b0..Conversion not completed. 391 * 0b1..Conversion completed. 392 */ 393 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 394 /*! @} */ 395 396 /*! @name SC2 - Status and Control Register 2 */ 397 /*! @{ */ 398 #define ADC_SC2_REFSEL_MASK (0x3U) 399 #define ADC_SC2_REFSEL_SHIFT (0U) 400 /*! REFSEL - Voltage Reference Selection 401 * 0b00..Default voltage reference pin pair (VREFH/VREFL). 402 * 0b01..Analog supply pin pair (VDDA/VSSA). 403 * 0b10..Reserved. 404 * 0b11..Reserved - Selects default voltage reference (VREFH/VREFL) pin pair. 405 */ 406 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 407 #define ADC_SC2_FFULL_MASK (0x4U) 408 #define ADC_SC2_FFULL_SHIFT (2U) 409 /*! FFULL - Result FIFO full 410 * 0b0..Indicates that ADC result FIFO is not full and next conversion data still can be stored into FIFO. 411 * 0b1..Indicates that ADC result FIFO is full and next conversion will override old data in case of no read action. 412 */ 413 #define ADC_SC2_FFULL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_FFULL_SHIFT)) & ADC_SC2_FFULL_MASK) 414 #define ADC_SC2_FEMPTY_MASK (0x8U) 415 #define ADC_SC2_FEMPTY_SHIFT (3U) 416 /*! FEMPTY - Result FIFO empty 417 * 0b0..Indicates that ADC result FIFO have at least one valid new data. 418 * 0b1..Indicates that ADC result FIFO have no valid new data. 419 */ 420 #define ADC_SC2_FEMPTY(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_FEMPTY_SHIFT)) & ADC_SC2_FEMPTY_MASK) 421 #define ADC_SC2_ACFGT_MASK (0x10U) 422 #define ADC_SC2_ACFGT_SHIFT (4U) 423 /*! ACFGT - Compare Function Greater Than Enable 424 * 0b0..Compare triggers when input is less than compare level. 425 * 0b1..Compare triggers when input is greater than or equal to compare level. 426 */ 427 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 428 #define ADC_SC2_ACFE_MASK (0x20U) 429 #define ADC_SC2_ACFE_SHIFT (5U) 430 /*! ACFE - Compare Function Enable 431 * 0b0..Compare function disabled. 432 * 0b1..Compare function enabled. 433 */ 434 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 435 #define ADC_SC2_ADTRG_MASK (0x40U) 436 #define ADC_SC2_ADTRG_SHIFT (6U) 437 /*! ADTRG - Conversion Trigger Select 438 * 0b0..Software trigger selected. 439 * 0b1..Hardware trigger selected. 440 */ 441 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 442 #define ADC_SC2_ADACT_MASK (0x80U) 443 #define ADC_SC2_ADACT_SHIFT (7U) 444 /*! ADACT - Conversion Active 445 * 0b0..Conversion not in progress. 446 * 0b1..Conversion in progress. 447 */ 448 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 449 /*! @} */ 450 451 /*! @name SC3 - Status and Control Register 3 */ 452 /*! @{ */ 453 #define ADC_SC3_ADICLK_MASK (0x3U) 454 #define ADC_SC3_ADICLK_SHIFT (0U) 455 /*! ADICLK - Input Clock Select 456 * 0b00..Bus clock 457 * 0b01..Bus clock divided by 2 458 * 0b10..Alternate clock (ALTCLK) 459 * 0b11..Asynchronous clock (ADACK) 460 */ 461 #define ADC_SC3_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADICLK_SHIFT)) & ADC_SC3_ADICLK_MASK) 462 #define ADC_SC3_MODE_MASK (0xCU) 463 #define ADC_SC3_MODE_SHIFT (2U) 464 /*! MODE - Conversion Mode Selection 465 * 0b00..8-bit conversion (N = 8) 466 * 0b01..10-bit conversion (N = 10) 467 * 0b10..12-bit conversion (N = 12) 468 * 0b11..Reserved 469 */ 470 #define ADC_SC3_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_MODE_SHIFT)) & ADC_SC3_MODE_MASK) 471 #define ADC_SC3_ADLSMP_MASK (0x10U) 472 #define ADC_SC3_ADLSMP_SHIFT (4U) 473 /*! ADLSMP - Long Sample Time Configuration 474 * 0b0..Short sample time. 475 * 0b1..Long sample time. 476 */ 477 #define ADC_SC3_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADLSMP_SHIFT)) & ADC_SC3_ADLSMP_MASK) 478 #define ADC_SC3_ADIV_MASK (0x60U) 479 #define ADC_SC3_ADIV_SHIFT (5U) 480 /*! ADIV - Clock Divide Select 481 * 0b00..Divide ration = 1, and clock rate = Input clock. 482 * 0b01..Divide ration = 2, and clock rate = Input clock * 2. 483 * 0b10..Divide ration = 3, and clock rate = Input clock * 4. 484 * 0b11..Divide ration = 4, and clock rate = Input clock * 8. 485 */ 486 #define ADC_SC3_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADIV_SHIFT)) & ADC_SC3_ADIV_MASK) 487 #define ADC_SC3_ADLPC_MASK (0x80U) 488 #define ADC_SC3_ADLPC_SHIFT (7U) 489 /*! ADLPC - Low-Power Configuration 490 * 0b0..High speed configuration. 491 * 0b1..Low power configuration:The power is reduced at the expense of maximum clock speed. 492 */ 493 #define ADC_SC3_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADLPC_SHIFT)) & ADC_SC3_ADLPC_MASK) 494 /*! @} */ 495 496 /*! @name SC4 - Status and Control Register 4 */ 497 /*! @{ */ 498 #define ADC_SC4_AFDEP_MASK (0x7U) 499 #define ADC_SC4_AFDEP_SHIFT (0U) 500 /*! AFDEP - FIFO Depth 501 * 0b000..FIFO is disabled. 502 * 0b001..2-level FIFO is enabled. 503 * 0b010..3-level FIFO is enabled.. 504 * 0b011..4-level FIFO is enabled. 505 * 0b100..5-level FIFO is enabled. 506 * 0b101..6-level FIFO is enabled. 507 * 0b110..7-level FIFO is enabled. 508 * 0b111..8-level FIFO is enabled. 509 */ 510 #define ADC_SC4_AFDEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_AFDEP_SHIFT)) & ADC_SC4_AFDEP_MASK) 511 #define ADC_SC4_ACFSEL_MASK (0x20U) 512 #define ADC_SC4_ACFSEL_SHIFT (5U) 513 /*! ACFSEL - Compare Function Selection 514 * 0b0..OR all of compare trigger. 515 * 0b1..AND all of compare trigger. 516 */ 517 #define ADC_SC4_ACFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_ACFSEL_SHIFT)) & ADC_SC4_ACFSEL_MASK) 518 #define ADC_SC4_ASCANE_MASK (0x40U) 519 #define ADC_SC4_ASCANE_SHIFT (6U) 520 /*! ASCANE - FIFO Scan Mode Enable 521 * 0b0..FIFO scan mode disabled. 522 * 0b1..FIFO scan mode enabled. 523 */ 524 #define ADC_SC4_ASCANE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_ASCANE_SHIFT)) & ADC_SC4_ASCANE_MASK) 525 #define ADC_SC4_HTRGME_MASK (0x100U) 526 #define ADC_SC4_HTRGME_SHIFT (8U) 527 /*! HTRGME - Hardware Trigger Multiple Conversion Enable 528 * 0b0..One hardware trigger pulse triggers one conversion. 529 * 0b1..One hardware trigger pulse triggers multiple conversions in fifo mode. 530 */ 531 #define ADC_SC4_HTRGME(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC4_HTRGME_SHIFT)) & ADC_SC4_HTRGME_MASK) 532 /*! @} */ 533 534 /*! @name R - Conversion Result Register */ 535 /*! @{ */ 536 #define ADC_R_ADR_MASK (0xFFFU) 537 #define ADC_R_ADR_SHIFT (0U) 538 #define ADC_R_ADR(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_ADR_SHIFT)) & ADC_R_ADR_MASK) 539 /*! @} */ 540 541 /*! @name CV - Compare Value Register */ 542 /*! @{ */ 543 #define ADC_CV_CV_MASK (0xFFFU) 544 #define ADC_CV_CV_SHIFT (0U) 545 #define ADC_CV_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV_SHIFT)) & ADC_CV_CV_MASK) 546 /*! @} */ 547 548 /*! @name APCTL1 - Pin Control 1 Register */ 549 /*! @{ */ 550 #define ADC_APCTL1_ADPC_MASK (0xFFFFU) 551 #define ADC_APCTL1_ADPC_SHIFT (0U) 552 /*! ADPC - ADC Pin Control 553 * 0b0000000000000000..ADx pin I/O control enabled. 554 * 0b0000000000000001..ADx pin I/O control disabled. 555 */ 556 #define ADC_APCTL1_ADPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_APCTL1_ADPC_SHIFT)) & ADC_APCTL1_ADPC_MASK) 557 /*! @} */ 558 559 /*! @name SC5 - Status and Control Register 5 */ 560 /*! @{ */ 561 #define ADC_SC5_HTRGMASKSEL_MASK (0x1U) 562 #define ADC_SC5_HTRGMASKSEL_SHIFT (0U) 563 /*! HTRGMASKSEL - Hardware Trigger Mask Mode Select 564 * 0b0..Hardware trigger mask with HTRGMASKE. 565 * 0b1..Hardware trigger mask automatically when data fifo is not empty. 566 */ 567 #define ADC_SC5_HTRGMASKSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC5_HTRGMASKSEL_SHIFT)) & ADC_SC5_HTRGMASKSEL_MASK) 568 #define ADC_SC5_HTRGMASKE_MASK (0x2U) 569 #define ADC_SC5_HTRGMASKE_SHIFT (1U) 570 /*! HTRGMASKE - Hardware Trigger Mask Enable 571 * 0b0..Hardware trigger mask disable. 572 * 0b1..Hardware trigger mask enable and hardware trigger cannot trigger ADC conversion.. 573 */ 574 #define ADC_SC5_HTRGMASKE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC5_HTRGMASKE_SHIFT)) & ADC_SC5_HTRGMASKE_MASK) 575 /*! @} */ 576 577 578 /*! 579 * @} 580 */ /* end of group ADC_Register_Masks */ 581 582 583 /* ADC - Peripheral instance base addresses */ 584 /** Peripheral ADC base address */ 585 #define ADC_BASE (0x4003B000u) 586 /** Peripheral ADC base pointer */ 587 #define ADC ((ADC_Type *)ADC_BASE) 588 /** Array initializer of ADC peripheral base addresses */ 589 #define ADC_BASE_ADDRS { ADC_BASE } 590 /** Array initializer of ADC peripheral base pointers */ 591 #define ADC_BASE_PTRS { ADC } 592 /** Interrupt vectors for the ADC peripheral type */ 593 #define ADC_IRQS { ADC_IRQn } 594 595 /*! 596 * @} 597 */ /* end of group ADC_Peripheral_Access_Layer */ 598 599 600 /* ---------------------------------------------------------------------------- 601 -- CRC Peripheral Access Layer 602 ---------------------------------------------------------------------------- */ 603 604 /*! 605 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 606 * @{ 607 */ 608 609 /** CRC - Register Layout Typedef */ 610 typedef struct { 611 union { /* offset: 0x0 */ 612 struct { /* offset: 0x0 */ 613 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 614 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 615 } ACCESS16BIT; 616 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 617 struct { /* offset: 0x0 */ 618 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 619 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 620 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 621 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 622 } ACCESS8BIT; 623 }; 624 union { /* offset: 0x4 */ 625 struct { /* offset: 0x4 */ 626 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 627 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 628 } GPOLY_ACCESS16BIT; 629 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 630 struct { /* offset: 0x4 */ 631 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 632 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 633 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 634 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 635 } GPOLY_ACCESS8BIT; 636 }; 637 union { /* offset: 0x8 */ 638 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 639 struct { /* offset: 0x8 */ 640 uint8_t RESERVED_0[3]; 641 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 642 } CTRL_ACCESS8BIT; 643 }; 644 } CRC_Type; 645 646 /* ---------------------------------------------------------------------------- 647 -- CRC Register Masks 648 ---------------------------------------------------------------------------- */ 649 650 /*! 651 * @addtogroup CRC_Register_Masks CRC Register Masks 652 * @{ 653 */ 654 655 /*! @name DATAL - CRC_DATAL register. */ 656 /*! @{ */ 657 #define CRC_DATAL_DATAL_MASK (0xFFFFU) 658 #define CRC_DATAL_DATAL_SHIFT (0U) 659 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) 660 /*! @} */ 661 662 /*! @name DATAH - CRC_DATAH register. */ 663 /*! @{ */ 664 #define CRC_DATAH_DATAH_MASK (0xFFFFU) 665 #define CRC_DATAH_DATAH_SHIFT (0U) 666 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) 667 /*! @} */ 668 669 /*! @name DATA - CRC Data register */ 670 /*! @{ */ 671 #define CRC_DATA_LL_MASK (0xFFU) 672 #define CRC_DATA_LL_SHIFT (0U) 673 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 674 #define CRC_DATA_LU_MASK (0xFF00U) 675 #define CRC_DATA_LU_SHIFT (8U) 676 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 677 #define CRC_DATA_HL_MASK (0xFF0000U) 678 #define CRC_DATA_HL_SHIFT (16U) 679 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 680 #define CRC_DATA_HU_MASK (0xFF000000U) 681 #define CRC_DATA_HU_SHIFT (24U) 682 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 683 /*! @} */ 684 685 /*! @name DATALL - CRC_DATALL register. */ 686 /*! @{ */ 687 #define CRC_DATALL_DATALL_MASK (0xFFU) 688 #define CRC_DATALL_DATALL_SHIFT (0U) 689 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) 690 /*! @} */ 691 692 /*! @name DATALU - CRC_DATALU register. */ 693 /*! @{ */ 694 #define CRC_DATALU_DATALU_MASK (0xFFU) 695 #define CRC_DATALU_DATALU_SHIFT (0U) 696 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) 697 /*! @} */ 698 699 /*! @name DATAHL - CRC_DATAHL register. */ 700 /*! @{ */ 701 #define CRC_DATAHL_DATAHL_MASK (0xFFU) 702 #define CRC_DATAHL_DATAHL_SHIFT (0U) 703 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) 704 /*! @} */ 705 706 /*! @name DATAHU - CRC_DATAHU register. */ 707 /*! @{ */ 708 #define CRC_DATAHU_DATAHU_MASK (0xFFU) 709 #define CRC_DATAHU_DATAHU_SHIFT (0U) 710 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) 711 /*! @} */ 712 713 /*! @name GPOLYL - CRC_GPOLYL register. */ 714 /*! @{ */ 715 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 716 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 717 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 718 /*! @} */ 719 720 /*! @name GPOLYH - CRC_GPOLYH register. */ 721 /*! @{ */ 722 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 723 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 724 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 725 /*! @} */ 726 727 /*! @name GPOLY - CRC Polynomial register */ 728 /*! @{ */ 729 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 730 #define CRC_GPOLY_LOW_SHIFT (0U) 731 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 732 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 733 #define CRC_GPOLY_HIGH_SHIFT (16U) 734 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 735 /*! @} */ 736 737 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 738 /*! @{ */ 739 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 740 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 741 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 742 /*! @} */ 743 744 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 745 /*! @{ */ 746 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 747 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 748 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 749 /*! @} */ 750 751 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 752 /*! @{ */ 753 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 754 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 755 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 756 /*! @} */ 757 758 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 759 /*! @{ */ 760 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 761 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 762 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 763 /*! @} */ 764 765 /*! @name CTRL - CRC Control register */ 766 /*! @{ */ 767 #define CRC_CTRL_TCRC_MASK (0x1000000U) 768 #define CRC_CTRL_TCRC_SHIFT (24U) 769 /*! TCRC 770 * 0b0..16-bit CRC protocol. 771 * 0b1..32-bit CRC protocol. 772 */ 773 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 774 #define CRC_CTRL_WAS_MASK (0x2000000U) 775 #define CRC_CTRL_WAS_SHIFT (25U) 776 /*! WAS - Write CRC Data Register As Seed 777 * 0b0..Writes to the CRC data register are data values. 778 * 0b1..Writes to the CRC data register are seed values. 779 */ 780 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 781 #define CRC_CTRL_FXOR_MASK (0x4000000U) 782 #define CRC_CTRL_FXOR_SHIFT (26U) 783 /*! FXOR - Complement Read Of CRC Data Register 784 * 0b0..No XOR on reading. 785 * 0b1..Invert or complement the read value of the CRC Data register. 786 */ 787 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 788 #define CRC_CTRL_TOTR_MASK (0x30000000U) 789 #define CRC_CTRL_TOTR_SHIFT (28U) 790 /*! TOTR - Type Of Transpose For Read 791 * 0b00..No transposition. 792 * 0b01..Bits in bytes are transposed; bytes are not transposed. 793 * 0b10..Both bits in bytes and bytes are transposed. 794 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 795 */ 796 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 797 #define CRC_CTRL_TOT_MASK (0xC0000000U) 798 #define CRC_CTRL_TOT_SHIFT (30U) 799 /*! TOT - Type Of Transpose For Writes 800 * 0b00..No transposition. 801 * 0b01..Bits in bytes are transposed; bytes are not transposed. 802 * 0b10..Both bits in bytes and bytes are transposed. 803 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 804 */ 805 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 806 /*! @} */ 807 808 /*! @name CTRLHU - CRC_CTRLHU register. */ 809 /*! @{ */ 810 #define CRC_CTRLHU_TCRC_MASK (0x1U) 811 #define CRC_CTRLHU_TCRC_SHIFT (0U) 812 /*! TCRC 813 * 0b0..16-bit CRC protocol. 814 * 0b1..32-bit CRC protocol. 815 */ 816 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 817 #define CRC_CTRLHU_WAS_MASK (0x2U) 818 #define CRC_CTRLHU_WAS_SHIFT (1U) 819 /*! WAS 820 * 0b0..Writes to CRC data register are data values. 821 * 0b1..Writes to CRC data reguster are seed values. 822 */ 823 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 824 #define CRC_CTRLHU_FXOR_MASK (0x4U) 825 #define CRC_CTRLHU_FXOR_SHIFT (2U) 826 /*! FXOR 827 * 0b0..No XOR on reading. 828 * 0b1..Invert or complement the read value of CRC data register. 829 */ 830 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 831 #define CRC_CTRLHU_TOTR_MASK (0x30U) 832 #define CRC_CTRLHU_TOTR_SHIFT (4U) 833 /*! TOTR 834 * 0b00..No Transposition. 835 * 0b01..Bits in bytes are transposed, bytes are not transposed. 836 * 0b10..Both bits in bytes and bytes are transposed. 837 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 838 */ 839 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 840 #define CRC_CTRLHU_TOT_MASK (0xC0U) 841 #define CRC_CTRLHU_TOT_SHIFT (6U) 842 /*! TOT 843 * 0b00..No Transposition. 844 * 0b01..Bits in bytes are transposed, bytes are not transposed. 845 * 0b10..Both bits in bytes and bytes are transposed. 846 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 847 */ 848 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 849 /*! @} */ 850 851 852 /*! 853 * @} 854 */ /* end of group CRC_Register_Masks */ 855 856 857 /* CRC - Peripheral instance base addresses */ 858 /** Peripheral CRC base address */ 859 #define CRC_BASE (0x40032000u) 860 /** Peripheral CRC base pointer */ 861 #define CRC0 ((CRC_Type *)CRC_BASE) 862 /** Array initializer of CRC peripheral base addresses */ 863 #define CRC_BASE_ADDRS { CRC_BASE } 864 /** Array initializer of CRC peripheral base pointers */ 865 #define CRC_BASE_PTRS { CRC0 } 866 867 /*! 868 * @} 869 */ /* end of group CRC_Peripheral_Access_Layer */ 870 871 872 /* ---------------------------------------------------------------------------- 873 -- FGPIO Peripheral Access Layer 874 ---------------------------------------------------------------------------- */ 875 876 /*! 877 * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer 878 * @{ 879 */ 880 881 /** FGPIO - Register Layout Typedef */ 882 typedef struct { 883 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 884 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 885 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 886 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 887 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 888 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 889 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 890 } FGPIO_Type; 891 892 /* ---------------------------------------------------------------------------- 893 -- FGPIO Register Masks 894 ---------------------------------------------------------------------------- */ 895 896 /*! 897 * @addtogroup FGPIO_Register_Masks FGPIO Register Masks 898 * @{ 899 */ 900 901 /*! @name PDOR - Port Data Output Register */ 902 /*! @{ */ 903 #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 904 #define FGPIO_PDOR_PDO_SHIFT (0U) 905 /*! PDO - Port Data Output 906 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 907 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 908 */ 909 #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) 910 /*! @} */ 911 912 /*! @name PSOR - Port Set Output Register */ 913 /*! @{ */ 914 #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 915 #define FGPIO_PSOR_PTSO_SHIFT (0U) 916 /*! PTSO - Port Set Output 917 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 918 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 919 */ 920 #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) 921 /*! @} */ 922 923 /*! @name PCOR - Port Clear Output Register */ 924 /*! @{ */ 925 #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 926 #define FGPIO_PCOR_PTCO_SHIFT (0U) 927 /*! PTCO - Port Clear Output 928 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 929 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 930 */ 931 #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) 932 /*! @} */ 933 934 /*! @name PTOR - Port Toggle Output Register */ 935 /*! @{ */ 936 #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 937 #define FGPIO_PTOR_PTTO_SHIFT (0U) 938 /*! PTTO - Port Toggle Output 939 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 940 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 941 */ 942 #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) 943 /*! @} */ 944 945 /*! @name PDIR - Port Data Input Register */ 946 /*! @{ */ 947 #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 948 #define FGPIO_PDIR_PDI_SHIFT (0U) 949 /*! PDI - Port Data Input 950 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 951 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 952 */ 953 #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) 954 /*! @} */ 955 956 /*! @name PDDR - Port Data Direction Register */ 957 /*! @{ */ 958 #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 959 #define FGPIO_PDDR_PDD_SHIFT (0U) 960 /*! PDD - Port Data Direction 961 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in FPIOx_PIDR register. 962 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 963 */ 964 #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) 965 /*! @} */ 966 967 /*! @name PIDR - Port Input Disable Register */ 968 /*! @{ */ 969 #define FGPIO_PIDR_PID_MASK (0xFFFFFFFFU) 970 #define FGPIO_PIDR_PID_SHIFT (0U) 971 /*! PID - Port Input Disable 972 * 0b00000000000000000000000000000000..Pin is configured for General Purpose Input, provided the pin is configured for any digital function. 973 * 0b00000000000000000000000000000001..Pin is not configured as General Purpose Input. Corresponding Port Data Input Register bit will read zero. 974 */ 975 #define FGPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PIDR_PID_SHIFT)) & FGPIO_PIDR_PID_MASK) 976 /*! @} */ 977 978 979 /*! 980 * @} 981 */ /* end of group FGPIO_Register_Masks */ 982 983 984 /* FGPIO - Peripheral instance base addresses */ 985 /** Peripheral FGPIOA base address */ 986 #define FGPIOA_BASE (0xF8000000u) 987 /** Peripheral FGPIOA base pointer */ 988 #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) 989 /** Peripheral FGPIOB base address */ 990 #define FGPIOB_BASE (0xF8000040u) 991 /** Peripheral FGPIOB base pointer */ 992 #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) 993 /** Peripheral FGPIOC base address */ 994 #define FGPIOC_BASE (0xF8000080u) 995 /** Peripheral FGPIOC base pointer */ 996 #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) 997 /** Array initializer of FGPIO peripheral base addresses */ 998 #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE } 999 /** Array initializer of FGPIO peripheral base pointers */ 1000 #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC } 1001 1002 /*! 1003 * @} 1004 */ /* end of group FGPIO_Peripheral_Access_Layer */ 1005 1006 1007 /* ---------------------------------------------------------------------------- 1008 -- FTM Peripheral Access Layer 1009 ---------------------------------------------------------------------------- */ 1010 1011 /*! 1012 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer 1013 * @{ 1014 */ 1015 1016 /** FTM - Register Layout Typedef */ 1017 typedef struct { 1018 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */ 1019 __IO uint32_t CNT; /**< Counter, offset: 0x4 */ 1020 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ 1021 struct { /* offset: 0xC, array step: 0x8 */ 1022 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */ 1023 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ 1024 } CONTROLS[8]; 1025 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */ 1026 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */ 1027 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */ 1028 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */ 1029 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */ 1030 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */ 1031 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */ 1032 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */ 1033 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */ 1034 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */ 1035 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */ 1036 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */ 1037 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */ 1038 uint8_t RESERVED_0[4]; 1039 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ 1040 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */ 1041 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */ 1042 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */ 1043 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */ 1044 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */ 1045 } FTM_Type; 1046 1047 /* ---------------------------------------------------------------------------- 1048 -- FTM Register Masks 1049 ---------------------------------------------------------------------------- */ 1050 1051 /*! 1052 * @addtogroup FTM_Register_Masks FTM Register Masks 1053 * @{ 1054 */ 1055 1056 /*! @name SC - Status And Control */ 1057 /*! @{ */ 1058 #define FTM_SC_PS_MASK (0x7U) 1059 #define FTM_SC_PS_SHIFT (0U) 1060 /*! PS - Prescale Factor Selection 1061 * 0b000..Divide by 1 1062 * 0b001..Divide by 2 1063 * 0b010..Divide by 4 1064 * 0b011..Divide by 8 1065 * 0b100..Divide by 16 1066 * 0b101..Divide by 32 1067 * 0b110..Divide by 64 1068 * 0b111..Divide by 128 1069 */ 1070 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK) 1071 #define FTM_SC_CLKS_MASK (0x18U) 1072 #define FTM_SC_CLKS_SHIFT (3U) 1073 /*! CLKS - Clock Source Selection 1074 * 0b00..No clock selected. This in effect disables the FTM counter. 1075 * 0b01..System clock 1076 * 0b10..Fixed frequency clock 1077 * 0b11..External clock 1078 */ 1079 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK) 1080 #define FTM_SC_CPWMS_MASK (0x20U) 1081 #define FTM_SC_CPWMS_SHIFT (5U) 1082 /*! CPWMS - Center-Aligned PWM Select 1083 * 0b0..FTM counter operates in Up Counting mode. 1084 * 0b1..FTM counter operates in Up-Down Counting mode. 1085 */ 1086 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK) 1087 #define FTM_SC_TOIE_MASK (0x40U) 1088 #define FTM_SC_TOIE_SHIFT (6U) 1089 /*! TOIE - Timer Overflow Interrupt Enable 1090 * 0b0..Disable TOF interrupts. Use software polling. 1091 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one. 1092 */ 1093 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK) 1094 #define FTM_SC_TOF_MASK (0x80U) 1095 #define FTM_SC_TOF_SHIFT (7U) 1096 /*! TOF - Timer Overflow Flag 1097 * 0b0..FTM counter has not overflowed. 1098 * 0b1..FTM counter has overflowed. 1099 */ 1100 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK) 1101 /*! @} */ 1102 1103 /*! @name CNT - Counter */ 1104 /*! @{ */ 1105 #define FTM_CNT_COUNT_MASK (0xFFFFU) 1106 #define FTM_CNT_COUNT_SHIFT (0U) 1107 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK) 1108 /*! @} */ 1109 1110 /*! @name MOD - Modulo */ 1111 /*! @{ */ 1112 #define FTM_MOD_MOD_MASK (0xFFFFU) 1113 #define FTM_MOD_MOD_SHIFT (0U) 1114 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK) 1115 /*! @} */ 1116 1117 /*! @name CnSC - Channel (n) Status And Control */ 1118 /*! @{ */ 1119 #define FTM_CnSC_ELSA_MASK (0x4U) 1120 #define FTM_CnSC_ELSA_SHIFT (2U) 1121 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK) 1122 #define FTM_CnSC_ELSB_MASK (0x8U) 1123 #define FTM_CnSC_ELSB_SHIFT (3U) 1124 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK) 1125 #define FTM_CnSC_MSA_MASK (0x10U) 1126 #define FTM_CnSC_MSA_SHIFT (4U) 1127 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK) 1128 #define FTM_CnSC_MSB_MASK (0x20U) 1129 #define FTM_CnSC_MSB_SHIFT (5U) 1130 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK) 1131 #define FTM_CnSC_CHIE_MASK (0x40U) 1132 #define FTM_CnSC_CHIE_SHIFT (6U) 1133 /*! CHIE - Channel Interrupt Enable 1134 * 0b0..Disable channel interrupts. Use software polling. 1135 * 0b1..Enable channel interrupts. 1136 */ 1137 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK) 1138 #define FTM_CnSC_CHF_MASK (0x80U) 1139 #define FTM_CnSC_CHF_SHIFT (7U) 1140 /*! CHF - Channel Flag 1141 * 0b0..No channel event has occurred. 1142 * 0b1..A channel event has occurred. 1143 */ 1144 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK) 1145 /*! @} */ 1146 1147 /* The count of FTM_CnSC */ 1148 #define FTM_CnSC_COUNT (8U) 1149 1150 /*! @name CnV - Channel (n) Value */ 1151 /*! @{ */ 1152 #define FTM_CnV_VAL_MASK (0xFFFFU) 1153 #define FTM_CnV_VAL_SHIFT (0U) 1154 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK) 1155 /*! @} */ 1156 1157 /* The count of FTM_CnV */ 1158 #define FTM_CnV_COUNT (8U) 1159 1160 /*! @name CNTIN - Counter Initial Value */ 1161 /*! @{ */ 1162 #define FTM_CNTIN_INIT_MASK (0xFFFFU) 1163 #define FTM_CNTIN_INIT_SHIFT (0U) 1164 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK) 1165 /*! @} */ 1166 1167 /*! @name STATUS - Capture And Compare Status */ 1168 /*! @{ */ 1169 #define FTM_STATUS_CH0F_MASK (0x1U) 1170 #define FTM_STATUS_CH0F_SHIFT (0U) 1171 /*! CH0F - Channel 0 Flag 1172 * 0b0..No channel event has occurred. 1173 * 0b1..A channel event has occurred. 1174 */ 1175 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK) 1176 #define FTM_STATUS_CH1F_MASK (0x2U) 1177 #define FTM_STATUS_CH1F_SHIFT (1U) 1178 /*! CH1F - Channel 1 Flag 1179 * 0b0..No channel event has occurred. 1180 * 0b1..A channel event has occurred. 1181 */ 1182 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK) 1183 #define FTM_STATUS_CH2F_MASK (0x4U) 1184 #define FTM_STATUS_CH2F_SHIFT (2U) 1185 /*! CH2F - Channel 2 Flag 1186 * 0b0..No channel event has occurred. 1187 * 0b1..A channel event has occurred. 1188 */ 1189 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK) 1190 #define FTM_STATUS_CH3F_MASK (0x8U) 1191 #define FTM_STATUS_CH3F_SHIFT (3U) 1192 /*! CH3F - Channel 3 Flag 1193 * 0b0..No channel event has occurred. 1194 * 0b1..A channel event has occurred. 1195 */ 1196 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK) 1197 #define FTM_STATUS_CH4F_MASK (0x10U) 1198 #define FTM_STATUS_CH4F_SHIFT (4U) 1199 /*! CH4F - Channel 4 Flag 1200 * 0b0..No channel event has occurred. 1201 * 0b1..A channel event has occurred. 1202 */ 1203 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK) 1204 #define FTM_STATUS_CH5F_MASK (0x20U) 1205 #define FTM_STATUS_CH5F_SHIFT (5U) 1206 /*! CH5F - Channel 5 Flag 1207 * 0b0..No channel event has occurred. 1208 * 0b1..A channel event has occurred. 1209 */ 1210 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK) 1211 #define FTM_STATUS_CH6F_MASK (0x40U) 1212 #define FTM_STATUS_CH6F_SHIFT (6U) 1213 /*! CH6F - Channel 6 Flag 1214 * 0b0..No channel event has occurred. 1215 * 0b1..A channel event has occurred. 1216 */ 1217 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK) 1218 #define FTM_STATUS_CH7F_MASK (0x80U) 1219 #define FTM_STATUS_CH7F_SHIFT (7U) 1220 /*! CH7F - Channel 7 Flag 1221 * 0b0..No channel event has occurred. 1222 * 0b1..A channel event has occurred. 1223 */ 1224 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK) 1225 /*! @} */ 1226 1227 /*! @name MODE - Features Mode Selection */ 1228 /*! @{ */ 1229 #define FTM_MODE_FTMEN_MASK (0x1U) 1230 #define FTM_MODE_FTMEN_SHIFT (0U) 1231 /*! FTMEN - FTM Enable 1232 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM. 1233 * 0b1..Free running counter and synchronization are different from TPM behavior. 1234 */ 1235 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK) 1236 #define FTM_MODE_INIT_MASK (0x2U) 1237 #define FTM_MODE_INIT_SHIFT (1U) 1238 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK) 1239 #define FTM_MODE_WPDIS_MASK (0x4U) 1240 #define FTM_MODE_WPDIS_SHIFT (2U) 1241 /*! WPDIS - Write Protection Disable 1242 * 0b0..Write protection is enabled. 1243 * 0b1..Write protection is disabled. 1244 */ 1245 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK) 1246 #define FTM_MODE_PWMSYNC_MASK (0x8U) 1247 #define FTM_MODE_PWMSYNC_SHIFT (3U) 1248 /*! PWMSYNC - PWM Synchronization Mode 1249 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. 1250 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. 1251 */ 1252 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK) 1253 #define FTM_MODE_CAPTEST_MASK (0x10U) 1254 #define FTM_MODE_CAPTEST_SHIFT (4U) 1255 /*! CAPTEST - Capture Test Mode Enable 1256 * 0b0..Capture test mode is disabled. 1257 * 0b1..Capture test mode is enabled. 1258 */ 1259 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK) 1260 #define FTM_MODE_FAULTM_MASK (0x60U) 1261 #define FTM_MODE_FAULTM_SHIFT (5U) 1262 /*! FAULTM - Fault Control Mode 1263 * 0b00..Fault control is disabled for all channels. 1264 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. 1265 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing. 1266 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. 1267 */ 1268 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK) 1269 #define FTM_MODE_FAULTIE_MASK (0x80U) 1270 #define FTM_MODE_FAULTIE_SHIFT (7U) 1271 /*! FAULTIE - Fault Interrupt Enable 1272 * 0b0..Fault control interrupt is disabled. 1273 * 0b1..Fault control interrupt is enabled. 1274 */ 1275 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK) 1276 /*! @} */ 1277 1278 /*! @name SYNC - Synchronization */ 1279 /*! @{ */ 1280 #define FTM_SYNC_CNTMIN_MASK (0x1U) 1281 #define FTM_SYNC_CNTMIN_SHIFT (0U) 1282 /*! CNTMIN - Minimum Loading Point Enable 1283 * 0b0..The minimum loading point is disabled. 1284 * 0b1..The minimum loading point is enabled. 1285 */ 1286 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK) 1287 #define FTM_SYNC_CNTMAX_MASK (0x2U) 1288 #define FTM_SYNC_CNTMAX_SHIFT (1U) 1289 /*! CNTMAX - Maximum Loading Point Enable 1290 * 0b0..The maximum loading point is disabled. 1291 * 0b1..The maximum loading point is enabled. 1292 */ 1293 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK) 1294 #define FTM_SYNC_REINIT_MASK (0x4U) 1295 #define FTM_SYNC_REINIT_SHIFT (2U) 1296 /*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization) 1297 * 0b0..FTM counter continues to count normally. 1298 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected. 1299 */ 1300 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK) 1301 #define FTM_SYNC_SYNCHOM_MASK (0x8U) 1302 #define FTM_SYNC_SYNCHOM_SHIFT (3U) 1303 /*! SYNCHOM - Output Mask Synchronization 1304 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. 1305 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization. 1306 */ 1307 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK) 1308 #define FTM_SYNC_TRIG0_MASK (0x10U) 1309 #define FTM_SYNC_TRIG0_SHIFT (4U) 1310 /*! TRIG0 - PWM Synchronization Hardware Trigger 0 1311 * 0b0..Trigger is disabled. 1312 * 0b1..Trigger is enabled. 1313 */ 1314 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK) 1315 #define FTM_SYNC_TRIG1_MASK (0x20U) 1316 #define FTM_SYNC_TRIG1_SHIFT (5U) 1317 /*! TRIG1 - PWM Synchronization Hardware Trigger 1 1318 * 0b0..Trigger is disabled. 1319 * 0b1..Trigger is enabled. 1320 */ 1321 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK) 1322 #define FTM_SYNC_TRIG2_MASK (0x40U) 1323 #define FTM_SYNC_TRIG2_SHIFT (6U) 1324 /*! TRIG2 - PWM Synchronization Hardware Trigger 2 1325 * 0b0..Trigger is disabled. 1326 * 0b1..Trigger is enabled. 1327 */ 1328 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK) 1329 #define FTM_SYNC_SWSYNC_MASK (0x80U) 1330 #define FTM_SYNC_SWSYNC_SHIFT (7U) 1331 /*! SWSYNC - PWM Synchronization Software Trigger 1332 * 0b0..Software trigger is not selected. 1333 * 0b1..Software trigger is selected. 1334 */ 1335 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK) 1336 /*! @} */ 1337 1338 /*! @name OUTINIT - Initial State For Channels Output */ 1339 /*! @{ */ 1340 #define FTM_OUTINIT_CH0OI_MASK (0x1U) 1341 #define FTM_OUTINIT_CH0OI_SHIFT (0U) 1342 /*! CH0OI - Channel 0 Output Initialization Value 1343 * 0b0..The initialization value is 0. 1344 * 0b1..The initialization value is 1. 1345 */ 1346 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK) 1347 #define FTM_OUTINIT_CH1OI_MASK (0x2U) 1348 #define FTM_OUTINIT_CH1OI_SHIFT (1U) 1349 /*! CH1OI - Channel 1 Output Initialization Value 1350 * 0b0..The initialization value is 0. 1351 * 0b1..The initialization value is 1. 1352 */ 1353 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK) 1354 #define FTM_OUTINIT_CH2OI_MASK (0x4U) 1355 #define FTM_OUTINIT_CH2OI_SHIFT (2U) 1356 /*! CH2OI - Channel 2 Output Initialization Value 1357 * 0b0..The initialization value is 0. 1358 * 0b1..The initialization value is 1. 1359 */ 1360 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK) 1361 #define FTM_OUTINIT_CH3OI_MASK (0x8U) 1362 #define FTM_OUTINIT_CH3OI_SHIFT (3U) 1363 /*! CH3OI - Channel 3 Output Initialization Value 1364 * 0b0..The initialization value is 0. 1365 * 0b1..The initialization value is 1. 1366 */ 1367 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK) 1368 #define FTM_OUTINIT_CH4OI_MASK (0x10U) 1369 #define FTM_OUTINIT_CH4OI_SHIFT (4U) 1370 /*! CH4OI - Channel 4 Output Initialization Value 1371 * 0b0..The initialization value is 0. 1372 * 0b1..The initialization value is 1. 1373 */ 1374 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK) 1375 #define FTM_OUTINIT_CH5OI_MASK (0x20U) 1376 #define FTM_OUTINIT_CH5OI_SHIFT (5U) 1377 /*! CH5OI - Channel 5 Output Initialization Value 1378 * 0b0..The initialization value is 0. 1379 * 0b1..The initialization value is 1. 1380 */ 1381 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK) 1382 #define FTM_OUTINIT_CH6OI_MASK (0x40U) 1383 #define FTM_OUTINIT_CH6OI_SHIFT (6U) 1384 /*! CH6OI - Channel 6 Output Initialization Value 1385 * 0b0..The initialization value is 0. 1386 * 0b1..The initialization value is 1. 1387 */ 1388 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK) 1389 #define FTM_OUTINIT_CH7OI_MASK (0x80U) 1390 #define FTM_OUTINIT_CH7OI_SHIFT (7U) 1391 /*! CH7OI - Channel 7 Output Initialization Value 1392 * 0b0..The initialization value is 0. 1393 * 0b1..The initialization value is 1. 1394 */ 1395 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK) 1396 /*! @} */ 1397 1398 /*! @name OUTMASK - Output Mask */ 1399 /*! @{ */ 1400 #define FTM_OUTMASK_CH0OM_MASK (0x1U) 1401 #define FTM_OUTMASK_CH0OM_SHIFT (0U) 1402 /*! CH0OM - Channel 0 Output Mask 1403 * 0b0..Channel output is not masked. It continues to operate normally. 1404 * 0b1..Channel output is masked. It is forced to its inactive state. 1405 */ 1406 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK) 1407 #define FTM_OUTMASK_CH1OM_MASK (0x2U) 1408 #define FTM_OUTMASK_CH1OM_SHIFT (1U) 1409 /*! CH1OM - Channel 1 Output Mask 1410 * 0b0..Channel output is not masked. It continues to operate normally. 1411 * 0b1..Channel output is masked. It is forced to its inactive state. 1412 */ 1413 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK) 1414 #define FTM_OUTMASK_CH2OM_MASK (0x4U) 1415 #define FTM_OUTMASK_CH2OM_SHIFT (2U) 1416 /*! CH2OM - Channel 2 Output Mask 1417 * 0b0..Channel output is not masked. It continues to operate normally. 1418 * 0b1..Channel output is masked. It is forced to its inactive state. 1419 */ 1420 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK) 1421 #define FTM_OUTMASK_CH3OM_MASK (0x8U) 1422 #define FTM_OUTMASK_CH3OM_SHIFT (3U) 1423 /*! CH3OM - Channel 3 Output Mask 1424 * 0b0..Channel output is not masked. It continues to operate normally. 1425 * 0b1..Channel output is masked. It is forced to its inactive state. 1426 */ 1427 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK) 1428 #define FTM_OUTMASK_CH4OM_MASK (0x10U) 1429 #define FTM_OUTMASK_CH4OM_SHIFT (4U) 1430 /*! CH4OM - Channel 4 Output Mask 1431 * 0b0..Channel output is not masked. It continues to operate normally. 1432 * 0b1..Channel output is masked. It is forced to its inactive state. 1433 */ 1434 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK) 1435 #define FTM_OUTMASK_CH5OM_MASK (0x20U) 1436 #define FTM_OUTMASK_CH5OM_SHIFT (5U) 1437 /*! CH5OM - Channel 5 Output Mask 1438 * 0b0..Channel output is not masked. It continues to operate normally. 1439 * 0b1..Channel output is masked. It is forced to its inactive state. 1440 */ 1441 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK) 1442 #define FTM_OUTMASK_CH6OM_MASK (0x40U) 1443 #define FTM_OUTMASK_CH6OM_SHIFT (6U) 1444 /*! CH6OM - Channel 6 Output Mask 1445 * 0b0..Channel output is not masked. It continues to operate normally. 1446 * 0b1..Channel output is masked. It is forced to its inactive state. 1447 */ 1448 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK) 1449 #define FTM_OUTMASK_CH7OM_MASK (0x80U) 1450 #define FTM_OUTMASK_CH7OM_SHIFT (7U) 1451 /*! CH7OM - Channel 7 Output Mask 1452 * 0b0..Channel output is not masked. It continues to operate normally. 1453 * 0b1..Channel output is masked. It is forced to its inactive state. 1454 */ 1455 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK) 1456 /*! @} */ 1457 1458 /*! @name COMBINE - Function For Linked Channels */ 1459 /*! @{ */ 1460 #define FTM_COMBINE_COMBINE0_MASK (0x1U) 1461 #define FTM_COMBINE_COMBINE0_SHIFT (0U) 1462 /*! COMBINE0 - Combine Channels For n = 0 1463 * 0b0..Channels (n) and (n+1) are independent. 1464 * 0b1..Channels (n) and (n+1) are combined. 1465 */ 1466 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK) 1467 #define FTM_COMBINE_COMP0_MASK (0x2U) 1468 #define FTM_COMBINE_COMP0_SHIFT (1U) 1469 /*! COMP0 - Complement Of Channel (n) For n = 0 1470 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1471 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1472 */ 1473 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK) 1474 #define FTM_COMBINE_DECAPEN0_MASK (0x4U) 1475 #define FTM_COMBINE_DECAPEN0_SHIFT (2U) 1476 /*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0 1477 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1478 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1479 */ 1480 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK) 1481 #define FTM_COMBINE_DECAP0_MASK (0x8U) 1482 #define FTM_COMBINE_DECAP0_SHIFT (3U) 1483 /*! DECAP0 - Dual Edge Capture Mode Captures For n = 0 1484 * 0b0..The dual edge captures are inactive. 1485 * 0b1..The dual edge captures are active. 1486 */ 1487 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK) 1488 #define FTM_COMBINE_DTEN0_MASK (0x10U) 1489 #define FTM_COMBINE_DTEN0_SHIFT (4U) 1490 /*! DTEN0 - Deadtime Enable For n = 0 1491 * 0b0..The deadtime insertion in this pair of channels is disabled. 1492 * 0b1..The deadtime insertion in this pair of channels is enabled. 1493 */ 1494 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK) 1495 #define FTM_COMBINE_SYNCEN0_MASK (0x20U) 1496 #define FTM_COMBINE_SYNCEN0_SHIFT (5U) 1497 /*! SYNCEN0 - Synchronization Enable For n = 0 1498 * 0b0..The PWM synchronization in this pair of channels is disabled. 1499 * 0b1..The PWM synchronization in this pair of channels is enabled. 1500 */ 1501 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK) 1502 #define FTM_COMBINE_FAULTEN0_MASK (0x40U) 1503 #define FTM_COMBINE_FAULTEN0_SHIFT (6U) 1504 /*! FAULTEN0 - Fault Control Enable For n = 0 1505 * 0b0..The fault control in this pair of channels is disabled. 1506 * 0b1..The fault control in this pair of channels is enabled. 1507 */ 1508 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK) 1509 #define FTM_COMBINE_COMBINE1_MASK (0x100U) 1510 #define FTM_COMBINE_COMBINE1_SHIFT (8U) 1511 /*! COMBINE1 - Combine Channels For n = 2 1512 * 0b0..Channels (n) and (n+1) are independent. 1513 * 0b1..Channels (n) and (n+1) are combined. 1514 */ 1515 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK) 1516 #define FTM_COMBINE_COMP1_MASK (0x200U) 1517 #define FTM_COMBINE_COMP1_SHIFT (9U) 1518 /*! COMP1 - Complement Of Channel (n) For n = 2 1519 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1520 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1521 */ 1522 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK) 1523 #define FTM_COMBINE_DECAPEN1_MASK (0x400U) 1524 #define FTM_COMBINE_DECAPEN1_SHIFT (10U) 1525 /*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2 1526 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1527 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1528 */ 1529 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK) 1530 #define FTM_COMBINE_DECAP1_MASK (0x800U) 1531 #define FTM_COMBINE_DECAP1_SHIFT (11U) 1532 /*! DECAP1 - Dual Edge Capture Mode Captures For n = 2 1533 * 0b0..The dual edge captures are inactive. 1534 * 0b1..The dual edge captures are active. 1535 */ 1536 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK) 1537 #define FTM_COMBINE_DTEN1_MASK (0x1000U) 1538 #define FTM_COMBINE_DTEN1_SHIFT (12U) 1539 /*! DTEN1 - Deadtime Enable For n = 2 1540 * 0b0..The deadtime insertion in this pair of channels is disabled. 1541 * 0b1..The deadtime insertion in this pair of channels is enabled. 1542 */ 1543 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK) 1544 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U) 1545 #define FTM_COMBINE_SYNCEN1_SHIFT (13U) 1546 /*! SYNCEN1 - Synchronization Enable For n = 2 1547 * 0b0..The PWM synchronization in this pair of channels is disabled. 1548 * 0b1..The PWM synchronization in this pair of channels is enabled. 1549 */ 1550 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK) 1551 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U) 1552 #define FTM_COMBINE_FAULTEN1_SHIFT (14U) 1553 /*! FAULTEN1 - Fault Control Enable For n = 2 1554 * 0b0..The fault control in this pair of channels is disabled. 1555 * 0b1..The fault control in this pair of channels is enabled. 1556 */ 1557 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK) 1558 #define FTM_COMBINE_COMBINE2_MASK (0x10000U) 1559 #define FTM_COMBINE_COMBINE2_SHIFT (16U) 1560 /*! COMBINE2 - Combine Channels For n = 4 1561 * 0b0..Channels (n) and (n+1) are independent. 1562 * 0b1..Channels (n) and (n+1) are combined. 1563 */ 1564 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK) 1565 #define FTM_COMBINE_COMP2_MASK (0x20000U) 1566 #define FTM_COMBINE_COMP2_SHIFT (17U) 1567 /*! COMP2 - Complement Of Channel (n) For n = 4 1568 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1569 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1570 */ 1571 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK) 1572 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U) 1573 #define FTM_COMBINE_DECAPEN2_SHIFT (18U) 1574 /*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4 1575 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1576 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1577 */ 1578 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK) 1579 #define FTM_COMBINE_DECAP2_MASK (0x80000U) 1580 #define FTM_COMBINE_DECAP2_SHIFT (19U) 1581 /*! DECAP2 - Dual Edge Capture Mode Captures For n = 4 1582 * 0b0..The dual edge captures are inactive. 1583 * 0b1..The dual edge captures are active. 1584 */ 1585 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK) 1586 #define FTM_COMBINE_DTEN2_MASK (0x100000U) 1587 #define FTM_COMBINE_DTEN2_SHIFT (20U) 1588 /*! DTEN2 - Deadtime Enable For n = 4 1589 * 0b0..The deadtime insertion in this pair of channels is disabled. 1590 * 0b1..The deadtime insertion in this pair of channels is enabled. 1591 */ 1592 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK) 1593 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U) 1594 #define FTM_COMBINE_SYNCEN2_SHIFT (21U) 1595 /*! SYNCEN2 - Synchronization Enable For n = 4 1596 * 0b0..The PWM synchronization in this pair of channels is disabled. 1597 * 0b1..The PWM synchronization in this pair of channels is enabled. 1598 */ 1599 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK) 1600 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U) 1601 #define FTM_COMBINE_FAULTEN2_SHIFT (22U) 1602 /*! FAULTEN2 - Fault Control Enable For n = 4 1603 * 0b0..The fault control in this pair of channels is disabled. 1604 * 0b1..The fault control in this pair of channels is enabled. 1605 */ 1606 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK) 1607 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U) 1608 #define FTM_COMBINE_COMBINE3_SHIFT (24U) 1609 /*! COMBINE3 - Combine Channels For n = 6 1610 * 0b0..Channels (n) and (n+1) are independent. 1611 * 0b1..Channels (n) and (n+1) are combined. 1612 */ 1613 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK) 1614 #define FTM_COMBINE_COMP3_MASK (0x2000000U) 1615 #define FTM_COMBINE_COMP3_SHIFT (25U) 1616 /*! COMP3 - Complement Of Channel (n) for n = 6 1617 * 0b0..The channel (n+1) output is the same as the channel (n) output. 1618 * 0b1..The channel (n+1) output is the complement of the channel (n) output. 1619 */ 1620 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK) 1621 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U) 1622 #define FTM_COMBINE_DECAPEN3_SHIFT (26U) 1623 /*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6 1624 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled. 1625 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled. 1626 */ 1627 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK) 1628 #define FTM_COMBINE_DECAP3_MASK (0x8000000U) 1629 #define FTM_COMBINE_DECAP3_SHIFT (27U) 1630 /*! DECAP3 - Dual Edge Capture Mode Captures For n = 6 1631 * 0b0..The dual edge captures are inactive. 1632 * 0b1..The dual edge captures are active. 1633 */ 1634 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK) 1635 #define FTM_COMBINE_DTEN3_MASK (0x10000000U) 1636 #define FTM_COMBINE_DTEN3_SHIFT (28U) 1637 /*! DTEN3 - Deadtime Enable For n = 6 1638 * 0b0..The deadtime insertion in this pair of channels is disabled. 1639 * 0b1..The deadtime insertion in this pair of channels is enabled. 1640 */ 1641 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK) 1642 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U) 1643 #define FTM_COMBINE_SYNCEN3_SHIFT (29U) 1644 /*! SYNCEN3 - Synchronization Enable For n = 6 1645 * 0b0..The PWM synchronization in this pair of channels is disabled. 1646 * 0b1..The PWM synchronization in this pair of channels is enabled. 1647 */ 1648 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK) 1649 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U) 1650 #define FTM_COMBINE_FAULTEN3_SHIFT (30U) 1651 /*! FAULTEN3 - Fault Control Enable For n = 6 1652 * 0b0..The fault control in this pair of channels is disabled. 1653 * 0b1..The fault control in this pair of channels is enabled. 1654 */ 1655 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK) 1656 /*! @} */ 1657 1658 /*! @name DEADTIME - Deadtime Insertion Control */ 1659 /*! @{ */ 1660 #define FTM_DEADTIME_DTVAL_MASK (0x3FU) 1661 #define FTM_DEADTIME_DTVAL_SHIFT (0U) 1662 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK) 1663 #define FTM_DEADTIME_DTPS_MASK (0xC0U) 1664 #define FTM_DEADTIME_DTPS_SHIFT (6U) 1665 /*! DTPS - Deadtime Prescaler Value 1666 * 0b0x..Divide the system clock by 1. 1667 * 0b10..Divide the system clock by 4. 1668 * 0b11..Divide the system clock by 16. 1669 */ 1670 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK) 1671 /*! @} */ 1672 1673 /*! @name EXTTRIG - FTM External Trigger */ 1674 /*! @{ */ 1675 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U) 1676 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U) 1677 /*! CH2TRIG - Channel 2 Trigger Enable 1678 * 0b0..The generation of the channel trigger is disabled. 1679 * 0b1..The generation of the channel trigger is enabled. 1680 */ 1681 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK) 1682 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U) 1683 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U) 1684 /*! CH3TRIG - Channel 3 Trigger Enable 1685 * 0b0..The generation of the channel trigger is disabled. 1686 * 0b1..The generation of the channel trigger is enabled. 1687 */ 1688 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK) 1689 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U) 1690 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U) 1691 /*! CH4TRIG - Channel 4 Trigger Enable 1692 * 0b0..The generation of the channel trigger is disabled. 1693 * 0b1..The generation of the channel trigger is enabled. 1694 */ 1695 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK) 1696 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U) 1697 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U) 1698 /*! CH5TRIG - Channel 5 Trigger Enable 1699 * 0b0..The generation of the channel trigger is disabled. 1700 * 0b1..The generation of the channel trigger is enabled. 1701 */ 1702 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK) 1703 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U) 1704 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U) 1705 /*! CH0TRIG - Channel 0 Trigger Enable 1706 * 0b0..The generation of the channel trigger is disabled. 1707 * 0b1..The generation of the channel trigger is enabled. 1708 */ 1709 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK) 1710 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U) 1711 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U) 1712 /*! CH1TRIG - Channel 1 Trigger Enable 1713 * 0b0..The generation of the channel trigger is disabled. 1714 * 0b1..The generation of the channel trigger is enabled. 1715 */ 1716 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK) 1717 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U) 1718 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U) 1719 /*! INITTRIGEN - Initialization Trigger Enable 1720 * 0b0..The generation of initialization trigger is disabled. 1721 * 0b1..The generation of initialization trigger is enabled. 1722 */ 1723 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK) 1724 #define FTM_EXTTRIG_TRIGF_MASK (0x80U) 1725 #define FTM_EXTTRIG_TRIGF_SHIFT (7U) 1726 /*! TRIGF - Channel Trigger Flag 1727 * 0b0..No channel trigger was generated. 1728 * 0b1..A channel trigger was generated. 1729 */ 1730 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK) 1731 /*! @} */ 1732 1733 /*! @name POL - Channels Polarity */ 1734 /*! @{ */ 1735 #define FTM_POL_POL0_MASK (0x1U) 1736 #define FTM_POL_POL0_SHIFT (0U) 1737 /*! POL0 - Channel 0 Polarity 1738 * 0b0..The channel polarity is active high. 1739 * 0b1..The channel polarity is active low. 1740 */ 1741 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK) 1742 #define FTM_POL_POL1_MASK (0x2U) 1743 #define FTM_POL_POL1_SHIFT (1U) 1744 /*! POL1 - Channel 1 Polarity 1745 * 0b0..The channel polarity is active high. 1746 * 0b1..The channel polarity is active low. 1747 */ 1748 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK) 1749 #define FTM_POL_POL2_MASK (0x4U) 1750 #define FTM_POL_POL2_SHIFT (2U) 1751 /*! POL2 - Channel 2 Polarity 1752 * 0b0..The channel polarity is active high. 1753 * 0b1..The channel polarity is active low. 1754 */ 1755 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK) 1756 #define FTM_POL_POL3_MASK (0x8U) 1757 #define FTM_POL_POL3_SHIFT (3U) 1758 /*! POL3 - Channel 3 Polarity 1759 * 0b0..The channel polarity is active high. 1760 * 0b1..The channel polarity is active low. 1761 */ 1762 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK) 1763 #define FTM_POL_POL4_MASK (0x10U) 1764 #define FTM_POL_POL4_SHIFT (4U) 1765 /*! POL4 - Channel 4 Polarity 1766 * 0b0..The channel polarity is active high. 1767 * 0b1..The channel polarity is active low. 1768 */ 1769 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK) 1770 #define FTM_POL_POL5_MASK (0x20U) 1771 #define FTM_POL_POL5_SHIFT (5U) 1772 /*! POL5 - Channel 5 Polarity 1773 * 0b0..The channel polarity is active high. 1774 * 0b1..The channel polarity is active low. 1775 */ 1776 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK) 1777 #define FTM_POL_POL6_MASK (0x40U) 1778 #define FTM_POL_POL6_SHIFT (6U) 1779 /*! POL6 - Channel 6 Polarity 1780 * 0b0..The channel polarity is active high. 1781 * 0b1..The channel polarity is active low. 1782 */ 1783 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK) 1784 #define FTM_POL_POL7_MASK (0x80U) 1785 #define FTM_POL_POL7_SHIFT (7U) 1786 /*! POL7 - Channel 7 Polarity 1787 * 0b0..The channel polarity is active high. 1788 * 0b1..The channel polarity is active low. 1789 */ 1790 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK) 1791 /*! @} */ 1792 1793 /*! @name FMS - Fault Mode Status */ 1794 /*! @{ */ 1795 #define FTM_FMS_FAULTF0_MASK (0x1U) 1796 #define FTM_FMS_FAULTF0_SHIFT (0U) 1797 /*! FAULTF0 - Fault Detection Flag 0 1798 * 0b0..No fault condition was detected at the fault input. 1799 * 0b1..A fault condition was detected at the fault input. 1800 */ 1801 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK) 1802 #define FTM_FMS_FAULTF1_MASK (0x2U) 1803 #define FTM_FMS_FAULTF1_SHIFT (1U) 1804 /*! FAULTF1 - Fault Detection Flag 1 1805 * 0b0..No fault condition was detected at the fault input. 1806 * 0b1..A fault condition was detected at the fault input. 1807 */ 1808 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK) 1809 #define FTM_FMS_FAULTF2_MASK (0x4U) 1810 #define FTM_FMS_FAULTF2_SHIFT (2U) 1811 /*! FAULTF2 - Fault Detection Flag 2 1812 * 0b0..No fault condition was detected at the fault input. 1813 * 0b1..A fault condition was detected at the fault input. 1814 */ 1815 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK) 1816 #define FTM_FMS_FAULTF3_MASK (0x8U) 1817 #define FTM_FMS_FAULTF3_SHIFT (3U) 1818 /*! FAULTF3 - Fault Detection Flag 3 1819 * 0b0..No fault condition was detected at the fault input. 1820 * 0b1..A fault condition was detected at the fault input. 1821 */ 1822 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK) 1823 #define FTM_FMS_FAULTIN_MASK (0x20U) 1824 #define FTM_FMS_FAULTIN_SHIFT (5U) 1825 /*! FAULTIN - Fault Inputs 1826 * 0b0..The logic OR of the enabled fault inputs is 0. 1827 * 0b1..The logic OR of the enabled fault inputs is 1. 1828 */ 1829 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK) 1830 #define FTM_FMS_WPEN_MASK (0x40U) 1831 #define FTM_FMS_WPEN_SHIFT (6U) 1832 /*! WPEN - Write Protection Enable 1833 * 0b0..Write protection is disabled. Write protected bits can be written. 1834 * 0b1..Write protection is enabled. Write protected bits cannot be written. 1835 */ 1836 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK) 1837 #define FTM_FMS_FAULTF_MASK (0x80U) 1838 #define FTM_FMS_FAULTF_SHIFT (7U) 1839 /*! FAULTF - Fault Detection Flag 1840 * 0b0..No fault condition was detected. 1841 * 0b1..A fault condition was detected. 1842 */ 1843 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK) 1844 /*! @} */ 1845 1846 /*! @name FILTER - Input Capture Filter Control */ 1847 /*! @{ */ 1848 #define FTM_FILTER_CH0FVAL_MASK (0xFU) 1849 #define FTM_FILTER_CH0FVAL_SHIFT (0U) 1850 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK) 1851 #define FTM_FILTER_CH1FVAL_MASK (0xF0U) 1852 #define FTM_FILTER_CH1FVAL_SHIFT (4U) 1853 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK) 1854 #define FTM_FILTER_CH2FVAL_MASK (0xF00U) 1855 #define FTM_FILTER_CH2FVAL_SHIFT (8U) 1856 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK) 1857 #define FTM_FILTER_CH3FVAL_MASK (0xF000U) 1858 #define FTM_FILTER_CH3FVAL_SHIFT (12U) 1859 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK) 1860 /*! @} */ 1861 1862 /*! @name FLTCTRL - Fault Control */ 1863 /*! @{ */ 1864 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U) 1865 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U) 1866 /*! FAULT0EN - Fault Input 0 Enable 1867 * 0b0..Fault input is disabled. 1868 * 0b1..Fault input is enabled. 1869 */ 1870 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK) 1871 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U) 1872 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U) 1873 /*! FAULT1EN - Fault Input 1 Enable 1874 * 0b0..Fault input is disabled. 1875 * 0b1..Fault input is enabled. 1876 */ 1877 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK) 1878 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U) 1879 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U) 1880 /*! FAULT2EN - Fault Input 2 Enable 1881 * 0b0..Fault input is disabled. 1882 * 0b1..Fault input is enabled. 1883 */ 1884 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK) 1885 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U) 1886 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U) 1887 /*! FAULT3EN - Fault Input 3 Enable 1888 * 0b0..Fault input is disabled. 1889 * 0b1..Fault input is enabled. 1890 */ 1891 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK) 1892 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U) 1893 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U) 1894 /*! FFLTR0EN - Fault Input 0 Filter Enable 1895 * 0b0..Fault input filter is disabled. 1896 * 0b1..Fault input filter is enabled. 1897 */ 1898 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK) 1899 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U) 1900 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U) 1901 /*! FFLTR1EN - Fault Input 1 Filter Enable 1902 * 0b0..Fault input filter is disabled. 1903 * 0b1..Fault input filter is enabled. 1904 */ 1905 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK) 1906 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U) 1907 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U) 1908 /*! FFLTR2EN - Fault Input 2 Filter Enable 1909 * 0b0..Fault input filter is disabled. 1910 * 0b1..Fault input filter is enabled. 1911 */ 1912 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK) 1913 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U) 1914 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U) 1915 /*! FFLTR3EN - Fault Input 3 Filter Enable 1916 * 0b0..Fault input filter is disabled. 1917 * 0b1..Fault input filter is enabled. 1918 */ 1919 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK) 1920 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U) 1921 #define FTM_FLTCTRL_FFVAL_SHIFT (8U) 1922 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK) 1923 /*! @} */ 1924 1925 /*! @name CONF - Configuration */ 1926 /*! @{ */ 1927 #define FTM_CONF_NUMTOF_MASK (0x1FU) 1928 #define FTM_CONF_NUMTOF_SHIFT (0U) 1929 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK) 1930 #define FTM_CONF_BDMMODE_MASK (0xC0U) 1931 #define FTM_CONF_BDMMODE_SHIFT (6U) 1932 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK) 1933 #define FTM_CONF_GTBEEN_MASK (0x200U) 1934 #define FTM_CONF_GTBEEN_SHIFT (9U) 1935 /*! GTBEEN - Global Time Base Enable 1936 * 0b0..Use of an external global time base is disabled. 1937 * 0b1..Use of an external global time base is enabled. 1938 */ 1939 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK) 1940 #define FTM_CONF_GTBEOUT_MASK (0x400U) 1941 #define FTM_CONF_GTBEOUT_SHIFT (10U) 1942 /*! GTBEOUT - Global Time Base Output 1943 * 0b0..A global time base signal generation is disabled. 1944 * 0b1..A global time base signal generation is enabled. 1945 */ 1946 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK) 1947 /*! @} */ 1948 1949 /*! @name FLTPOL - FTM Fault Input Polarity */ 1950 /*! @{ */ 1951 #define FTM_FLTPOL_FLT0POL_MASK (0x1U) 1952 #define FTM_FLTPOL_FLT0POL_SHIFT (0U) 1953 /*! FLT0POL - Fault Input 0 Polarity 1954 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1955 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1956 */ 1957 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK) 1958 #define FTM_FLTPOL_FLT1POL_MASK (0x2U) 1959 #define FTM_FLTPOL_FLT1POL_SHIFT (1U) 1960 /*! FLT1POL - Fault Input 1 Polarity 1961 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1962 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1963 */ 1964 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK) 1965 #define FTM_FLTPOL_FLT2POL_MASK (0x4U) 1966 #define FTM_FLTPOL_FLT2POL_SHIFT (2U) 1967 /*! FLT2POL - Fault Input 2 Polarity 1968 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1969 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1970 */ 1971 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK) 1972 #define FTM_FLTPOL_FLT3POL_MASK (0x8U) 1973 #define FTM_FLTPOL_FLT3POL_SHIFT (3U) 1974 /*! FLT3POL - Fault Input 3 Polarity 1975 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault. 1976 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault. 1977 */ 1978 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK) 1979 /*! @} */ 1980 1981 /*! @name SYNCONF - Synchronization Configuration */ 1982 /*! @{ */ 1983 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U) 1984 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U) 1985 /*! HWTRIGMODE - Hardware Trigger Mode 1986 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 1987 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2. 1988 */ 1989 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK) 1990 #define FTM_SYNCONF_CNTINC_MASK (0x4U) 1991 #define FTM_SYNCONF_CNTINC_SHIFT (2U) 1992 /*! CNTINC - CNTIN Register Synchronization 1993 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock. 1994 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization. 1995 */ 1996 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK) 1997 #define FTM_SYNCONF_INVC_MASK (0x10U) 1998 #define FTM_SYNCONF_INVC_SHIFT (4U) 1999 /*! INVC - INVCTRL Register Synchronization 2000 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock. 2001 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization. 2002 */ 2003 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK) 2004 #define FTM_SYNCONF_SWOC_MASK (0x20U) 2005 #define FTM_SYNCONF_SWOC_SHIFT (5U) 2006 /*! SWOC - SWOCTRL Register Synchronization 2007 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock. 2008 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization. 2009 */ 2010 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK) 2011 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U) 2012 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U) 2013 /*! SYNCMODE - Synchronization Mode 2014 * 0b0..Legacy PWM synchronization is selected. 2015 * 0b1..Enhanced PWM synchronization is selected. 2016 */ 2017 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK) 2018 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U) 2019 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U) 2020 /*! SWRSTCNT 2021 * 0b0..The software trigger does not activate the FTM counter synchronization. 2022 * 0b1..The software trigger activates the FTM counter synchronization. 2023 */ 2024 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK) 2025 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U) 2026 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U) 2027 /*! SWWRBUF 2028 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization. 2029 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization. 2030 */ 2031 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK) 2032 #define FTM_SYNCONF_SWOM_MASK (0x400U) 2033 #define FTM_SYNCONF_SWOM_SHIFT (10U) 2034 /*! SWOM 2035 * 0b0..The software trigger does not activate the OUTMASK register synchronization. 2036 * 0b1..The software trigger activates the OUTMASK register synchronization. 2037 */ 2038 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK) 2039 #define FTM_SYNCONF_SWINVC_MASK (0x800U) 2040 #define FTM_SYNCONF_SWINVC_SHIFT (11U) 2041 /*! SWINVC 2042 * 0b0..The software trigger does not activate the INVCTRL register synchronization. 2043 * 0b1..The software trigger activates the INVCTRL register synchronization. 2044 */ 2045 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK) 2046 #define FTM_SYNCONF_SWSOC_MASK (0x1000U) 2047 #define FTM_SYNCONF_SWSOC_SHIFT (12U) 2048 /*! SWSOC 2049 * 0b0..The software trigger does not activate the SWOCTRL register synchronization. 2050 * 0b1..The software trigger activates the SWOCTRL register synchronization. 2051 */ 2052 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK) 2053 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U) 2054 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U) 2055 /*! HWRSTCNT 2056 * 0b0..A hardware trigger does not activate the FTM counter synchronization. 2057 * 0b1..A hardware trigger activates the FTM counter synchronization. 2058 */ 2059 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK) 2060 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U) 2061 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U) 2062 /*! HWWRBUF 2063 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. 2064 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization. 2065 */ 2066 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK) 2067 #define FTM_SYNCONF_HWOM_MASK (0x40000U) 2068 #define FTM_SYNCONF_HWOM_SHIFT (18U) 2069 /*! HWOM 2070 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization. 2071 * 0b1..A hardware trigger activates the OUTMASK register synchronization. 2072 */ 2073 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK) 2074 #define FTM_SYNCONF_HWINVC_MASK (0x80000U) 2075 #define FTM_SYNCONF_HWINVC_SHIFT (19U) 2076 /*! HWINVC 2077 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization. 2078 * 0b1..A hardware trigger activates the INVCTRL register synchronization. 2079 */ 2080 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK) 2081 #define FTM_SYNCONF_HWSOC_MASK (0x100000U) 2082 #define FTM_SYNCONF_HWSOC_SHIFT (20U) 2083 /*! HWSOC 2084 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization. 2085 * 0b1..A hardware trigger activates the SWOCTRL register synchronization. 2086 */ 2087 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK) 2088 /*! @} */ 2089 2090 /*! @name INVCTRL - FTM Inverting Control */ 2091 /*! @{ */ 2092 #define FTM_INVCTRL_INV0EN_MASK (0x1U) 2093 #define FTM_INVCTRL_INV0EN_SHIFT (0U) 2094 /*! INV0EN - Pair Channels 0 Inverting Enable 2095 * 0b0..Inverting is disabled. 2096 * 0b1..Inverting is enabled. 2097 */ 2098 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK) 2099 #define FTM_INVCTRL_INV1EN_MASK (0x2U) 2100 #define FTM_INVCTRL_INV1EN_SHIFT (1U) 2101 /*! INV1EN - Pair Channels 1 Inverting Enable 2102 * 0b0..Inverting is disabled. 2103 * 0b1..Inverting is enabled. 2104 */ 2105 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK) 2106 #define FTM_INVCTRL_INV2EN_MASK (0x4U) 2107 #define FTM_INVCTRL_INV2EN_SHIFT (2U) 2108 /*! INV2EN - Pair Channels 2 Inverting Enable 2109 * 0b0..Inverting is disabled. 2110 * 0b1..Inverting is enabled. 2111 */ 2112 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK) 2113 #define FTM_INVCTRL_INV3EN_MASK (0x8U) 2114 #define FTM_INVCTRL_INV3EN_SHIFT (3U) 2115 /*! INV3EN - Pair Channels 3 Inverting Enable 2116 * 0b0..Inverting is disabled. 2117 * 0b1..Inverting is enabled. 2118 */ 2119 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK) 2120 /*! @} */ 2121 2122 /*! @name SWOCTRL - FTM Software Output Control */ 2123 /*! @{ */ 2124 #define FTM_SWOCTRL_CH0OC_MASK (0x1U) 2125 #define FTM_SWOCTRL_CH0OC_SHIFT (0U) 2126 /*! CH0OC - Channel 0 Software Output Control Enable 2127 * 0b0..The channel output is not affected by software output control. 2128 * 0b1..The channel output is affected by software output control. 2129 */ 2130 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK) 2131 #define FTM_SWOCTRL_CH1OC_MASK (0x2U) 2132 #define FTM_SWOCTRL_CH1OC_SHIFT (1U) 2133 /*! CH1OC - Channel 1 Software Output Control Enable 2134 * 0b0..The channel output is not affected by software output control. 2135 * 0b1..The channel output is affected by software output control. 2136 */ 2137 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK) 2138 #define FTM_SWOCTRL_CH2OC_MASK (0x4U) 2139 #define FTM_SWOCTRL_CH2OC_SHIFT (2U) 2140 /*! CH2OC - Channel 2 Software Output Control Enable 2141 * 0b0..The channel output is not affected by software output control. 2142 * 0b1..The channel output is affected by software output control. 2143 */ 2144 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK) 2145 #define FTM_SWOCTRL_CH3OC_MASK (0x8U) 2146 #define FTM_SWOCTRL_CH3OC_SHIFT (3U) 2147 /*! CH3OC - Channel 3 Software Output Control Enable 2148 * 0b0..The channel output is not affected by software output control. 2149 * 0b1..The channel output is affected by software output control. 2150 */ 2151 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK) 2152 #define FTM_SWOCTRL_CH4OC_MASK (0x10U) 2153 #define FTM_SWOCTRL_CH4OC_SHIFT (4U) 2154 /*! CH4OC - Channel 4 Software Output Control Enable 2155 * 0b0..The channel output is not affected by software output control. 2156 * 0b1..The channel output is affected by software output control. 2157 */ 2158 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK) 2159 #define FTM_SWOCTRL_CH5OC_MASK (0x20U) 2160 #define FTM_SWOCTRL_CH5OC_SHIFT (5U) 2161 /*! CH5OC - Channel 5 Software Output Control Enable 2162 * 0b0..The channel output is not affected by software output control. 2163 * 0b1..The channel output is affected by software output control. 2164 */ 2165 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK) 2166 #define FTM_SWOCTRL_CH6OC_MASK (0x40U) 2167 #define FTM_SWOCTRL_CH6OC_SHIFT (6U) 2168 /*! CH6OC - Channel 6 Software Output Control Enable 2169 * 0b0..The channel output is not affected by software output control. 2170 * 0b1..The channel output is affected by software output control. 2171 */ 2172 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK) 2173 #define FTM_SWOCTRL_CH7OC_MASK (0x80U) 2174 #define FTM_SWOCTRL_CH7OC_SHIFT (7U) 2175 /*! CH7OC - Channel 7 Software Output Control Enable 2176 * 0b0..The channel output is not affected by software output control. 2177 * 0b1..The channel output is affected by software output control. 2178 */ 2179 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK) 2180 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U) 2181 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U) 2182 /*! CH0OCV - Channel 0 Software Output Control Value 2183 * 0b0..The software output control forces 0 to the channel output. 2184 * 0b1..The software output control forces 1 to the channel output. 2185 */ 2186 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK) 2187 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U) 2188 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U) 2189 /*! CH1OCV - Channel 1 Software Output Control Value 2190 * 0b0..The software output control forces 0 to the channel output. 2191 * 0b1..The software output control forces 1 to the channel output. 2192 */ 2193 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK) 2194 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U) 2195 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U) 2196 /*! CH2OCV - Channel 2 Software Output Control Value 2197 * 0b0..The software output control forces 0 to the channel output. 2198 * 0b1..The software output control forces 1 to the channel output. 2199 */ 2200 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK) 2201 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U) 2202 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U) 2203 /*! CH3OCV - Channel 3 Software Output Control Value 2204 * 0b0..The software output control forces 0 to the channel output. 2205 * 0b1..The software output control forces 1 to the channel output. 2206 */ 2207 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK) 2208 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U) 2209 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U) 2210 /*! CH4OCV - Channel 4 Software Output Control Value 2211 * 0b0..The software output control forces 0 to the channel output. 2212 * 0b1..The software output control forces 1 to the channel output. 2213 */ 2214 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK) 2215 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U) 2216 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U) 2217 /*! CH5OCV - Channel 5 Software Output Control Value 2218 * 0b0..The software output control forces 0 to the channel output. 2219 * 0b1..The software output control forces 1 to the channel output. 2220 */ 2221 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK) 2222 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U) 2223 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U) 2224 /*! CH6OCV - Channel 6 Software Output Control Value 2225 * 0b0..The software output control forces 0 to the channel output. 2226 * 0b1..The software output control forces 1 to the channel output. 2227 */ 2228 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK) 2229 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U) 2230 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U) 2231 /*! CH7OCV - Channel 7 Software Output Control Value 2232 * 0b0..The software output control forces 0 to the channel output. 2233 * 0b1..The software output control forces 1 to the channel output. 2234 */ 2235 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK) 2236 /*! @} */ 2237 2238 /*! @name PWMLOAD - FTM PWM Load */ 2239 /*! @{ */ 2240 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U) 2241 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U) 2242 /*! CH0SEL - Channel 0 Select 2243 * 0b0..Do not include the channel in the matching process. 2244 * 0b1..Include the channel in the matching process. 2245 */ 2246 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK) 2247 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U) 2248 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U) 2249 /*! CH1SEL - Channel 1 Select 2250 * 0b0..Do not include the channel in the matching process. 2251 * 0b1..Include the channel in the matching process. 2252 */ 2253 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK) 2254 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U) 2255 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U) 2256 /*! CH2SEL - Channel 2 Select 2257 * 0b0..Do not include the channel in the matching process. 2258 * 0b1..Include the channel in the matching process. 2259 */ 2260 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK) 2261 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U) 2262 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U) 2263 /*! CH3SEL - Channel 3 Select 2264 * 0b0..Do not include the channel in the matching process. 2265 * 0b1..Include the channel in the matching process. 2266 */ 2267 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK) 2268 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U) 2269 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U) 2270 /*! CH4SEL - Channel 4 Select 2271 * 0b0..Do not include the channel in the matching process. 2272 * 0b1..Include the channel in the matching process. 2273 */ 2274 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK) 2275 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U) 2276 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U) 2277 /*! CH5SEL - Channel 5 Select 2278 * 0b0..Do not include the channel in the matching process. 2279 * 0b1..Include the channel in the matching process. 2280 */ 2281 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK) 2282 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U) 2283 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U) 2284 /*! CH6SEL - Channel 6 Select 2285 * 0b0..Do not include the channel in the matching process. 2286 * 0b1..Include the channel in the matching process. 2287 */ 2288 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK) 2289 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U) 2290 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U) 2291 /*! CH7SEL - Channel 7 Select 2292 * 0b0..Do not include the channel in the matching process. 2293 * 0b1..Include the channel in the matching process. 2294 */ 2295 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK) 2296 #define FTM_PWMLOAD_LDOK_MASK (0x200U) 2297 #define FTM_PWMLOAD_LDOK_SHIFT (9U) 2298 /*! LDOK - Load Enable 2299 * 0b0..Loading updated values is disabled. 2300 * 0b1..Loading updated values is enabled. 2301 */ 2302 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK) 2303 /*! @} */ 2304 2305 2306 /*! 2307 * @} 2308 */ /* end of group FTM_Register_Masks */ 2309 2310 2311 /* FTM - Peripheral instance base addresses */ 2312 /** Peripheral FTM0 base address */ 2313 #define FTM0_BASE (0x40038000u) 2314 /** Peripheral FTM0 base pointer */ 2315 #define FTM0 ((FTM_Type *)FTM0_BASE) 2316 /** Peripheral FTM1 base address */ 2317 #define FTM1_BASE (0x40039000u) 2318 /** Peripheral FTM1 base pointer */ 2319 #define FTM1 ((FTM_Type *)FTM1_BASE) 2320 /** Peripheral FTM2 base address */ 2321 #define FTM2_BASE (0x4003A000u) 2322 /** Peripheral FTM2 base pointer */ 2323 #define FTM2 ((FTM_Type *)FTM2_BASE) 2324 /** Array initializer of FTM peripheral base addresses */ 2325 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE } 2326 /** Array initializer of FTM peripheral base pointers */ 2327 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2 } 2328 /** Interrupt vectors for the FTM peripheral type */ 2329 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn } 2330 /* Backward compatibility */ 2331 /*! @name SC - Status And Control */ 2332 #define TPM_SC_PS_MASK FTM_SC_PS_MASK 2333 #define TPM_SC_PS_SHIFT FTM_SC_PS_SHIFT 2334 #define TPM_SC_PS(x) FTM_SC_PS(x) 2335 #define TPM_SC_CLKS_MASK FTM_SC_CLKS_MASK 2336 #define TPM_SC_CLKS_SHIFT FTM_SC_CLKS_SHIFT 2337 #define TPM_SC_CLKS(x) FTM_SC_CLKS(x) 2338 #define TPM_SC_CPWMS_MASK FTM_SC_CPWMS_MASK 2339 #define TPM_SC_CPWMS_SHIFT FTM_SC_CPWMS_SHIFT 2340 #define TPM_SC_CPWMS(x) FTM_SC_CPWMS(x) 2341 #define TPM_SC_TOIE_MASK FTM_SC_TOIE_MASK 2342 #define TPM_SC_TOIE_SHIFT FTM_SC_TOIE_SHIFT 2343 #define TPM_SC_TOIE(x) FTM_SC_TOIE(x) 2344 #define TPM_SC_TOF_MASK FTM_SC_TOF_MASK 2345 #define TPM_SC_TOF_SHIFT FTM_SC_TOF_SHIFT 2346 #define TPM_SC_TOF(x) FTM_SC_TOF(x) 2347 /*! @name CNT - Counter */ 2348 #define TPM_CNT_COUNT_MASK FTM_CNT_COUNT_MASK 2349 #define TPM_CNT_COUNT_SHIFT FTM_CNT_COUNT_SHIFT 2350 #define TPM_CNT_COUNT(x) FTM_CNT_COUNT(x) 2351 /*! @name MOD - Modulo */ 2352 #define TPM_MOD_MOD_MASK FTM_MOD_MOD_MASK 2353 #define TPM_MOD_MOD_SHIFT FTM_MOD_MOD_SHIFT 2354 #define TPM_MOD_MOD(x) FTM_MOD_MOD(x) 2355 /*! @name CnSC - Channel (n) Status And Control */ 2356 #define TPM_CnSC_ELSA_MASK FTM_CnSC_ELSA_MASK 2357 #define TPM_CnSC_ELSA_SHIFT FTM_CnSC_ELSA_SHIFT 2358 #define TPM_CnSC_ELSA(x) FTM_CnSC_ELSA(x) 2359 #define TPM_CnSC_ELSB_MASK FTM_CnSC_ELSB_MASK 2360 #define TPM_CnSC_ELSB_SHIFT FTM_CnSC_ELSB_SHIFT 2361 #define TPM_CnSC_ELSB(x) FTM_CnSC_ELSB(x) 2362 #define TPM_CnSC_MSA_MASK FTM_CnSC_MSA_MASK 2363 #define TPM_CnSC_MSA_SHIFT FTM_CnSC_MSA_SHIFT 2364 #define TPM_CnSC_MSA(x) FTM_CnSC_MSA(x) 2365 #define TPM_CnSC_MSB_MASK FTM_CnSC_MSB_MASK 2366 #define TPM_CnSC_MSB_SHIFT FTM_CnSC_MSB_SHIFT 2367 #define TPM_CnSC_MSB(x) FTM_CnSC_MSB(x) 2368 #define TPM_CnSC_CHIE_MASK FTM_CnSC_CHIE_MASK 2369 #define TPM_CnSC_CHIE_SHIFT FTM_CnSC_CHIE_SHIFT 2370 #define TPM_CnSC_CHIE(x) FTM_CnSC_CHIE(x) 2371 #define TPM_CnSC_CHF_MASK FTM_CnSC_CHF_MASK 2372 #define TPM_CnSC_CHF_SHIFT FTM_CnSC_CHF_SHIFT 2373 #define TPM_CnSC_CHF(x) FTM_CnSC_CHF(x) 2374 /* The count of FTM_CnSC */ 2375 #define TPM_CnSC_COUNT (2U) 2376 /*! @name CnV - Channel (n) Value */ 2377 #define TPM_CnV_VAL_MASK FTM_CnV_VAL_MASK 2378 #define TPM_CnV_VAL_SHIFT FTM_CnV_VAL_SHIFT 2379 #define TPM_CnV_VAL(x) FTM_CnV_VAL(x) 2380 /* The count of FTM_CnSC */ 2381 #define TPM_CnV_COUNT (2U) 2382 /** TPM - Register Layout Typedef */ 2383 typedef FTM_Type TPM_Type; 2384 #define TPM0_IRQn FTM0_IRQn 2385 #define TPM0_IRQHandler FTM0_IRQHandler 2386 #define TPM1_IRQn FTM1_IRQn 2387 #define TPM1_IRQHandler FTM1_IRQHandler 2388 #define TPM_CLOCKS FTM_CLOCKS 2389 /* TPM - Peripheral instance base addresses */ 2390 /** Peripheral TPM0 base address */ 2391 #define TPM0_BASE FTM0_BASE 2392 /** Peripheral TPM0 base pointer */ 2393 #define TPM0 ((TPM_Type *)TPM0_BASE) 2394 /** Peripheral TPM1 base address */ 2395 #define TPM1_BASE FTM1_BASE 2396 /** Peripheral TPM1 base pointer */ 2397 #define TPM1 ((TPM_Type *)TPM1_BASE) 2398 /** Array initializer of TPM peripheral base addresses */ 2399 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE } 2400 /** Array initializer of TPM peripheral base pointers */ 2401 #define TPM_BASE_PTRS { TPM0, TPM1 } 2402 /** Interrupt vectors for the TPM peripheral type */ 2403 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn } 2404 2405 2406 /*! 2407 * @} 2408 */ /* end of group FTM_Peripheral_Access_Layer */ 2409 2410 2411 /* ---------------------------------------------------------------------------- 2412 -- FTMRE Peripheral Access Layer 2413 ---------------------------------------------------------------------------- */ 2414 2415 /*! 2416 * @addtogroup FTMRE_Peripheral_Access_Layer FTMRE Peripheral Access Layer 2417 * @{ 2418 */ 2419 2420 /** FTMRE - Register Layout Typedef */ 2421 typedef struct { 2422 uint8_t RESERVED_0[1]; 2423 __IO uint8_t FCCOBIX; /**< Flash CCOB Index Register, offset: 0x1 */ 2424 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 2425 __IO uint8_t FCLKDIV; /**< Flash Clock Divider Register, offset: 0x3 */ 2426 uint8_t RESERVED_1[1]; 2427 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x5 */ 2428 uint8_t RESERVED_2[1]; 2429 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x7 */ 2430 __IO uint8_t FCCOBLO; /**< Flash Common Command Object Register: Low, offset: 0x8 */ 2431 __IO uint8_t FCCOBHI; /**< Flash Common Command Object Register:High, offset: 0x9 */ 2432 uint8_t RESERVED_3[1]; 2433 __IO uint8_t FPROT; /**< Flash Protection Register, offset: 0xB */ 2434 uint8_t RESERVED_4[3]; 2435 __I uint8_t FOPT; /**< Flash Option Register, offset: 0xF */ 2436 } FTMRE_Type; 2437 2438 /* ---------------------------------------------------------------------------- 2439 -- FTMRE Register Masks 2440 ---------------------------------------------------------------------------- */ 2441 2442 /*! 2443 * @addtogroup FTMRE_Register_Masks FTMRE Register Masks 2444 * @{ 2445 */ 2446 2447 /*! @name FCCOBIX - Flash CCOB Index Register */ 2448 /*! @{ */ 2449 #define FTMRE_FCCOBIX_CCOBIX_MASK (0x7U) 2450 #define FTMRE_FCCOBIX_CCOBIX_SHIFT (0U) 2451 #define FTMRE_FCCOBIX_CCOBIX(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCCOBIX_CCOBIX_SHIFT)) & FTMRE_FCCOBIX_CCOBIX_MASK) 2452 /*! @} */ 2453 2454 /*! @name FSEC - Flash Security Register */ 2455 /*! @{ */ 2456 #define FTMRE_FSEC_SEC_MASK (0x3U) 2457 #define FTMRE_FSEC_SEC_SHIFT (0U) 2458 /*! SEC - Flash Security Bits 2459 * 0b00..Secured 2460 * 0b01..Secured 2461 * 0b10..Unsecured 2462 * 0b11..Secured 2463 */ 2464 #define FTMRE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSEC_SEC_SHIFT)) & FTMRE_FSEC_SEC_MASK) 2465 #define FTMRE_FSEC_KEYEN_MASK (0xC0U) 2466 #define FTMRE_FSEC_KEYEN_SHIFT (6U) 2467 /*! KEYEN - Backdoor Key Security Enable Bits 2468 * 0b00..Disabled 2469 * 0b01..Disabled 2470 * 0b10..Enabled 2471 * 0b11..Disabled 2472 */ 2473 #define FTMRE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSEC_KEYEN_SHIFT)) & FTMRE_FSEC_KEYEN_MASK) 2474 /*! @} */ 2475 2476 /*! @name FCLKDIV - Flash Clock Divider Register */ 2477 /*! @{ */ 2478 #define FTMRE_FCLKDIV_FDIV_MASK (0x3FU) 2479 #define FTMRE_FCLKDIV_FDIV_SHIFT (0U) 2480 #define FTMRE_FCLKDIV_FDIV(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCLKDIV_FDIV_SHIFT)) & FTMRE_FCLKDIV_FDIV_MASK) 2481 #define FTMRE_FCLKDIV_FDIVLCK_MASK (0x40U) 2482 #define FTMRE_FCLKDIV_FDIVLCK_SHIFT (6U) 2483 /*! FDIVLCK - Clock Divider Locked 2484 * 0b0..FDIV field is open for writing. 2485 * 0b1..FDIV value is locked and cannot be changed. After the lock bit is set high, only reset can clear this bit and restore writability to the FDIV field in user mode. 2486 */ 2487 #define FTMRE_FCLKDIV_FDIVLCK(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCLKDIV_FDIVLCK_SHIFT)) & FTMRE_FCLKDIV_FDIVLCK_MASK) 2488 #define FTMRE_FCLKDIV_FDIVLD_MASK (0x80U) 2489 #define FTMRE_FCLKDIV_FDIVLD_SHIFT (7U) 2490 /*! FDIVLD - Clock Divider Loaded 2491 * 0b0..FCLKDIV register has not been written since the last reset. 2492 * 0b1..FCLKDIV register has been written since the last reset. 2493 */ 2494 #define FTMRE_FCLKDIV_FDIVLD(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCLKDIV_FDIVLD_SHIFT)) & FTMRE_FCLKDIV_FDIVLD_MASK) 2495 /*! @} */ 2496 2497 /*! @name FSTAT - Flash Status Register */ 2498 /*! @{ */ 2499 #define FTMRE_FSTAT_MGSTAT_MASK (0x3U) 2500 #define FTMRE_FSTAT_MGSTAT_SHIFT (0U) 2501 #define FTMRE_FSTAT_MGSTAT(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_MGSTAT_SHIFT)) & FTMRE_FSTAT_MGSTAT_MASK) 2502 #define FTMRE_FSTAT_MGBUSY_MASK (0x8U) 2503 #define FTMRE_FSTAT_MGBUSY_SHIFT (3U) 2504 /*! MGBUSY - Memory Controller Busy Flag 2505 * 0b0..Memory controller is idle. 2506 * 0b1..Memory controller is busy executing a flash command (CCIF = 0). 2507 */ 2508 #define FTMRE_FSTAT_MGBUSY(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_MGBUSY_SHIFT)) & FTMRE_FSTAT_MGBUSY_MASK) 2509 #define FTMRE_FSTAT_FPVIOL_MASK (0x10U) 2510 #define FTMRE_FSTAT_FPVIOL_SHIFT (4U) 2511 /*! FPVIOL - Flash Protection Violation Flag 2512 * 0b0..No protection violation is detected. 2513 * 0b1..Protection violation is detected. 2514 */ 2515 #define FTMRE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_FPVIOL_SHIFT)) & FTMRE_FSTAT_FPVIOL_MASK) 2516 #define FTMRE_FSTAT_ACCERR_MASK (0x20U) 2517 #define FTMRE_FSTAT_ACCERR_SHIFT (5U) 2518 /*! ACCERR - Flash Access Error Flag 2519 * 0b0..No access error is detected. 2520 * 0b1..Access error is detected. 2521 */ 2522 #define FTMRE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_ACCERR_SHIFT)) & FTMRE_FSTAT_ACCERR_MASK) 2523 #define FTMRE_FSTAT_CCIF_MASK (0x80U) 2524 #define FTMRE_FSTAT_CCIF_SHIFT (7U) 2525 /*! CCIF - Command Complete Interrupt Flag 2526 * 0b0..Flash command is in progress. 2527 * 0b1..Flash command has completed. 2528 */ 2529 #define FTMRE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FSTAT_CCIF_SHIFT)) & FTMRE_FSTAT_CCIF_MASK) 2530 /*! @} */ 2531 2532 /*! @name FCNFG - Flash Configuration Register */ 2533 /*! @{ */ 2534 #define FTMRE_FCNFG_ERSAREQ_MASK (0x20U) 2535 #define FTMRE_FCNFG_ERSAREQ_SHIFT (5U) 2536 /*! ERSAREQ - Debugger Mass Erase Request 2537 * 0b0..No request or request complete 2538 * 0b1..Request to run the Erase All Blocks command verify the erased state program the security byte in the Flash Configuration Field to the unsecure state release MCU security by setting FSEC[SEC] to the unsecure state 2539 */ 2540 #define FTMRE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCNFG_ERSAREQ_SHIFT)) & FTMRE_FCNFG_ERSAREQ_MASK) 2541 #define FTMRE_FCNFG_CCIE_MASK (0x80U) 2542 #define FTMRE_FCNFG_CCIE_SHIFT (7U) 2543 /*! CCIE - Command Complete Interrupt Enable 2544 * 0b0..Command complete interrupt is disabled. 2545 * 0b1..An interrupt will be requested whenever the CCIF flag in the FSTAT register is set. 2546 */ 2547 #define FTMRE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCNFG_CCIE_SHIFT)) & FTMRE_FCNFG_CCIE_MASK) 2548 /*! @} */ 2549 2550 /*! @name FCCOBLO - Flash Common Command Object Register: Low */ 2551 /*! @{ */ 2552 #define FTMRE_FCCOBLO_CCOB_MASK (0xFFU) 2553 #define FTMRE_FCCOBLO_CCOB_SHIFT (0U) 2554 #define FTMRE_FCCOBLO_CCOB(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCCOBLO_CCOB_SHIFT)) & FTMRE_FCCOBLO_CCOB_MASK) 2555 /*! @} */ 2556 2557 /*! @name FCCOBHI - Flash Common Command Object Register:High */ 2558 /*! @{ */ 2559 #define FTMRE_FCCOBHI_CCOB_MASK (0xFFU) 2560 #define FTMRE_FCCOBHI_CCOB_SHIFT (0U) 2561 #define FTMRE_FCCOBHI_CCOB(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FCCOBHI_CCOB_SHIFT)) & FTMRE_FCCOBHI_CCOB_MASK) 2562 /*! @} */ 2563 2564 /*! @name FPROT - Flash Protection Register */ 2565 /*! @{ */ 2566 #define FTMRE_FPROT_FPLS_MASK (0x3U) 2567 #define FTMRE_FPROT_FPLS_SHIFT (0U) 2568 #define FTMRE_FPROT_FPLS(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPLS_SHIFT)) & FTMRE_FPROT_FPLS_MASK) 2569 #define FTMRE_FPROT_FPLDIS_MASK (0x4U) 2570 #define FTMRE_FPROT_FPLDIS_SHIFT (2U) 2571 /*! FPLDIS - Flash Protection Lower Address Range Disable 2572 * 0b0..Protection/Unprotection enabled. 2573 * 0b1..Protection/Unprotection disabled. 2574 */ 2575 #define FTMRE_FPROT_FPLDIS(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPLDIS_SHIFT)) & FTMRE_FPROT_FPLDIS_MASK) 2576 #define FTMRE_FPROT_FPHS_MASK (0x18U) 2577 #define FTMRE_FPROT_FPHS_SHIFT (3U) 2578 #define FTMRE_FPROT_FPHS(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPHS_SHIFT)) & FTMRE_FPROT_FPHS_MASK) 2579 #define FTMRE_FPROT_FPHDIS_MASK (0x20U) 2580 #define FTMRE_FPROT_FPHDIS_SHIFT (5U) 2581 /*! FPHDIS - Flash Protection Higher Address Range Disable 2582 * 0b0..Protection/Unprotection enabled. 2583 * 0b1..Protection/Unprotection disabled. 2584 */ 2585 #define FTMRE_FPROT_FPHDIS(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPHDIS_SHIFT)) & FTMRE_FPROT_FPHDIS_MASK) 2586 #define FTMRE_FPROT_RNV6_MASK (0x40U) 2587 #define FTMRE_FPROT_RNV6_SHIFT (6U) 2588 #define FTMRE_FPROT_RNV6(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_RNV6_SHIFT)) & FTMRE_FPROT_RNV6_MASK) 2589 #define FTMRE_FPROT_FPOPEN_MASK (0x80U) 2590 #define FTMRE_FPROT_FPOPEN_SHIFT (7U) 2591 /*! FPOPEN - Flash Protection Operation Enable 2592 * 0b0..When FPOPEN is clear, the FPHDIS and FPLDIS fields define unprotected address ranges as specified by the corresponding FPHS and FPLS fields. 2593 * 0b1..When FPOPEN is set, the FPHDIS and FPLDIS fields enable protection for the address range specified by the corresponding FPHS and FPLS fields. 2594 */ 2595 #define FTMRE_FPROT_FPOPEN(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FPROT_FPOPEN_SHIFT)) & FTMRE_FPROT_FPOPEN_MASK) 2596 /*! @} */ 2597 2598 /*! @name FOPT - Flash Option Register */ 2599 /*! @{ */ 2600 #define FTMRE_FOPT_NV_MASK (0xFFU) 2601 #define FTMRE_FOPT_NV_SHIFT (0U) 2602 #define FTMRE_FOPT_NV(x) (((uint8_t)(((uint8_t)(x)) << FTMRE_FOPT_NV_SHIFT)) & FTMRE_FOPT_NV_MASK) 2603 /*! @} */ 2604 2605 2606 /*! 2607 * @} 2608 */ /* end of group FTMRE_Register_Masks */ 2609 2610 2611 /* FTMRE - Peripheral instance base addresses */ 2612 /** Peripheral FTMRE base address */ 2613 #define FTMRE_BASE (0x40020000u) 2614 /** Peripheral FTMRE base pointer */ 2615 #define FTMRE ((FTMRE_Type *)FTMRE_BASE) 2616 /** Array initializer of FTMRE peripheral base addresses */ 2617 #define FTMRE_BASE_ADDRS { FTMRE_BASE } 2618 /** Array initializer of FTMRE peripheral base pointers */ 2619 #define FTMRE_BASE_PTRS { FTMRE } 2620 /** Interrupt vectors for the FTMRE peripheral type */ 2621 #define FTMRE_IRQS { FTMRE_IRQn } 2622 2623 /*! 2624 * @} 2625 */ /* end of group FTMRE_Peripheral_Access_Layer */ 2626 2627 2628 /* ---------------------------------------------------------------------------- 2629 -- GPIO Peripheral Access Layer 2630 ---------------------------------------------------------------------------- */ 2631 2632 /*! 2633 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 2634 * @{ 2635 */ 2636 2637 /** GPIO - Register Layout Typedef */ 2638 typedef struct { 2639 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 2640 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ 2641 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ 2642 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ 2643 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 2644 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 2645 __IO uint32_t PIDR; /**< Port Input Disable Register, offset: 0x18 */ 2646 } GPIO_Type; 2647 2648 /* ---------------------------------------------------------------------------- 2649 -- GPIO Register Masks 2650 ---------------------------------------------------------------------------- */ 2651 2652 /*! 2653 * @addtogroup GPIO_Register_Masks GPIO Register Masks 2654 * @{ 2655 */ 2656 2657 /*! @name PDOR - Port Data Output Register */ 2658 /*! @{ */ 2659 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) 2660 #define GPIO_PDOR_PDO_SHIFT (0U) 2661 /*! PDO - Port Data Output 2662 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 2663 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 2664 */ 2665 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 2666 /*! @} */ 2667 2668 /*! @name PSOR - Port Set Output Register */ 2669 /*! @{ */ 2670 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) 2671 #define GPIO_PSOR_PTSO_SHIFT (0U) 2672 /*! PTSO - Port Set Output 2673 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2674 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1. 2675 */ 2676 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) 2677 /*! @} */ 2678 2679 /*! @name PCOR - Port Clear Output Register */ 2680 /*! @{ */ 2681 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) 2682 #define GPIO_PCOR_PTCO_SHIFT (0U) 2683 /*! PTCO - Port Clear Output 2684 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2685 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0. 2686 */ 2687 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) 2688 /*! @} */ 2689 2690 /*! @name PTOR - Port Toggle Output Register */ 2691 /*! @{ */ 2692 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) 2693 #define GPIO_PTOR_PTTO_SHIFT (0U) 2694 /*! PTTO - Port Toggle Output 2695 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change. 2696 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state. 2697 */ 2698 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) 2699 /*! @} */ 2700 2701 /*! @name PDIR - Port Data Input Register */ 2702 /*! @{ */ 2703 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) 2704 #define GPIO_PDIR_PDI_SHIFT (0U) 2705 /*! PDI - Port Data Input 2706 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function. 2707 * 0b00000000000000000000000000000001..Pin logic level is logic 1. 2708 */ 2709 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 2710 /*! @} */ 2711 2712 /*! @name PDDR - Port Data Direction Register */ 2713 /*! @{ */ 2714 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) 2715 #define GPIO_PDDR_PDD_SHIFT (0U) 2716 /*! PDD - Port Data Direction 2717 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function. The pin will be high-Z if the port input is disabled in GPIOx_PIDR register. 2718 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function. 2719 */ 2720 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 2721 /*! @} */ 2722 2723 /*! @name PIDR - Port Input Disable Register */ 2724 /*! @{ */ 2725 #define GPIO_PIDR_PID_MASK (0xFFFFFFFFU) 2726 #define GPIO_PIDR_PID_SHIFT (0U) 2727 /*! PID - Port Input Disable 2728 * 0b00000000000000000000000000000000..Pin is configured for General Purpose Input, provided the pin is configured for any digital function. 2729 * 0b00000000000000000000000000000001..Pin is not configured as General Purpose Input.Corresponding Port Data Input Register bit will read zero. 2730 */ 2731 #define GPIO_PIDR_PID(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIDR_PID_SHIFT)) & GPIO_PIDR_PID_MASK) 2732 /*! @} */ 2733 2734 2735 /*! 2736 * @} 2737 */ /* end of group GPIO_Register_Masks */ 2738 2739 2740 /* GPIO - Peripheral instance base addresses */ 2741 /** Peripheral GPIOA base address */ 2742 #define GPIOA_BASE (0x400FF000u) 2743 /** Peripheral GPIOA base pointer */ 2744 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 2745 /** Peripheral GPIOB base address */ 2746 #define GPIOB_BASE (0x400FF040u) 2747 /** Peripheral GPIOB base pointer */ 2748 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 2749 /** Peripheral GPIOC base address */ 2750 #define GPIOC_BASE (0x400FF080u) 2751 /** Peripheral GPIOC base pointer */ 2752 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 2753 /** Array initializer of GPIO peripheral base addresses */ 2754 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE } 2755 /** Array initializer of GPIO peripheral base pointers */ 2756 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC } 2757 2758 /*! 2759 * @} 2760 */ /* end of group GPIO_Peripheral_Access_Layer */ 2761 2762 2763 /* ---------------------------------------------------------------------------- 2764 -- I2C Peripheral Access Layer 2765 ---------------------------------------------------------------------------- */ 2766 2767 /*! 2768 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 2769 * @{ 2770 */ 2771 2772 /** I2C - Register Layout Typedef */ 2773 typedef struct { 2774 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 2775 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 2776 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 2777 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 2778 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 2779 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 2780 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ 2781 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 2782 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 2783 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 2784 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 2785 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 2786 } I2C_Type; 2787 2788 /* ---------------------------------------------------------------------------- 2789 -- I2C Register Masks 2790 ---------------------------------------------------------------------------- */ 2791 2792 /*! 2793 * @addtogroup I2C_Register_Masks I2C Register Masks 2794 * @{ 2795 */ 2796 2797 /*! @name A1 - I2C Address Register 1 */ 2798 /*! @{ */ 2799 #define I2C_A1_AD_MASK (0xFEU) 2800 #define I2C_A1_AD_SHIFT (1U) 2801 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 2802 /*! @} */ 2803 2804 /*! @name F - I2C Frequency Divider register */ 2805 /*! @{ */ 2806 #define I2C_F_ICR_MASK (0x3FU) 2807 #define I2C_F_ICR_SHIFT (0U) 2808 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 2809 #define I2C_F_MULT_MASK (0xC0U) 2810 #define I2C_F_MULT_SHIFT (6U) 2811 /*! MULT - Multiplier Factor 2812 * 0b00..mul = 1 2813 * 0b01..mul = 2 2814 * 0b10..mul = 4 2815 * 0b11..Reserved 2816 */ 2817 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 2818 /*! @} */ 2819 2820 /*! @name C1 - I2C Control Register 1 */ 2821 /*! @{ */ 2822 #define I2C_C1_WUEN_MASK (0x2U) 2823 #define I2C_C1_WUEN_SHIFT (1U) 2824 /*! WUEN - Wakeup Enable 2825 * 0b0..Normal operation. No interrupt generated when address matching in low power mode. 2826 * 0b1..Enables the wakeup function in low power mode. 2827 */ 2828 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 2829 #define I2C_C1_RSTA_MASK (0x4U) 2830 #define I2C_C1_RSTA_SHIFT (2U) 2831 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 2832 #define I2C_C1_TXAK_MASK (0x8U) 2833 #define I2C_C1_TXAK_SHIFT (3U) 2834 /*! TXAK - Transmit Acknowledge Enable 2835 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set). 2836 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set). 2837 */ 2838 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 2839 #define I2C_C1_TX_MASK (0x10U) 2840 #define I2C_C1_TX_SHIFT (4U) 2841 /*! TX - Transmit Mode Select 2842 * 0b0..Receive 2843 * 0b1..Transmit 2844 */ 2845 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 2846 #define I2C_C1_MST_MASK (0x20U) 2847 #define I2C_C1_MST_SHIFT (5U) 2848 /*! MST - Master Mode Select 2849 * 0b0..Slave mode 2850 * 0b1..Master mode 2851 */ 2852 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 2853 #define I2C_C1_IICIE_MASK (0x40U) 2854 #define I2C_C1_IICIE_SHIFT (6U) 2855 /*! IICIE - I2C Interrupt Enable 2856 * 0b0..Disabled 2857 * 0b1..Enabled 2858 */ 2859 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 2860 #define I2C_C1_IICEN_MASK (0x80U) 2861 #define I2C_C1_IICEN_SHIFT (7U) 2862 /*! IICEN - I2C Enable 2863 * 0b0..Disabled 2864 * 0b1..Enabled 2865 */ 2866 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 2867 /*! @} */ 2868 2869 /*! @name S - I2C Status register */ 2870 /*! @{ */ 2871 #define I2C_S_RXAK_MASK (0x1U) 2872 #define I2C_S_RXAK_SHIFT (0U) 2873 /*! RXAK - Receive Acknowledge 2874 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 2875 * 0b1..No acknowledge signal detected 2876 */ 2877 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 2878 #define I2C_S_IICIF_MASK (0x2U) 2879 #define I2C_S_IICIF_SHIFT (1U) 2880 /*! IICIF - Interrupt Flag 2881 * 0b0..No interrupt pending 2882 * 0b1..Interrupt pending 2883 */ 2884 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 2885 #define I2C_S_SRW_MASK (0x4U) 2886 #define I2C_S_SRW_SHIFT (2U) 2887 /*! SRW - Slave Read/Write 2888 * 0b0..Slave receive, master writing to slave 2889 * 0b1..Slave transmit, master reading from slave 2890 */ 2891 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 2892 #define I2C_S_RAM_MASK (0x8U) 2893 #define I2C_S_RAM_SHIFT (3U) 2894 /*! RAM - Range Address Match 2895 * 0b0..Not addressed 2896 * 0b1..Addressed as a slave 2897 */ 2898 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 2899 #define I2C_S_ARBL_MASK (0x10U) 2900 #define I2C_S_ARBL_SHIFT (4U) 2901 /*! ARBL - Arbitration Lost 2902 * 0b0..Standard bus operation. 2903 * 0b1..Loss of arbitration. 2904 */ 2905 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 2906 #define I2C_S_BUSY_MASK (0x20U) 2907 #define I2C_S_BUSY_SHIFT (5U) 2908 /*! BUSY - Bus Busy 2909 * 0b0..Bus is idle 2910 * 0b1..Bus is busy 2911 */ 2912 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 2913 #define I2C_S_IAAS_MASK (0x40U) 2914 #define I2C_S_IAAS_SHIFT (6U) 2915 /*! IAAS - Addressed As A Slave 2916 * 0b0..Not addressed 2917 * 0b1..Addressed as a slave 2918 */ 2919 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 2920 #define I2C_S_TCF_MASK (0x80U) 2921 #define I2C_S_TCF_SHIFT (7U) 2922 /*! TCF - Transfer Complete Flag 2923 * 0b0..Transfer in progress 2924 * 0b1..Transfer complete 2925 */ 2926 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 2927 /*! @} */ 2928 2929 /*! @name D - I2C Data I/O register */ 2930 /*! @{ */ 2931 #define I2C_D_DATA_MASK (0xFFU) 2932 #define I2C_D_DATA_SHIFT (0U) 2933 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 2934 /*! @} */ 2935 2936 /*! @name C2 - I2C Control Register 2 */ 2937 /*! @{ */ 2938 #define I2C_C2_AD_MASK (0x7U) 2939 #define I2C_C2_AD_SHIFT (0U) 2940 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 2941 #define I2C_C2_RMEN_MASK (0x8U) 2942 #define I2C_C2_RMEN_SHIFT (3U) 2943 /*! RMEN - Range Address Matching Enable 2944 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 2945 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. 2946 */ 2947 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 2948 #define I2C_C2_SBRC_MASK (0x10U) 2949 #define I2C_C2_SBRC_SHIFT (4U) 2950 /*! SBRC - Slave Baud Rate Control 2951 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 2952 * 0b1..Slave baud rate is independent of the master baud rate 2953 */ 2954 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 2955 #define I2C_C2_ADEXT_MASK (0x40U) 2956 #define I2C_C2_ADEXT_SHIFT (6U) 2957 /*! ADEXT - Address Extension 2958 * 0b0..7-bit address scheme 2959 * 0b1..10-bit address scheme 2960 */ 2961 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 2962 #define I2C_C2_GCAEN_MASK (0x80U) 2963 #define I2C_C2_GCAEN_SHIFT (7U) 2964 /*! GCAEN - General Call Address Enable 2965 * 0b0..Disabled 2966 * 0b1..Enabled 2967 */ 2968 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 2969 /*! @} */ 2970 2971 /*! @name FLT - I2C Programmable Input Glitch Filter Register */ 2972 /*! @{ */ 2973 #define I2C_FLT_FLT_MASK (0xFU) 2974 #define I2C_FLT_FLT_SHIFT (0U) 2975 /*! FLT - I2C Programmable Filter Factor 2976 * 0b0000..No filter/bypass 2977 */ 2978 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 2979 #define I2C_FLT_STARTF_MASK (0x10U) 2980 #define I2C_FLT_STARTF_SHIFT (4U) 2981 /*! STARTF - I2C Bus Start Detect Flag 2982 * 0b0..No start happens on I2C bus 2983 * 0b1..Start detected on I2C bus 2984 */ 2985 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 2986 #define I2C_FLT_SSIE_MASK (0x20U) 2987 #define I2C_FLT_SSIE_SHIFT (5U) 2988 /*! SSIE - I2C Bus Stop or Start Interrupt Enable 2989 * 0b0..Stop or start detection interrupt is disabled 2990 * 0b1..Stop or start detection interrupt is enabled 2991 */ 2992 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 2993 #define I2C_FLT_STOPF_MASK (0x40U) 2994 #define I2C_FLT_STOPF_SHIFT (6U) 2995 /*! STOPF - I2C Bus Stop Detect Flag 2996 * 0b0..No stop happens on I2C bus 2997 * 0b1..Stop detected on I2C bus 2998 */ 2999 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 3000 #define I2C_FLT_SHEN_MASK (0x80U) 3001 #define I2C_FLT_SHEN_SHIFT (7U) 3002 /*! SHEN - Stop Hold Enable 3003 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 3004 * 0b1..Stop holdoff is enabled. 3005 */ 3006 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 3007 /*! @} */ 3008 3009 /*! @name RA - I2C Range Address register */ 3010 /*! @{ */ 3011 #define I2C_RA_RAD_MASK (0xFEU) 3012 #define I2C_RA_RAD_SHIFT (1U) 3013 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 3014 /*! @} */ 3015 3016 /*! @name SMB - I2C SMBus Control and Status register */ 3017 /*! @{ */ 3018 #define I2C_SMB_SHTF2IE_MASK (0x1U) 3019 #define I2C_SMB_SHTF2IE_SHIFT (0U) 3020 /*! SHTF2IE - SHTF2 Interrupt Enable 3021 * 0b0..SHTF2 interrupt is disabled 3022 * 0b1..SHTF2 interrupt is enabled 3023 */ 3024 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 3025 #define I2C_SMB_SHTF2_MASK (0x2U) 3026 #define I2C_SMB_SHTF2_SHIFT (1U) 3027 /*! SHTF2 - SCL High Timeout Flag 2 3028 * 0b0..No SCL high and SDA low timeout occurs 3029 * 0b1..SCL high and SDA low timeout occurs 3030 */ 3031 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 3032 #define I2C_SMB_SHTF1_MASK (0x4U) 3033 #define I2C_SMB_SHTF1_SHIFT (2U) 3034 /*! SHTF1 - SCL High Timeout Flag 1 3035 * 0b0..No SCL high and SDA high timeout occurs 3036 * 0b1..SCL high and SDA high timeout occurs 3037 */ 3038 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 3039 #define I2C_SMB_SLTF_MASK (0x8U) 3040 #define I2C_SMB_SLTF_SHIFT (3U) 3041 /*! SLTF - SCL Low Timeout Flag 3042 * 0b0..No low timeout occurs 3043 * 0b1..Low timeout occurs 3044 */ 3045 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 3046 #define I2C_SMB_TCKSEL_MASK (0x10U) 3047 #define I2C_SMB_TCKSEL_SHIFT (4U) 3048 /*! TCKSEL - Timeout Counter Clock Select 3049 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 3050 * 0b1..Timeout counter counts at the frequency of the I2C module clock 3051 */ 3052 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 3053 #define I2C_SMB_SIICAEN_MASK (0x20U) 3054 #define I2C_SMB_SIICAEN_SHIFT (5U) 3055 /*! SIICAEN - Second I2C Address Enable 3056 * 0b0..I2C address register 2 matching is disabled 3057 * 0b1..I2C address register 2 matching is enabled 3058 */ 3059 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 3060 #define I2C_SMB_ALERTEN_MASK (0x40U) 3061 #define I2C_SMB_ALERTEN_SHIFT (6U) 3062 /*! ALERTEN - SMBus Alert Response Address Enable 3063 * 0b0..SMBus alert response address matching is disabled 3064 * 0b1..SMBus alert response address matching is enabled 3065 */ 3066 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 3067 #define I2C_SMB_FACK_MASK (0x80U) 3068 #define I2C_SMB_FACK_SHIFT (7U) 3069 /*! FACK - Fast NACK/ACK Enable 3070 * 0b0..An ACK or NACK is sent on the following receiving data byte 3071 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. 3072 */ 3073 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 3074 /*! @} */ 3075 3076 /*! @name A2 - I2C Address Register 2 */ 3077 /*! @{ */ 3078 #define I2C_A2_SAD_MASK (0xFEU) 3079 #define I2C_A2_SAD_SHIFT (1U) 3080 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 3081 /*! @} */ 3082 3083 /*! @name SLTH - I2C SCL Low Timeout Register High */ 3084 /*! @{ */ 3085 #define I2C_SLTH_SSLT_MASK (0xFFU) 3086 #define I2C_SLTH_SSLT_SHIFT (0U) 3087 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 3088 /*! @} */ 3089 3090 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 3091 /*! @{ */ 3092 #define I2C_SLTL_SSLT_MASK (0xFFU) 3093 #define I2C_SLTL_SSLT_SHIFT (0U) 3094 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 3095 /*! @} */ 3096 3097 3098 /*! 3099 * @} 3100 */ /* end of group I2C_Register_Masks */ 3101 3102 3103 /* I2C - Peripheral instance base addresses */ 3104 /** Peripheral I2C0 base address */ 3105 #define I2C0_BASE (0x40066000u) 3106 /** Peripheral I2C0 base pointer */ 3107 #define I2C0 ((I2C_Type *)I2C0_BASE) 3108 /** Peripheral I2C1 base address */ 3109 #define I2C1_BASE (0x40067000u) 3110 /** Peripheral I2C1 base pointer */ 3111 #define I2C1 ((I2C_Type *)I2C1_BASE) 3112 /** Array initializer of I2C peripheral base addresses */ 3113 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } 3114 /** Array initializer of I2C peripheral base pointers */ 3115 #define I2C_BASE_PTRS { I2C0, I2C1 } 3116 /** Interrupt vectors for the I2C peripheral type */ 3117 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } 3118 3119 /*! 3120 * @} 3121 */ /* end of group I2C_Peripheral_Access_Layer */ 3122 3123 3124 /* ---------------------------------------------------------------------------- 3125 -- ICS Peripheral Access Layer 3126 ---------------------------------------------------------------------------- */ 3127 3128 /*! 3129 * @addtogroup ICS_Peripheral_Access_Layer ICS Peripheral Access Layer 3130 * @{ 3131 */ 3132 3133 /** ICS - Register Layout Typedef */ 3134 typedef struct { 3135 __IO uint8_t C1; /**< ICS Control Register 1, offset: 0x0 */ 3136 __IO uint8_t C2; /**< ICS Control Register 2, offset: 0x1 */ 3137 __IO uint8_t C3; /**< ICS Control Register 3, offset: 0x2 */ 3138 __IO uint8_t C4; /**< ICS Control Register 4, offset: 0x3 */ 3139 __IO uint8_t S; /**< ICS Status Register, offset: 0x4 */ 3140 } ICS_Type; 3141 3142 /* ---------------------------------------------------------------------------- 3143 -- ICS Register Masks 3144 ---------------------------------------------------------------------------- */ 3145 3146 /*! 3147 * @addtogroup ICS_Register_Masks ICS Register Masks 3148 * @{ 3149 */ 3150 3151 /*! @name C1 - ICS Control Register 1 */ 3152 /*! @{ */ 3153 #define ICS_C1_IREFSTEN_MASK (0x1U) 3154 #define ICS_C1_IREFSTEN_SHIFT (0U) 3155 /*! IREFSTEN - Internal Reference Stop Enable 3156 * 0b0..Internal reference clock is disabled in Stop mode. 3157 * 0b1..Internal reference clock stays enabled in Stop mode if IRCLKEN is set, or if ICS is in FEI, FBI, or FBILP mode before entering Stop. 3158 */ 3159 #define ICS_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IREFSTEN_SHIFT)) & ICS_C1_IREFSTEN_MASK) 3160 #define ICS_C1_IRCLKEN_MASK (0x2U) 3161 #define ICS_C1_IRCLKEN_SHIFT (1U) 3162 /*! IRCLKEN - Internal Reference Clock Enable 3163 * 0b0..ICSIRCLK is inactive. 3164 * 0b1..ICSIRCLK is active. 3165 */ 3166 #define ICS_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IRCLKEN_SHIFT)) & ICS_C1_IRCLKEN_MASK) 3167 #define ICS_C1_IREFS_MASK (0x4U) 3168 #define ICS_C1_IREFS_SHIFT (2U) 3169 /*! IREFS - Internal Reference Select 3170 * 0b0..External reference clock is selected. 3171 * 0b1..Internal reference clock is selected. 3172 */ 3173 #define ICS_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_IREFS_SHIFT)) & ICS_C1_IREFS_MASK) 3174 #define ICS_C1_RDIV_MASK (0x38U) 3175 #define ICS_C1_RDIV_SHIFT (3U) 3176 #define ICS_C1_RDIV(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_RDIV_SHIFT)) & ICS_C1_RDIV_MASK) 3177 #define ICS_C1_CLKS_MASK (0xC0U) 3178 #define ICS_C1_CLKS_SHIFT (6U) 3179 /*! CLKS - Clock Source Select 3180 * 0b00..Output of FLL is selected. 3181 * 0b01..Internal reference clock is selected. 3182 * 0b10..External reference clock is selected. 3183 * 0b11..Reserved, defaults to 00. 3184 */ 3185 #define ICS_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << ICS_C1_CLKS_SHIFT)) & ICS_C1_CLKS_MASK) 3186 /*! @} */ 3187 3188 /*! @name C2 - ICS Control Register 2 */ 3189 /*! @{ */ 3190 #define ICS_C2_LP_MASK (0x10U) 3191 #define ICS_C2_LP_SHIFT (4U) 3192 /*! LP - Low Power Select 3193 * 0b0..FLL is not disabled in bypass mode. 3194 * 0b1..FLL is disabled in bypass modes unless debug is active. 3195 */ 3196 #define ICS_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << ICS_C2_LP_SHIFT)) & ICS_C2_LP_MASK) 3197 #define ICS_C2_BDIV_MASK (0xE0U) 3198 #define ICS_C2_BDIV_SHIFT (5U) 3199 /*! BDIV - Bus Frequency Divider 3200 * 0b000..Encoding 0-Divides the selected clock by 1. 3201 * 0b001..Encoding 1-Divides the selected clock by 2 (reset default). 3202 * 0b010..Encoding 2-Divides the selected clock by 4. 3203 * 0b011..Encoding 3-Divides the selected clock by 8. 3204 * 0b100..Encoding 4-Divides the selected clock by 16. 3205 * 0b101..Encoding 5-Divides the selected clock by 32. 3206 * 0b110..Encoding 6-Divides the selected clock by 64. 3207 * 0b111..Encoding 7-Divides the selected clock by 128. 3208 */ 3209 #define ICS_C2_BDIV(x) (((uint8_t)(((uint8_t)(x)) << ICS_C2_BDIV_SHIFT)) & ICS_C2_BDIV_MASK) 3210 /*! @} */ 3211 3212 /*! @name C3 - ICS Control Register 3 */ 3213 /*! @{ */ 3214 #define ICS_C3_SCTRIM_MASK (0xFFU) 3215 #define ICS_C3_SCTRIM_SHIFT (0U) 3216 #define ICS_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << ICS_C3_SCTRIM_SHIFT)) & ICS_C3_SCTRIM_MASK) 3217 /*! @} */ 3218 3219 /*! @name C4 - ICS Control Register 4 */ 3220 /*! @{ */ 3221 #define ICS_C4_SCFTRIM_MASK (0x1U) 3222 #define ICS_C4_SCFTRIM_SHIFT (0U) 3223 #define ICS_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_SCFTRIM_SHIFT)) & ICS_C4_SCFTRIM_MASK) 3224 #define ICS_C4_CME_MASK (0x20U) 3225 #define ICS_C4_CME_SHIFT (5U) 3226 /*! CME - Clock Monitor Enable 3227 * 0b0..Clock monitor is disabled. 3228 * 0b1..Generates a reset request on loss of external clock. 3229 */ 3230 #define ICS_C4_CME(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_CME_SHIFT)) & ICS_C4_CME_MASK) 3231 #define ICS_C4_LOLIE_MASK (0x80U) 3232 #define ICS_C4_LOLIE_SHIFT (7U) 3233 /*! LOLIE - Loss of Lock Interrupt 3234 * 0b0..No request on loss of lock. 3235 * 0b1..Generates an interrupt request on loss of lock. 3236 */ 3237 #define ICS_C4_LOLIE(x) (((uint8_t)(((uint8_t)(x)) << ICS_C4_LOLIE_SHIFT)) & ICS_C4_LOLIE_MASK) 3238 /*! @} */ 3239 3240 /*! @name S - ICS Status Register */ 3241 /*! @{ */ 3242 #define ICS_S_CLKST_MASK (0xCU) 3243 #define ICS_S_CLKST_SHIFT (2U) 3244 /*! CLKST - Clock Mode Status 3245 * 0b00..Output of FLL is selected. 3246 * 0b01..FLL Bypassed, internal reference clock is selected. 3247 * 0b10..FLL Bypassed, external reference clock is selected. 3248 * 0b11..Reserved. 3249 */ 3250 #define ICS_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_CLKST_SHIFT)) & ICS_S_CLKST_MASK) 3251 #define ICS_S_IREFST_MASK (0x10U) 3252 #define ICS_S_IREFST_SHIFT (4U) 3253 /*! IREFST - Internal Reference Status 3254 * 0b0..Source of reference clock is external clock. 3255 * 0b1..Source of reference clock is internal clock. 3256 */ 3257 #define ICS_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_IREFST_SHIFT)) & ICS_S_IREFST_MASK) 3258 #define ICS_S_LOCK_MASK (0x40U) 3259 #define ICS_S_LOCK_SHIFT (6U) 3260 /*! LOCK - Lock Status 3261 * 0b0..FLL is currently unlocked. 3262 * 0b1..FLL is currently locked. 3263 */ 3264 #define ICS_S_LOCK(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_LOCK_SHIFT)) & ICS_S_LOCK_MASK) 3265 #define ICS_S_LOLS_MASK (0x80U) 3266 #define ICS_S_LOLS_SHIFT (7U) 3267 /*! LOLS - Loss of Lock Status 3268 * 0b0..FLL has not lost lock since LOLS was last cleared. 3269 * 0b1..FLL has lost lock since LOLS was last cleared. 3270 */ 3271 #define ICS_S_LOLS(x) (((uint8_t)(((uint8_t)(x)) << ICS_S_LOLS_SHIFT)) & ICS_S_LOLS_MASK) 3272 /*! @} */ 3273 3274 3275 /*! 3276 * @} 3277 */ /* end of group ICS_Register_Masks */ 3278 3279 3280 /* ICS - Peripheral instance base addresses */ 3281 /** Peripheral ICS base address */ 3282 #define ICS_BASE (0x40064000u) 3283 /** Peripheral ICS base pointer */ 3284 #define ICS ((ICS_Type *)ICS_BASE) 3285 /** Array initializer of ICS peripheral base addresses */ 3286 #define ICS_BASE_ADDRS { ICS_BASE } 3287 /** Array initializer of ICS peripheral base pointers */ 3288 #define ICS_BASE_PTRS { ICS } 3289 /** Interrupt vectors for the ICS peripheral type */ 3290 #define ICS_IRQS { ICS_IRQn } 3291 3292 /*! 3293 * @} 3294 */ /* end of group ICS_Peripheral_Access_Layer */ 3295 3296 3297 /* ---------------------------------------------------------------------------- 3298 -- IRQ Peripheral Access Layer 3299 ---------------------------------------------------------------------------- */ 3300 3301 /*! 3302 * @addtogroup IRQ_Peripheral_Access_Layer IRQ Peripheral Access Layer 3303 * @{ 3304 */ 3305 3306 /** IRQ - Register Layout Typedef */ 3307 typedef struct { 3308 __IO uint8_t SC; /**< Interrupt Pin Request Status and Control Register, offset: 0x0 */ 3309 } IRQ_Type; 3310 3311 /* ---------------------------------------------------------------------------- 3312 -- IRQ Register Masks 3313 ---------------------------------------------------------------------------- */ 3314 3315 /*! 3316 * @addtogroup IRQ_Register_Masks IRQ Register Masks 3317 * @{ 3318 */ 3319 3320 /*! @name SC - Interrupt Pin Request Status and Control Register */ 3321 /*! @{ */ 3322 #define IRQ_SC_IRQMOD_MASK (0x1U) 3323 #define IRQ_SC_IRQMOD_SHIFT (0U) 3324 /*! IRQMOD - IRQ Detection Mode 3325 * 0b0..IRQ event is detected only on falling/rising edges. 3326 * 0b1..IRQ event is detected on falling/rising edges and low/high levels. 3327 */ 3328 #define IRQ_SC_IRQMOD(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQMOD_SHIFT)) & IRQ_SC_IRQMOD_MASK) 3329 #define IRQ_SC_IRQIE_MASK (0x2U) 3330 #define IRQ_SC_IRQIE_SHIFT (1U) 3331 /*! IRQIE - IRQ Interrupt Enable 3332 * 0b0..Interrupt request when IRQF set is disabled (use polling). 3333 * 0b1..Interrupt requested whenever IRQF = 1. 3334 */ 3335 #define IRQ_SC_IRQIE(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQIE_SHIFT)) & IRQ_SC_IRQIE_MASK) 3336 #define IRQ_SC_IRQACK_MASK (0x4U) 3337 #define IRQ_SC_IRQACK_SHIFT (2U) 3338 #define IRQ_SC_IRQACK(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQACK_SHIFT)) & IRQ_SC_IRQACK_MASK) 3339 #define IRQ_SC_IRQF_MASK (0x8U) 3340 #define IRQ_SC_IRQF_SHIFT (3U) 3341 /*! IRQF - IRQ Flag 3342 * 0b0..No IRQ request 3343 * 0b1..IRQ event is detected. 3344 */ 3345 #define IRQ_SC_IRQF(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQF_SHIFT)) & IRQ_SC_IRQF_MASK) 3346 #define IRQ_SC_IRQPE_MASK (0x10U) 3347 #define IRQ_SC_IRQPE_SHIFT (4U) 3348 /*! IRQPE - IRQ Pin Enable 3349 * 0b0..IRQ pin function is disabled. 3350 * 0b1..IRQ pin function is enabled. 3351 */ 3352 #define IRQ_SC_IRQPE(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQPE_SHIFT)) & IRQ_SC_IRQPE_MASK) 3353 #define IRQ_SC_IRQEDG_MASK (0x20U) 3354 #define IRQ_SC_IRQEDG_SHIFT (5U) 3355 /*! IRQEDG - Interrupt Request (IRQ) Edge Select 3356 * 0b0..IRQ is falling-edge or falling-edge/low-level sensitive. 3357 * 0b1..IRQ is rising-edge or rising-edge/high-level sensitive. 3358 */ 3359 #define IRQ_SC_IRQEDG(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQEDG_SHIFT)) & IRQ_SC_IRQEDG_MASK) 3360 #define IRQ_SC_IRQPDD_MASK (0x40U) 3361 #define IRQ_SC_IRQPDD_SHIFT (6U) 3362 /*! IRQPDD - Interrupt Request (IRQ) Pull Device Disable 3363 * 0b0..IRQ pull device enabled if IRQPE = 1. 3364 * 0b1..IRQ pull device disabled if IRQPE = 1. 3365 */ 3366 #define IRQ_SC_IRQPDD(x) (((uint8_t)(((uint8_t)(x)) << IRQ_SC_IRQPDD_SHIFT)) & IRQ_SC_IRQPDD_MASK) 3367 /*! @} */ 3368 3369 3370 /*! 3371 * @} 3372 */ /* end of group IRQ_Register_Masks */ 3373 3374 3375 /* IRQ - Peripheral instance base addresses */ 3376 /** Peripheral IRQ base address */ 3377 #define IRQ_BASE (0x40031000u) 3378 /** Peripheral IRQ base pointer */ 3379 #define IRQ ((IRQ_Type *)IRQ_BASE) 3380 /** Array initializer of IRQ peripheral base addresses */ 3381 #define IRQ_BASE_ADDRS { IRQ_BASE } 3382 /** Array initializer of IRQ peripheral base pointers */ 3383 #define IRQ_BASE_PTRS { IRQ } 3384 3385 /*! 3386 * @} 3387 */ /* end of group IRQ_Peripheral_Access_Layer */ 3388 3389 3390 /* ---------------------------------------------------------------------------- 3391 -- KBI Peripheral Access Layer 3392 ---------------------------------------------------------------------------- */ 3393 3394 /*! 3395 * @addtogroup KBI_Peripheral_Access_Layer KBI Peripheral Access Layer 3396 * @{ 3397 */ 3398 3399 /** KBI - Register Layout Typedef */ 3400 typedef struct { 3401 __IO uint32_t PE; /**< KBI Pin Enable Register, offset: 0x0 */ 3402 __IO uint32_t ES; /**< KBI Edge Select Register, offset: 0x4 */ 3403 __IO uint32_t SC; /**< KBI Status and Control Register, offset: 0x8 */ 3404 __I uint32_t SP; /**< KBI Source Pin Register, offset: 0xC */ 3405 } KBI_Type; 3406 3407 /* ---------------------------------------------------------------------------- 3408 -- KBI Register Masks 3409 ---------------------------------------------------------------------------- */ 3410 3411 /*! 3412 * @addtogroup KBI_Register_Masks KBI Register Masks 3413 * @{ 3414 */ 3415 3416 /*! @name PE - KBI Pin Enable Register */ 3417 /*! @{ */ 3418 #define KBI_PE_KBIPE_MASK (0xFFFFFFFFU) 3419 #define KBI_PE_KBIPE_SHIFT (0U) 3420 /*! KBIPE - KBI Pin Enables 3421 * 0b00000000000000000000000000000000..Pin is not enabled as KBI interrupt. 3422 * 0b00000000000000000000000000000001..Pin is enabled as KBI interrupt. 3423 */ 3424 #define KBI_PE_KBIPE(x) (((uint32_t)(((uint32_t)(x)) << KBI_PE_KBIPE_SHIFT)) & KBI_PE_KBIPE_MASK) 3425 /*! @} */ 3426 3427 /*! @name ES - KBI Edge Select Register */ 3428 /*! @{ */ 3429 #define KBI_ES_KBEDG_MASK (0xFFFFFFFFU) 3430 #define KBI_ES_KBEDG_SHIFT (0U) 3431 /*! KBEDG - KBI Edge Selects 3432 * 0b00000000000000000000000000000000..Falling edge/low level. 3433 * 0b00000000000000000000000000000001..Rising edge/high level. 3434 */ 3435 #define KBI_ES_KBEDG(x) (((uint32_t)(((uint32_t)(x)) << KBI_ES_KBEDG_SHIFT)) & KBI_ES_KBEDG_MASK) 3436 /*! @} */ 3437 3438 /*! @name SC - KBI Status and Control Register */ 3439 /*! @{ */ 3440 #define KBI_SC_KBMOD_MASK (0x1U) 3441 #define KBI_SC_KBMOD_SHIFT (0U) 3442 /*! KBMOD - KBI Detection Mode 3443 * 0b0..Keyboard detects edges only. 3444 * 0b1..Keyboard detects both edges and levels. 3445 */ 3446 #define KBI_SC_KBMOD(x) (((uint32_t)(((uint32_t)(x)) << KBI_SC_KBMOD_SHIFT)) & KBI_SC_KBMOD_MASK) 3447 #define KBI_SC_KBIE_MASK (0x2U) 3448 #define KBI_SC_KBIE_SHIFT (1U) 3449 /*! KBIE - KBI Interrupt Enable 3450 * 0b0..KBI interrupt not enabled. 3451 * 0b1..KBI interrupt enabled. 3452 */ 3453 #define KBI_SC_KBIE(x) (((uint32_t)(((uint32_t)(x)) << KBI_SC_KBIE_SHIFT)) & KBI_SC_KBIE_MASK) 3454 #define KBI_SC_KBACK_MASK (0x4U) 3455 #define KBI_SC_KBACK_SHIFT (2U) 3456 #define KBI_SC_KBACK(x) (((uint32_t)(((uint32_t)(x)) << KBI_SC_KBACK_SHIFT)) & KBI_SC_KBACK_MASK) 3457 #define KBI_SC_KBF_MASK (0x8U) 3458 #define KBI_SC_KBF_SHIFT (3U) 3459 /*! KBF - KBI Interrupt Flag 3460 * 0b0..KBI interrupt request not detected. 3461 * 0b1..KBI interrupt request detected. 3462 */ 3463 #define KBI_SC_KBF(x) (((uint32_t)(((uint32_t)(x)) << KBI_SC_KBF_SHIFT)) & KBI_SC_KBF_MASK) 3464 #define KBI_SC_KBSPEN_MASK (0x10U) 3465 #define KBI_SC_KBSPEN_SHIFT (4U) 3466 /*! KBSPEN - Real KBI_SP register enable 3467 * 0b0..The real time value of Keyboard source pin to be read. 3468 * 0b1..The latched value in KBxSP register while interrupt flag occur to be read. 3469 */ 3470 #define KBI_SC_KBSPEN(x) (((uint32_t)(((uint32_t)(x)) << KBI_SC_KBSPEN_SHIFT)) & KBI_SC_KBSPEN_MASK) 3471 #define KBI_SC_RSTKBSP_MASK (0x20U) 3472 #define KBI_SC_RSTKBSP_SHIFT (5U) 3473 #define KBI_SC_RSTKBSP(x) (((uint32_t)(((uint32_t)(x)) << KBI_SC_RSTKBSP_SHIFT)) & KBI_SC_RSTKBSP_MASK) 3474 /*! @} */ 3475 3476 /*! @name SP - KBI Source Pin Register */ 3477 /*! @{ */ 3478 #define KBI_SP_SP_MASK (0xFFFFFFFFU) 3479 #define KBI_SP_SP_SHIFT (0U) 3480 #define KBI_SP_SP(x) (((uint32_t)(((uint32_t)(x)) << KBI_SP_SP_SHIFT)) & KBI_SP_SP_MASK) 3481 /*! @} */ 3482 3483 3484 /*! 3485 * @} 3486 */ /* end of group KBI_Register_Masks */ 3487 3488 3489 /* KBI - Peripheral instance base addresses */ 3490 /** Peripheral KBI0 base address */ 3491 #define KBI0_BASE (0x40079000u) 3492 /** Peripheral KBI0 base pointer */ 3493 #define KBI0 ((KBI_Type *)KBI0_BASE) 3494 /** Peripheral KBI1 base address */ 3495 #define KBI1_BASE (0x4007A000u) 3496 /** Peripheral KBI1 base pointer */ 3497 #define KBI1 ((KBI_Type *)KBI1_BASE) 3498 /** Array initializer of KBI peripheral base addresses */ 3499 #define KBI_BASE_ADDRS { KBI0_BASE, KBI1_BASE } 3500 /** Array initializer of KBI peripheral base pointers */ 3501 #define KBI_BASE_PTRS { KBI0, KBI1 } 3502 /** Interrupt vectors for the KBI peripheral type */ 3503 #define KBI_IRQS { KBI0_IRQn, KBI1_IRQn } 3504 3505 /*! 3506 * @} 3507 */ /* end of group KBI_Peripheral_Access_Layer */ 3508 3509 3510 /* ---------------------------------------------------------------------------- 3511 -- MCM Peripheral Access Layer 3512 ---------------------------------------------------------------------------- */ 3513 3514 /*! 3515 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 3516 * @{ 3517 */ 3518 3519 /** MCM - Register Layout Typedef */ 3520 typedef struct { 3521 uint8_t RESERVED_0[8]; 3522 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 3523 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 3524 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 3525 } MCM_Type; 3526 3527 /* ---------------------------------------------------------------------------- 3528 -- MCM Register Masks 3529 ---------------------------------------------------------------------------- */ 3530 3531 /*! 3532 * @addtogroup MCM_Register_Masks MCM Register Masks 3533 * @{ 3534 */ 3535 3536 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 3537 /*! @{ */ 3538 #define MCM_PLASC_ASC_MASK (0xFFU) 3539 #define MCM_PLASC_ASC_SHIFT (0U) 3540 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 3541 * 0b00000000..A bus slave connection to AXBS input port n is absent. 3542 * 0b00000001..A bus slave connection to AXBS input port n is present. 3543 */ 3544 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 3545 /*! @} */ 3546 3547 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 3548 /*! @{ */ 3549 #define MCM_PLAMC_AMC_MASK (0xFFU) 3550 #define MCM_PLAMC_AMC_SHIFT (0U) 3551 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 3552 * 0b00000000..A bus master connection to AXBS input port n is absent 3553 * 0b00000001..A bus master connection to AXBS input port n is present 3554 */ 3555 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 3556 /*! @} */ 3557 3558 /*! @name PLACR - Platform Control Register */ 3559 /*! @{ */ 3560 #define MCM_PLACR_CFCC_MASK (0x400U) 3561 #define MCM_PLACR_CFCC_SHIFT (10U) 3562 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 3563 #define MCM_PLACR_DFCDA_MASK (0x800U) 3564 #define MCM_PLACR_DFCDA_SHIFT (11U) 3565 /*! DFCDA - Disable Flash Controller Data Caching 3566 * 0b0..Enable flash controller data caching 3567 * 0b1..Disable flash controller data caching. 3568 */ 3569 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 3570 #define MCM_PLACR_DFCIC_MASK (0x1000U) 3571 #define MCM_PLACR_DFCIC_SHIFT (12U) 3572 /*! DFCIC - Disable Flash Controller Instruction Caching 3573 * 0b0..Enable flash controller instruction caching. 3574 * 0b1..Disable flash controller instruction caching. 3575 */ 3576 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 3577 #define MCM_PLACR_DFCC_MASK (0x2000U) 3578 #define MCM_PLACR_DFCC_SHIFT (13U) 3579 /*! DFCC - Disable Flash Controller Cache 3580 * 0b0..Enable flash controller cache. 3581 * 0b1..Disable flash controller cache. 3582 */ 3583 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 3584 #define MCM_PLACR_EFDS_MASK (0x4000U) 3585 #define MCM_PLACR_EFDS_SHIFT (14U) 3586 /*! EFDS - Enable Flash Data Speculation 3587 * 0b0..Disable flash data speculation. 3588 * 0b1..Enable flash data speculation. 3589 */ 3590 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 3591 #define MCM_PLACR_DFCS_MASK (0x8000U) 3592 #define MCM_PLACR_DFCS_SHIFT (15U) 3593 /*! DFCS - Disable Flash Controller Speculation 3594 * 0b0..Enable flash controller speculation. 3595 * 0b1..Disable flash controller speculation. 3596 */ 3597 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 3598 #define MCM_PLACR_ESFC_MASK (0x10000U) 3599 #define MCM_PLACR_ESFC_SHIFT (16U) 3600 /*! ESFC - Enable Stalling Flash Controller 3601 * 0b0..Disable stalling flash controller when flash is busy. 3602 * 0b1..Enable stalling flash controller when flash is busy. 3603 */ 3604 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 3605 /*! @} */ 3606 3607 3608 /*! 3609 * @} 3610 */ /* end of group MCM_Register_Masks */ 3611 3612 3613 /* MCM - Peripheral instance base addresses */ 3614 /** Peripheral MCM base address */ 3615 #define MCM_BASE (0xF0003000u) 3616 /** Peripheral MCM base pointer */ 3617 #define MCM ((MCM_Type *)MCM_BASE) 3618 /** Array initializer of MCM peripheral base addresses */ 3619 #define MCM_BASE_ADDRS { MCM_BASE } 3620 /** Array initializer of MCM peripheral base pointers */ 3621 #define MCM_BASE_PTRS { MCM } 3622 3623 /*! 3624 * @} 3625 */ /* end of group MCM_Peripheral_Access_Layer */ 3626 3627 3628 /* ---------------------------------------------------------------------------- 3629 -- MSCAN Peripheral Access Layer 3630 ---------------------------------------------------------------------------- */ 3631 3632 /*! 3633 * @addtogroup MSCAN_Peripheral_Access_Layer MSCAN Peripheral Access Layer 3634 * @{ 3635 */ 3636 3637 /** MSCAN - Register Layout Typedef */ 3638 typedef struct { 3639 __IO uint8_t CANCTL0; /**< MSCAN Control Register 0, offset: 0x0 */ 3640 __IO uint8_t CANCTL1; /**< MSCAN Control Register 1, offset: 0x1 */ 3641 __IO uint8_t CANBTR0; /**< MSCAN Bus Timing Register 0, offset: 0x2 */ 3642 __IO uint8_t CANBTR1; /**< MSCAN Bus Timing Register 1, offset: 0x3 */ 3643 __IO uint8_t CANRFLG; /**< MSCAN Receiver Flag Register, offset: 0x4 */ 3644 __IO uint8_t CANRIER; /**< MSCAN Receiver Interrupt Enable Register, offset: 0x5 */ 3645 __IO uint8_t CANTFLG; /**< MSCAN Transmitter Flag Register, offset: 0x6 */ 3646 __IO uint8_t CANTIER; /**< MSCAN Transmitter Interrupt Enable Register, offset: 0x7 */ 3647 __IO uint8_t CANTARQ; /**< MSCAN Transmitter Message Abort Request Register, offset: 0x8 */ 3648 __I uint8_t CANTAAK; /**< MSCAN Transmitter Message Abort Acknowledge Register, offset: 0x9 */ 3649 __IO uint8_t CANTBSEL; /**< MSCAN Transmit Buffer Selection Register, offset: 0xA */ 3650 __IO uint8_t CANIDAC; /**< MSCAN Identifier Acceptance Control Register, offset: 0xB */ 3651 uint8_t RESERVED_0[1]; 3652 __IO uint8_t CANMISC; /**< MSCAN Miscellaneous Register, offset: 0xD */ 3653 __I uint8_t CANRXERR; /**< MSCAN Receive Error Counter, offset: 0xE */ 3654 __I uint8_t CANTXERR; /**< MSCAN Transmit Error Counter, offset: 0xF */ 3655 __IO uint8_t CANIDAR_BANK_1[4]; /**< MSCAN Identifier Acceptance Register n of First Bank, array offset: 0x10, array step: 0x1 */ 3656 __IO uint8_t CANIDMR_BANK_1[4]; /**< MSCAN Identifier Mask Register n of First Bank, array offset: 0x14, array step: 0x1 */ 3657 __IO uint8_t CANIDAR_BANK_2[4]; /**< MSCAN Identifier Acceptance Register n of Second Bank, array offset: 0x18, array step: 0x1 */ 3658 __IO uint8_t CANIDMR_BANK_2[4]; /**< MSCAN Identifier Mask Register n of Second Bank, array offset: 0x1C, array step: 0x1 */ 3659 union { /* offset: 0x20 */ 3660 __I uint8_t REIDR0; /**< Receive Extended Identifier Register 0, offset: 0x20 */ 3661 __I uint8_t RSIDR0; /**< Receive Standard Identifier Register 0, offset: 0x20 */ 3662 }; 3663 union { /* offset: 0x21 */ 3664 __I uint8_t REIDR1; /**< Receive Extended Identifier Register 1, offset: 0x21 */ 3665 __I uint8_t RSIDR1; /**< Receive Standard Identifier Register 1, offset: 0x21 */ 3666 }; 3667 __I uint8_t REIDR2; /**< Receive Extended Identifier Register 2, offset: 0x22 */ 3668 __I uint8_t REIDR3; /**< Receive Extended Identifier Register 3, offset: 0x23 */ 3669 __I uint8_t REDSR[8]; /**< Receive Extended Data Segment Register N, array offset: 0x24, array step: 0x1 */ 3670 __I uint8_t RDLR; /**< Receive Data Length Register, offset: 0x2C */ 3671 uint8_t RESERVED_1[1]; 3672 __I uint8_t RTSRH; /**< Receive Time Stamp Register High, offset: 0x2E */ 3673 __I uint8_t RTSRL; /**< Receive Time Stamp Register Low, offset: 0x2F */ 3674 union { /* offset: 0x30 */ 3675 __IO uint8_t TEIDR0; /**< Transmit Extended Identifier Register 0, offset: 0x30 */ 3676 __IO uint8_t TSIDR0; /**< Transmit Standard Identifier Register 0, offset: 0x30 */ 3677 }; 3678 union { /* offset: 0x31 */ 3679 __IO uint8_t TEIDR1; /**< Transmit Extended Identifier Register 1, offset: 0x31 */ 3680 __IO uint8_t TSIDR1; /**< Transmit Standard Identifier Register 1, offset: 0x31 */ 3681 }; 3682 __IO uint8_t TEIDR2; /**< Transmit Extended Identifier Register 2, offset: 0x32 */ 3683 __IO uint8_t TEIDR3; /**< Transmit Extended Identifier Register 3, offset: 0x33 */ 3684 __IO uint8_t TEDSR[8]; /**< Transmit Extended Data Segment Register N, array offset: 0x34, array step: 0x1 */ 3685 __IO uint8_t TDLR; /**< Transmit Data Length Register, offset: 0x3C */ 3686 __IO uint8_t TBPR; /**< Transmit Buffer Priority Register, offset: 0x3D */ 3687 __I uint8_t TTSRH; /**< Transmit Time Stamp Register High, offset: 0x3E */ 3688 __I uint8_t TTSRL; /**< Transmit Time Stamp Register Low, offset: 0x3F */ 3689 } MSCAN_Type; 3690 3691 /* ---------------------------------------------------------------------------- 3692 -- MSCAN Register Masks 3693 ---------------------------------------------------------------------------- */ 3694 3695 /*! 3696 * @addtogroup MSCAN_Register_Masks MSCAN Register Masks 3697 * @{ 3698 */ 3699 3700 /*! @name CANCTL0 - MSCAN Control Register 0 */ 3701 /*! @{ */ 3702 #define MSCAN_CANCTL0_INITRQ_MASK (0x1U) 3703 #define MSCAN_CANCTL0_INITRQ_SHIFT (0U) 3704 /*! INITRQ - Initialization Mode Request 3705 * 0b0..Normal operation. 3706 * 0b1..MSCAN in initialization mode. 3707 */ 3708 #define MSCAN_CANCTL0_INITRQ(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_INITRQ_SHIFT)) & MSCAN_CANCTL0_INITRQ_MASK) 3709 #define MSCAN_CANCTL0_SLPRQ_MASK (0x2U) 3710 #define MSCAN_CANCTL0_SLPRQ_SHIFT (1U) 3711 /*! SLPRQ - Sleep Mode Request 3712 * 0b0..Running - The MSCAN functions normally. 3713 * 0b1..Sleep mode request - The MSCAN enters sleep mode when CAN bus idle. 3714 */ 3715 #define MSCAN_CANCTL0_SLPRQ(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_SLPRQ_SHIFT)) & MSCAN_CANCTL0_SLPRQ_MASK) 3716 #define MSCAN_CANCTL0_WUPE_MASK (0x4U) 3717 #define MSCAN_CANCTL0_WUPE_SHIFT (2U) 3718 /*! WUPE - WakeUp Enable 3719 * 0b0..Wakeup disabled - The MSCAN ignores traffic on CAN. 3720 * 0b1..Wakeup enabled - The MSCAN is able to restart. 3721 */ 3722 #define MSCAN_CANCTL0_WUPE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_WUPE_SHIFT)) & MSCAN_CANCTL0_WUPE_MASK) 3723 #define MSCAN_CANCTL0_TIME_MASK (0x8U) 3724 #define MSCAN_CANCTL0_TIME_SHIFT (3U) 3725 /*! TIME - Timer Enable 3726 * 0b0..Disable internal MSCAN timer. 3727 * 0b1..Enable internal MSCAN timer. 3728 */ 3729 #define MSCAN_CANCTL0_TIME(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_TIME_SHIFT)) & MSCAN_CANCTL0_TIME_MASK) 3730 #define MSCAN_CANCTL0_SYNCH_MASK (0x10U) 3731 #define MSCAN_CANCTL0_SYNCH_SHIFT (4U) 3732 /*! SYNCH - Synchronized Status 3733 * 0b0..MSCAN is not synchronized to the CAN bus. 3734 * 0b1..MSCAN is synchronized to the CAN bus. 3735 */ 3736 #define MSCAN_CANCTL0_SYNCH(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_SYNCH_SHIFT)) & MSCAN_CANCTL0_SYNCH_MASK) 3737 #define MSCAN_CANCTL0_CSWAI_MASK (0x20U) 3738 #define MSCAN_CANCTL0_CSWAI_SHIFT (5U) 3739 /*! CSWAI - CAN Stops in Wait Mode 3740 * 0b0..The module is not affected during wait mode. 3741 * 0b1..The module ceases to be clocked during wait mode. 3742 */ 3743 #define MSCAN_CANCTL0_CSWAI(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_CSWAI_SHIFT)) & MSCAN_CANCTL0_CSWAI_MASK) 3744 #define MSCAN_CANCTL0_RXACT_MASK (0x40U) 3745 #define MSCAN_CANCTL0_RXACT_SHIFT (6U) 3746 /*! RXACT - Receiver Active Status 3747 * 0b0..MSCAN is transmitting or idle. 3748 * 0b1..MSCAN is receiving a message, including when arbitration is lost. 3749 */ 3750 #define MSCAN_CANCTL0_RXACT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_RXACT_SHIFT)) & MSCAN_CANCTL0_RXACT_MASK) 3751 #define MSCAN_CANCTL0_RXFRM_MASK (0x80U) 3752 #define MSCAN_CANCTL0_RXFRM_SHIFT (7U) 3753 /*! RXFRM - Received Frame Flag 3754 * 0b0..No valid message was received since last clearing this flag. 3755 * 0b1..A valid message was received since last clearing of this flag. 3756 */ 3757 #define MSCAN_CANCTL0_RXFRM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL0_RXFRM_SHIFT)) & MSCAN_CANCTL0_RXFRM_MASK) 3758 /*! @} */ 3759 3760 /*! @name CANCTL1 - MSCAN Control Register 1 */ 3761 /*! @{ */ 3762 #define MSCAN_CANCTL1_INITAK_MASK (0x1U) 3763 #define MSCAN_CANCTL1_INITAK_SHIFT (0U) 3764 /*! INITAK - Initialization Mode Acknowledge 3765 * 0b0..Running - The MSCAN operates normally. 3766 * 0b1..Initialization mode active - The MSCAN has entered initialization mode. 3767 */ 3768 #define MSCAN_CANCTL1_INITAK(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_INITAK_SHIFT)) & MSCAN_CANCTL1_INITAK_MASK) 3769 #define MSCAN_CANCTL1_SLPAK_MASK (0x2U) 3770 #define MSCAN_CANCTL1_SLPAK_SHIFT (1U) 3771 /*! SLPAK - Sleep Mode Acknowledge 3772 * 0b0..Running - The MSCAN operates normally. 3773 * 0b1..Sleep mode active - The MSCAN has entered sleep mode. 3774 */ 3775 #define MSCAN_CANCTL1_SLPAK(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_SLPAK_SHIFT)) & MSCAN_CANCTL1_SLPAK_MASK) 3776 #define MSCAN_CANCTL1_WUPM_MASK (0x4U) 3777 #define MSCAN_CANCTL1_WUPM_SHIFT (2U) 3778 /*! WUPM - WakeUp Mode 3779 * 0b0..MSCAN wakes on any dominant level on the CAN bus. 3780 * 0b1..MSCAN wakes only in case of a dominant pulse on the CAN bus that has a length of Twup. 3781 */ 3782 #define MSCAN_CANCTL1_WUPM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_WUPM_SHIFT)) & MSCAN_CANCTL1_WUPM_MASK) 3783 #define MSCAN_CANCTL1_BORM_MASK (0x8U) 3784 #define MSCAN_CANCTL1_BORM_SHIFT (3U) 3785 /*! BORM - Bus-Off Recovery Mode 3786 * 0b0..Automatic bus-off recovery (see Bosch CAN 2.0A/B protocol specification). 3787 * 0b1..Bus-off recovery upon user request. 3788 */ 3789 #define MSCAN_CANCTL1_BORM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_BORM_SHIFT)) & MSCAN_CANCTL1_BORM_MASK) 3790 #define MSCAN_CANCTL1_LISTEN_MASK (0x10U) 3791 #define MSCAN_CANCTL1_LISTEN_SHIFT (4U) 3792 /*! LISTEN - Listen Only Mode 3793 * 0b0..Normal operation. 3794 * 0b1..Listen only mode activated. 3795 */ 3796 #define MSCAN_CANCTL1_LISTEN(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_LISTEN_SHIFT)) & MSCAN_CANCTL1_LISTEN_MASK) 3797 #define MSCAN_CANCTL1_LOOPB_MASK (0x20U) 3798 #define MSCAN_CANCTL1_LOOPB_SHIFT (5U) 3799 /*! LOOPB - Loopback Self Test Mode 3800 * 0b0..Loopback self test disabled. 3801 * 0b1..Loopback self test enabled. 3802 */ 3803 #define MSCAN_CANCTL1_LOOPB(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_LOOPB_SHIFT)) & MSCAN_CANCTL1_LOOPB_MASK) 3804 #define MSCAN_CANCTL1_CLKSRC_MASK (0x40U) 3805 #define MSCAN_CANCTL1_CLKSRC_SHIFT (6U) 3806 /*! CLKSRC - MSCAN Clock Source 3807 * 0b0..MSCAN clock source is the oscillator clock. 3808 * 0b1..MSCAN clock source is the bus clock. 3809 */ 3810 #define MSCAN_CANCTL1_CLKSRC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_CLKSRC_SHIFT)) & MSCAN_CANCTL1_CLKSRC_MASK) 3811 #define MSCAN_CANCTL1_CANE_MASK (0x80U) 3812 #define MSCAN_CANCTL1_CANE_SHIFT (7U) 3813 /*! CANE - MSCAN Enable 3814 * 0b0..MSCAN module is disabled. 3815 * 0b1..MSCAN module is enabled. 3816 */ 3817 #define MSCAN_CANCTL1_CANE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANCTL1_CANE_SHIFT)) & MSCAN_CANCTL1_CANE_MASK) 3818 /*! @} */ 3819 3820 /*! @name CANBTR0 - MSCAN Bus Timing Register 0 */ 3821 /*! @{ */ 3822 #define MSCAN_CANBTR0_BRP_MASK (0x3FU) 3823 #define MSCAN_CANBTR0_BRP_SHIFT (0U) 3824 /*! BRP - Baud Rate Prescaler 3825 * 0b000000..1 3826 * 0b000001..2 3827 * 0b000010........ 3828 * 0b000011........ 3829 * 0b111110..63 3830 * 0b111111..64 3831 */ 3832 #define MSCAN_CANBTR0_BRP(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR0_BRP_SHIFT)) & MSCAN_CANBTR0_BRP_MASK) 3833 #define MSCAN_CANBTR0_SJW_MASK (0xC0U) 3834 #define MSCAN_CANBTR0_SJW_SHIFT (6U) 3835 /*! SJW - Synchronization Jump Width 3836 * 0b00..1 Tq clock cycle. 3837 * 0b01..2 Tq clock cycles. 3838 * 0b10..3 Tq clock cycle. 3839 * 0b11..4 Tq clock cycles. 3840 */ 3841 #define MSCAN_CANBTR0_SJW(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR0_SJW_SHIFT)) & MSCAN_CANBTR0_SJW_MASK) 3842 /*! @} */ 3843 3844 /*! @name CANBTR1 - MSCAN Bus Timing Register 1 */ 3845 /*! @{ */ 3846 #define MSCAN_CANBTR1_TSEG1_MASK (0xFU) 3847 #define MSCAN_CANBTR1_TSEG1_SHIFT (0U) 3848 /*! TSEG1 - Time Segment 1 3849 * 0b0000..1 Tq clock cycle (not valid) 3850 * 0b0001..2 Tq clock cycles (not valid) 3851 * 0b0010..3 Tq clock cycles (not valid) 3852 * 0b0011..4 Tq clock cycles 3853 * 0b1110..15 Tq clock cycles 3854 * 0b1111..16 Tq clock cycles 3855 */ 3856 #define MSCAN_CANBTR1_TSEG1(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR1_TSEG1_SHIFT)) & MSCAN_CANBTR1_TSEG1_MASK) 3857 #define MSCAN_CANBTR1_TSEG2_MASK (0x70U) 3858 #define MSCAN_CANBTR1_TSEG2_SHIFT (4U) 3859 /*! TSEG2 - Time Segment 2 3860 * 0b000..1 Tq clock cycle (not valid) 3861 * 0b001..2 Tq clock cycles 3862 * 0b010..3 Tq clock cycles 3863 * 0b011..4 Tq clock cycles 3864 * 0b100..5 Tq clock cycles 3865 * 0b101..6 Tq clock cycles 3866 * 0b110..7 Tq clock cycles 3867 * 0b111..8 Tq clock cycles 3868 */ 3869 #define MSCAN_CANBTR1_TSEG2(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR1_TSEG2_SHIFT)) & MSCAN_CANBTR1_TSEG2_MASK) 3870 #define MSCAN_CANBTR1_SAMP_MASK (0x80U) 3871 #define MSCAN_CANBTR1_SAMP_SHIFT (7U) 3872 /*! SAMP - Sampling 3873 * 0b0..One sample per bit. 3874 * 0b1..Three samples per bit. In this case, PHASE_SEG1 must be at least 2 time quanta (Tq). 3875 */ 3876 #define MSCAN_CANBTR1_SAMP(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANBTR1_SAMP_SHIFT)) & MSCAN_CANBTR1_SAMP_MASK) 3877 /*! @} */ 3878 3879 /*! @name CANRFLG - MSCAN Receiver Flag Register */ 3880 /*! @{ */ 3881 #define MSCAN_CANRFLG_RXF_MASK (0x1U) 3882 #define MSCAN_CANRFLG_RXF_SHIFT (0U) 3883 /*! RXF - Receive Buffer Full Flag 3884 * 0b0..No new message available within the RxFG. 3885 * 0b1..The receiver FIFO is not empty. A new message is available in the RxFG. 3886 */ 3887 #define MSCAN_CANRFLG_RXF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_RXF_SHIFT)) & MSCAN_CANRFLG_RXF_MASK) 3888 #define MSCAN_CANRFLG_OVRIF_MASK (0x2U) 3889 #define MSCAN_CANRFLG_OVRIF_SHIFT (1U) 3890 /*! OVRIF - Overrun Interrupt Flag 3891 * 0b0..No data overrun condition. 3892 * 0b1..A data overrun detected. 3893 */ 3894 #define MSCAN_CANRFLG_OVRIF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_OVRIF_SHIFT)) & MSCAN_CANRFLG_OVRIF_MASK) 3895 #define MSCAN_CANRFLG_TSTAT_MASK (0xCU) 3896 #define MSCAN_CANRFLG_TSTAT_SHIFT (2U) 3897 /*! TSTAT - Transmitter Status 3898 * 0b00..TxOK: 0<=transmit error counter<96 3899 * 0b01..TxWRN: 96<=transmit error counter<128 3900 * 0b10..TxERR: 128<=transmit error counter<256 3901 * 0b11..Bus-off: 256<=transmit error counter 3902 */ 3903 #define MSCAN_CANRFLG_TSTAT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_TSTAT_SHIFT)) & MSCAN_CANRFLG_TSTAT_MASK) 3904 #define MSCAN_CANRFLG_RSTAT_MASK (0x30U) 3905 #define MSCAN_CANRFLG_RSTAT_SHIFT (4U) 3906 /*! RSTAT - Receiver Status 3907 * 0b00..RxOK: 0<=receive error counter<96 3908 * 0b01..RxWRN: 96<=receive error counter<128 3909 * 0b10..RxERR: 128<=receive error counter 3910 * 0b11..Bus-off: 256<=transmit error counter (Redundant Information for the most critical CAN bus status which is "bus-off". This only occurs if the Tx error counter exceeds a number of 255 errors. Bus-off affects the receiver state. As soon as the transmitter leaves its bus-off state the receiver state skips to RxOK too. Refer also to TSTAT[1:0] coding in this register. ) 3911 */ 3912 #define MSCAN_CANRFLG_RSTAT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_RSTAT_SHIFT)) & MSCAN_CANRFLG_RSTAT_MASK) 3913 #define MSCAN_CANRFLG_CSCIF_MASK (0x40U) 3914 #define MSCAN_CANRFLG_CSCIF_SHIFT (6U) 3915 /*! CSCIF - CAN Status Change Interrupt Flag 3916 * 0b0..No change in CAN bus status occurred since last interrupt. 3917 * 0b1..MSCAN changed current CAN bus status. 3918 */ 3919 #define MSCAN_CANRFLG_CSCIF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_CSCIF_SHIFT)) & MSCAN_CANRFLG_CSCIF_MASK) 3920 #define MSCAN_CANRFLG_WUPIF_MASK (0x80U) 3921 #define MSCAN_CANRFLG_WUPIF_SHIFT (7U) 3922 /*! WUPIF - Wake-Up Interrupt Flag 3923 * 0b0..No wakeup activity observed while in sleep mode. 3924 * 0b1..MSCAN detected activity on the CAN bus and requested wakeup. 3925 */ 3926 #define MSCAN_CANRFLG_WUPIF(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRFLG_WUPIF_SHIFT)) & MSCAN_CANRFLG_WUPIF_MASK) 3927 /*! @} */ 3928 3929 /*! @name CANRIER - MSCAN Receiver Interrupt Enable Register */ 3930 /*! @{ */ 3931 #define MSCAN_CANRIER_RXFIE_MASK (0x1U) 3932 #define MSCAN_CANRIER_RXFIE_SHIFT (0U) 3933 /*! RXFIE - Receiver Full Interrupt Enable 3934 * 0b0..No interrupt request is generated from this event. 3935 * 0b1..A receive buffer full (successful message reception) event causes a receiver interrupt request. 3936 */ 3937 #define MSCAN_CANRIER_RXFIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_RXFIE_SHIFT)) & MSCAN_CANRIER_RXFIE_MASK) 3938 #define MSCAN_CANRIER_OVRIE_MASK (0x2U) 3939 #define MSCAN_CANRIER_OVRIE_SHIFT (1U) 3940 /*! OVRIE - Overrun Interrupt Enable 3941 * 0b0..No interrupt request is generated from this event. 3942 * 0b1..An overrun event causes an error interrupt request. 3943 */ 3944 #define MSCAN_CANRIER_OVRIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_OVRIE_SHIFT)) & MSCAN_CANRIER_OVRIE_MASK) 3945 #define MSCAN_CANRIER_TSTATE_MASK (0xCU) 3946 #define MSCAN_CANRIER_TSTATE_SHIFT (2U) 3947 /*! TSTATE - Transmitter Status Change Enable 3948 * 0b00..Do not generate any CSCIF interrupt caused by transmitter state changes. 3949 * 0b01..Generate CSCIF interrupt only if the transmitter enters or leaves "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt. 3950 * 0b10..Generate CSCIF interrupt only if the transmitter enters or leaves "TxErr" or "bus-off" state. Discard other transmitter state changes for generating CSCIF interrupt. 3951 * 0b11..Generate CSCIF interrupt on all state changes. 3952 */ 3953 #define MSCAN_CANRIER_TSTATE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_TSTATE_SHIFT)) & MSCAN_CANRIER_TSTATE_MASK) 3954 #define MSCAN_CANRIER_RSTATE_MASK (0x30U) 3955 #define MSCAN_CANRIER_RSTATE_SHIFT (4U) 3956 /*! RSTATE - Receiver Status Change Enable 3957 * 0b00..Do not generate any CSCIF interrupt caused by receiver state changes. 3958 * 0b01..Generate CSCIF interrupt only if the receiver enters or leaves "bus-off" state. Discard other receiver state changes for generating CSCIF interrupt. 3959 * 0b10..Generate CSCIF interrupt only if the receiver enters or leaves "RxErr" or "bus-off"Bus-off state is only defined for transmitters by the CAN standard (see Bosch CAN 2.0A/B protocol specification). Because the only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK, the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver state. Discard other receiver state changes for generating CSCIF interrupt. 3960 * 0b11..Generate CSCIF interrupt on all state changes. 3961 */ 3962 #define MSCAN_CANRIER_RSTATE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_RSTATE_SHIFT)) & MSCAN_CANRIER_RSTATE_MASK) 3963 #define MSCAN_CANRIER_CSCIE_MASK (0x40U) 3964 #define MSCAN_CANRIER_CSCIE_SHIFT (6U) 3965 /*! CSCIE - CAN Status Change Interrupt Enable 3966 * 0b0..No interrupt request is generated from this event. 3967 * 0b1..A CAN Status Change event causes an error interrupt request. 3968 */ 3969 #define MSCAN_CANRIER_CSCIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_CSCIE_SHIFT)) & MSCAN_CANRIER_CSCIE_MASK) 3970 #define MSCAN_CANRIER_WUPIE_MASK (0x80U) 3971 #define MSCAN_CANRIER_WUPIE_SHIFT (7U) 3972 /*! WUPIE - WakeUp Interrupt Enable 3973 * 0b0..No interrupt request is generated from this event. 3974 * 0b1..A wake-up event causes a Wake-Up interrupt request. 3975 */ 3976 #define MSCAN_CANRIER_WUPIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRIER_WUPIE_SHIFT)) & MSCAN_CANRIER_WUPIE_MASK) 3977 /*! @} */ 3978 3979 /*! @name CANTFLG - MSCAN Transmitter Flag Register */ 3980 /*! @{ */ 3981 #define MSCAN_CANTFLG_TXE_MASK (0x7U) 3982 #define MSCAN_CANTFLG_TXE_SHIFT (0U) 3983 /*! TXE - Transmitter Buffer Empty 3984 * 0b000..The associated message buffer is full (loaded with a message due for transmission). 3985 * 0b001..The associated message buffer is empty (not scheduled). 3986 */ 3987 #define MSCAN_CANTFLG_TXE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTFLG_TXE_SHIFT)) & MSCAN_CANTFLG_TXE_MASK) 3988 /*! @} */ 3989 3990 /*! @name CANTIER - MSCAN Transmitter Interrupt Enable Register */ 3991 /*! @{ */ 3992 #define MSCAN_CANTIER_TXEIE_MASK (0x7U) 3993 #define MSCAN_CANTIER_TXEIE_SHIFT (0U) 3994 /*! TXEIE - Transmitter Empty Interrupt Enable 3995 * 0b000..No interrupt request is generated from this event. 3996 * 0b001..A transmitter empty (transmit buffer available for transmission) event causes a transmitter empty interrupt request. 3997 */ 3998 #define MSCAN_CANTIER_TXEIE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTIER_TXEIE_SHIFT)) & MSCAN_CANTIER_TXEIE_MASK) 3999 /*! @} */ 4000 4001 /*! @name CANTARQ - MSCAN Transmitter Message Abort Request Register */ 4002 /*! @{ */ 4003 #define MSCAN_CANTARQ_ABTRQ_MASK (0x7U) 4004 #define MSCAN_CANTARQ_ABTRQ_SHIFT (0U) 4005 /*! ABTRQ - Abort Request 4006 * 0b000..No abort request. 4007 * 0b001..Abort request pending. 4008 */ 4009 #define MSCAN_CANTARQ_ABTRQ(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTARQ_ABTRQ_SHIFT)) & MSCAN_CANTARQ_ABTRQ_MASK) 4010 /*! @} */ 4011 4012 /*! @name CANTAAK - MSCAN Transmitter Message Abort Acknowledge Register */ 4013 /*! @{ */ 4014 #define MSCAN_CANTAAK_ABTAK_MASK (0x7U) 4015 #define MSCAN_CANTAAK_ABTAK_SHIFT (0U) 4016 /*! ABTAK - Abort Acknowledge 4017 * 0b000..The message was not aborted. 4018 * 0b001..The message was aborted. 4019 */ 4020 #define MSCAN_CANTAAK_ABTAK(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTAAK_ABTAK_SHIFT)) & MSCAN_CANTAAK_ABTAK_MASK) 4021 /*! @} */ 4022 4023 /*! @name CANTBSEL - MSCAN Transmit Buffer Selection Register */ 4024 /*! @{ */ 4025 #define MSCAN_CANTBSEL_TX_MASK (0x7U) 4026 #define MSCAN_CANTBSEL_TX_SHIFT (0U) 4027 /*! TX - Transmit Buffer Select 4028 * 0b000..The associated message buffer is deselected. 4029 * 0b001..The associated message buffer is selected, if lowest numbered bit. 4030 */ 4031 #define MSCAN_CANTBSEL_TX(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTBSEL_TX_SHIFT)) & MSCAN_CANTBSEL_TX_MASK) 4032 /*! @} */ 4033 4034 /*! @name CANIDAC - MSCAN Identifier Acceptance Control Register */ 4035 /*! @{ */ 4036 #define MSCAN_CANIDAC_IDHIT_MASK (0x7U) 4037 #define MSCAN_CANIDAC_IDHIT_SHIFT (0U) 4038 /*! IDHIT - Identifier Acceptance Hit Indicator 4039 * 0b000..Filter 0 hit. 4040 * 0b001..Filter 1 hit. 4041 * 0b010..Filter 2 hit. 4042 * 0b011..Filter 3 hit. 4043 * 0b100..Filter 4 hit. 4044 * 0b101..Filter 5 hit. 4045 * 0b110..Filter 6 hit. 4046 * 0b111..Filter 7 hit. 4047 */ 4048 #define MSCAN_CANIDAC_IDHIT(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAC_IDHIT_SHIFT)) & MSCAN_CANIDAC_IDHIT_MASK) 4049 #define MSCAN_CANIDAC_IDAM_MASK (0x30U) 4050 #define MSCAN_CANIDAC_IDAM_SHIFT (4U) 4051 /*! IDAM - Identifier Acceptance Mode 4052 * 0b00..Two 32-bit acceptance filters. 4053 * 0b01..Four 16-bit acceptance filters. 4054 * 0b10..Eight 8-bit acceptance filters. 4055 * 0b11..Filter closed. 4056 */ 4057 #define MSCAN_CANIDAC_IDAM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAC_IDAM_SHIFT)) & MSCAN_CANIDAC_IDAM_MASK) 4058 /*! @} */ 4059 4060 /*! @name CANMISC - MSCAN Miscellaneous Register */ 4061 /*! @{ */ 4062 #define MSCAN_CANMISC_BOHOLD_MASK (0x1U) 4063 #define MSCAN_CANMISC_BOHOLD_SHIFT (0U) 4064 /*! BOHOLD - Bus-off State Hold Until User Request 4065 * 0b0..Module is not bus-off or recovery has been requested by user in bus-off state. 4066 * 0b1..Module is bus-off and holds this state until user request. 4067 */ 4068 #define MSCAN_CANMISC_BOHOLD(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANMISC_BOHOLD_SHIFT)) & MSCAN_CANMISC_BOHOLD_MASK) 4069 /*! @} */ 4070 4071 /*! @name CANRXERR - MSCAN Receive Error Counter */ 4072 /*! @{ */ 4073 #define MSCAN_CANRXERR_RXERR_MASK (0xFFU) 4074 #define MSCAN_CANRXERR_RXERR_SHIFT (0U) 4075 #define MSCAN_CANRXERR_RXERR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANRXERR_RXERR_SHIFT)) & MSCAN_CANRXERR_RXERR_MASK) 4076 /*! @} */ 4077 4078 /*! @name CANTXERR - MSCAN Transmit Error Counter */ 4079 /*! @{ */ 4080 #define MSCAN_CANTXERR_TXERR_MASK (0xFFU) 4081 #define MSCAN_CANTXERR_TXERR_SHIFT (0U) 4082 #define MSCAN_CANTXERR_TXERR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANTXERR_TXERR_SHIFT)) & MSCAN_CANTXERR_TXERR_MASK) 4083 /*! @} */ 4084 4085 /*! @name CANIDAR_BANK_1 - MSCAN Identifier Acceptance Register n of First Bank */ 4086 /*! @{ */ 4087 #define MSCAN_CANIDAR_BANK_1_AC_MASK (0xFFU) 4088 #define MSCAN_CANIDAR_BANK_1_AC_SHIFT (0U) 4089 #define MSCAN_CANIDAR_BANK_1_AC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAR_BANK_1_AC_SHIFT)) & MSCAN_CANIDAR_BANK_1_AC_MASK) 4090 /*! @} */ 4091 4092 /* The count of MSCAN_CANIDAR_BANK_1 */ 4093 #define MSCAN_CANIDAR_BANK_1_COUNT (4U) 4094 4095 /*! @name CANIDMR_BANK_1 - MSCAN Identifier Mask Register n of First Bank */ 4096 /*! @{ */ 4097 #define MSCAN_CANIDMR_BANK_1_AM_MASK (0xFFU) 4098 #define MSCAN_CANIDMR_BANK_1_AM_SHIFT (0U) 4099 /*! AM - Acceptance Mask Bits 4100 * 0b00000000..Match corresponding acceptance code register and identifier bits. 4101 * 0b00000001..Ignore corresponding acceptance code register bit. 4102 */ 4103 #define MSCAN_CANIDMR_BANK_1_AM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDMR_BANK_1_AM_SHIFT)) & MSCAN_CANIDMR_BANK_1_AM_MASK) 4104 /*! @} */ 4105 4106 /* The count of MSCAN_CANIDMR_BANK_1 */ 4107 #define MSCAN_CANIDMR_BANK_1_COUNT (4U) 4108 4109 /*! @name CANIDAR_BANK_2 - MSCAN Identifier Acceptance Register n of Second Bank */ 4110 /*! @{ */ 4111 #define MSCAN_CANIDAR_BANK_2_AC_MASK (0xFFU) 4112 #define MSCAN_CANIDAR_BANK_2_AC_SHIFT (0U) 4113 #define MSCAN_CANIDAR_BANK_2_AC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDAR_BANK_2_AC_SHIFT)) & MSCAN_CANIDAR_BANK_2_AC_MASK) 4114 /*! @} */ 4115 4116 /* The count of MSCAN_CANIDAR_BANK_2 */ 4117 #define MSCAN_CANIDAR_BANK_2_COUNT (4U) 4118 4119 /*! @name CANIDMR_BANK_2 - MSCAN Identifier Mask Register n of Second Bank */ 4120 /*! @{ */ 4121 #define MSCAN_CANIDMR_BANK_2_AM_MASK (0xFFU) 4122 #define MSCAN_CANIDMR_BANK_2_AM_SHIFT (0U) 4123 /*! AM - Acceptance Mask Bits 4124 * 0b00000000..Match corresponding acceptance code register and identifier bits. 4125 * 0b00000001..Ignore corresponding acceptance code register bit. 4126 */ 4127 #define MSCAN_CANIDMR_BANK_2_AM(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_CANIDMR_BANK_2_AM_SHIFT)) & MSCAN_CANIDMR_BANK_2_AM_MASK) 4128 /*! @} */ 4129 4130 /* The count of MSCAN_CANIDMR_BANK_2 */ 4131 #define MSCAN_CANIDMR_BANK_2_COUNT (4U) 4132 4133 /*! @name REIDR0 - Receive Extended Identifier Register 0 */ 4134 /*! @{ */ 4135 #define MSCAN_REIDR0_REID28_REID21_MASK (0xFFU) 4136 #define MSCAN_REIDR0_REID28_REID21_SHIFT (0U) 4137 #define MSCAN_REIDR0_REID28_REID21(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR0_REID28_REID21_SHIFT)) & MSCAN_REIDR0_REID28_REID21_MASK) 4138 /*! @} */ 4139 4140 /*! @name RSIDR0 - Receive Standard Identifier Register 0 */ 4141 /*! @{ */ 4142 #define MSCAN_RSIDR0_RSID10_RSID3_MASK (0xFFU) 4143 #define MSCAN_RSIDR0_RSID10_RSID3_SHIFT (0U) 4144 #define MSCAN_RSIDR0_RSID10_RSID3(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR0_RSID10_RSID3_SHIFT)) & MSCAN_RSIDR0_RSID10_RSID3_MASK) 4145 /*! @} */ 4146 4147 /*! @name REIDR1 - Receive Extended Identifier Register 1 */ 4148 /*! @{ */ 4149 #define MSCAN_REIDR1_REID17_REID15_MASK (0x7U) 4150 #define MSCAN_REIDR1_REID17_REID15_SHIFT (0U) 4151 #define MSCAN_REIDR1_REID17_REID15(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_REID17_REID15_SHIFT)) & MSCAN_REIDR1_REID17_REID15_MASK) 4152 #define MSCAN_REIDR1_REIDE_MASK (0x8U) 4153 #define MSCAN_REIDR1_REIDE_SHIFT (3U) 4154 /*! REIDE - ID Extended 4155 * 0b0..Standard format (11 bit). 4156 * 0b1..Extended format (29 bit). 4157 */ 4158 #define MSCAN_REIDR1_REIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_REIDE_SHIFT)) & MSCAN_REIDR1_REIDE_MASK) 4159 #define MSCAN_REIDR1_RSRR_MASK (0x10U) 4160 #define MSCAN_REIDR1_RSRR_SHIFT (4U) 4161 #define MSCAN_REIDR1_RSRR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_RSRR_SHIFT)) & MSCAN_REIDR1_RSRR_MASK) 4162 #define MSCAN_REIDR1_REID20_REID18_MASK (0xE0U) 4163 #define MSCAN_REIDR1_REID20_REID18_SHIFT (5U) 4164 #define MSCAN_REIDR1_REID20_REID18(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR1_REID20_REID18_SHIFT)) & MSCAN_REIDR1_REID20_REID18_MASK) 4165 /*! @} */ 4166 4167 /*! @name RSIDR1 - Receive Standard Identifier Register 1 */ 4168 /*! @{ */ 4169 #define MSCAN_RSIDR1_RSIDE_MASK (0x8U) 4170 #define MSCAN_RSIDR1_RSIDE_SHIFT (3U) 4171 /*! RSIDE - ID Extended 4172 * 0b0..Standard format (11 bit). 4173 * 0b1..Extended format (29 bit). 4174 */ 4175 #define MSCAN_RSIDR1_RSIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR1_RSIDE_SHIFT)) & MSCAN_RSIDR1_RSIDE_MASK) 4176 #define MSCAN_RSIDR1_RSRTR_MASK (0x10U) 4177 #define MSCAN_RSIDR1_RSRTR_SHIFT (4U) 4178 /*! RSRTR - Remote Transmission Request 4179 * 0b0..Data frame. 4180 * 0b1..Remote frame. 4181 */ 4182 #define MSCAN_RSIDR1_RSRTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR1_RSRTR_SHIFT)) & MSCAN_RSIDR1_RSRTR_MASK) 4183 #define MSCAN_RSIDR1_RSID2_RSID0_MASK (0xE0U) 4184 #define MSCAN_RSIDR1_RSID2_RSID0_SHIFT (5U) 4185 #define MSCAN_RSIDR1_RSID2_RSID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RSIDR1_RSID2_RSID0_SHIFT)) & MSCAN_RSIDR1_RSID2_RSID0_MASK) 4186 /*! @} */ 4187 4188 /*! @name REIDR2 - Receive Extended Identifier Register 2 */ 4189 /*! @{ */ 4190 #define MSCAN_REIDR2_REID14_REID7_MASK (0xFFU) 4191 #define MSCAN_REIDR2_REID14_REID7_SHIFT (0U) 4192 #define MSCAN_REIDR2_REID14_REID7(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR2_REID14_REID7_SHIFT)) & MSCAN_REIDR2_REID14_REID7_MASK) 4193 /*! @} */ 4194 4195 /*! @name REIDR3 - Receive Extended Identifier Register 3 */ 4196 /*! @{ */ 4197 #define MSCAN_REIDR3_RERTR_MASK (0x1U) 4198 #define MSCAN_REIDR3_RERTR_SHIFT (0U) 4199 /*! RERTR - Remote Transmission Request 4200 * 0b0..Data frame. 4201 * 0b1..Remote frame. 4202 */ 4203 #define MSCAN_REIDR3_RERTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR3_RERTR_SHIFT)) & MSCAN_REIDR3_RERTR_MASK) 4204 #define MSCAN_REIDR3_REID6_REID0_MASK (0xFEU) 4205 #define MSCAN_REIDR3_REID6_REID0_SHIFT (1U) 4206 #define MSCAN_REIDR3_REID6_REID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REIDR3_REID6_REID0_SHIFT)) & MSCAN_REIDR3_REID6_REID0_MASK) 4207 /*! @} */ 4208 4209 /*! @name REDSR - Receive Extended Data Segment Register N */ 4210 /*! @{ */ 4211 #define MSCAN_REDSR_RDB_MASK (0xFFU) 4212 #define MSCAN_REDSR_RDB_SHIFT (0U) 4213 #define MSCAN_REDSR_RDB(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_REDSR_RDB_SHIFT)) & MSCAN_REDSR_RDB_MASK) 4214 /*! @} */ 4215 4216 /* The count of MSCAN_REDSR */ 4217 #define MSCAN_REDSR_COUNT (8U) 4218 4219 /*! @name RDLR - Receive Data Length Register */ 4220 /*! @{ */ 4221 #define MSCAN_RDLR_RDLC_MASK (0xFU) 4222 #define MSCAN_RDLR_RDLC_SHIFT (0U) 4223 /*! RDLC - Data Length Code Bits 4224 * 0b0000..0 4225 * 0b0001..1 4226 * 0b0010..2 4227 * 0b0011..3 4228 * 0b0100..4 4229 * 0b0101..5 4230 * 0b0110..6 4231 * 0b0111..7 4232 * 0b1000..8 4233 */ 4234 #define MSCAN_RDLR_RDLC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RDLR_RDLC_SHIFT)) & MSCAN_RDLR_RDLC_MASK) 4235 /*! @} */ 4236 4237 /*! @name RTSRH - Receive Time Stamp Register High */ 4238 /*! @{ */ 4239 #define MSCAN_RTSRH_RTS_MASK (0xFFU) 4240 #define MSCAN_RTSRH_RTS_SHIFT (0U) 4241 #define MSCAN_RTSRH_RTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RTSRH_RTS_SHIFT)) & MSCAN_RTSRH_RTS_MASK) 4242 /*! @} */ 4243 4244 /*! @name RTSRL - Receive Time Stamp Register Low */ 4245 /*! @{ */ 4246 #define MSCAN_RTSRL_RTS_MASK (0xFFU) 4247 #define MSCAN_RTSRL_RTS_SHIFT (0U) 4248 #define MSCAN_RTSRL_RTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_RTSRL_RTS_SHIFT)) & MSCAN_RTSRL_RTS_MASK) 4249 /*! @} */ 4250 4251 /*! @name TEIDR0 - Transmit Extended Identifier Register 0 */ 4252 /*! @{ */ 4253 #define MSCAN_TEIDR0_TEID28_TEID21_MASK (0xFFU) 4254 #define MSCAN_TEIDR0_TEID28_TEID21_SHIFT (0U) 4255 #define MSCAN_TEIDR0_TEID28_TEID21(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR0_TEID28_TEID21_SHIFT)) & MSCAN_TEIDR0_TEID28_TEID21_MASK) 4256 /*! @} */ 4257 4258 /*! @name TSIDR0 - Transmit Standard Identifier Register 0 */ 4259 /*! @{ */ 4260 #define MSCAN_TSIDR0_TSID10_TSID3_MASK (0xFFU) 4261 #define MSCAN_TSIDR0_TSID10_TSID3_SHIFT (0U) 4262 #define MSCAN_TSIDR0_TSID10_TSID3(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR0_TSID10_TSID3_SHIFT)) & MSCAN_TSIDR0_TSID10_TSID3_MASK) 4263 /*! @} */ 4264 4265 /*! @name TEIDR1 - Transmit Extended Identifier Register 1 */ 4266 /*! @{ */ 4267 #define MSCAN_TEIDR1_TEID17_TEID15_MASK (0x7U) 4268 #define MSCAN_TEIDR1_TEID17_TEID15_SHIFT (0U) 4269 #define MSCAN_TEIDR1_TEID17_TEID15(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TEID17_TEID15_SHIFT)) & MSCAN_TEIDR1_TEID17_TEID15_MASK) 4270 #define MSCAN_TEIDR1_TEIDE_MASK (0x8U) 4271 #define MSCAN_TEIDR1_TEIDE_SHIFT (3U) 4272 /*! TEIDE - ID Extended 4273 * 0b0..Standard format (11 bit). 4274 * 0b1..Extended format (29 bit). 4275 */ 4276 #define MSCAN_TEIDR1_TEIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TEIDE_SHIFT)) & MSCAN_TEIDR1_TEIDE_MASK) 4277 #define MSCAN_TEIDR1_TSRR_MASK (0x10U) 4278 #define MSCAN_TEIDR1_TSRR_SHIFT (4U) 4279 #define MSCAN_TEIDR1_TSRR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TSRR_SHIFT)) & MSCAN_TEIDR1_TSRR_MASK) 4280 #define MSCAN_TEIDR1_TEID20_TEID18_MASK (0xE0U) 4281 #define MSCAN_TEIDR1_TEID20_TEID18_SHIFT (5U) 4282 #define MSCAN_TEIDR1_TEID20_TEID18(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR1_TEID20_TEID18_SHIFT)) & MSCAN_TEIDR1_TEID20_TEID18_MASK) 4283 /*! @} */ 4284 4285 /*! @name TSIDR1 - Transmit Standard Identifier Register 1 */ 4286 /*! @{ */ 4287 #define MSCAN_TSIDR1_TSIDE_MASK (0x8U) 4288 #define MSCAN_TSIDR1_TSIDE_SHIFT (3U) 4289 /*! TSIDE - ID Extended 4290 * 0b0..Standard format (11 bit). 4291 * 0b1..Extended format (29 bit). 4292 */ 4293 #define MSCAN_TSIDR1_TSIDE(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR1_TSIDE_SHIFT)) & MSCAN_TSIDR1_TSIDE_MASK) 4294 #define MSCAN_TSIDR1_TSRTR_MASK (0x10U) 4295 #define MSCAN_TSIDR1_TSRTR_SHIFT (4U) 4296 /*! TSRTR - Remote Transmission Request 4297 * 0b0..Data frame. 4298 * 0b1..Remote frame. 4299 */ 4300 #define MSCAN_TSIDR1_TSRTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR1_TSRTR_SHIFT)) & MSCAN_TSIDR1_TSRTR_MASK) 4301 #define MSCAN_TSIDR1_TSID2_TSID0_MASK (0xE0U) 4302 #define MSCAN_TSIDR1_TSID2_TSID0_SHIFT (5U) 4303 #define MSCAN_TSIDR1_TSID2_TSID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TSIDR1_TSID2_TSID0_SHIFT)) & MSCAN_TSIDR1_TSID2_TSID0_MASK) 4304 /*! @} */ 4305 4306 /*! @name TEIDR2 - Transmit Extended Identifier Register 2 */ 4307 /*! @{ */ 4308 #define MSCAN_TEIDR2_TEID14_TEID7_MASK (0xFFU) 4309 #define MSCAN_TEIDR2_TEID14_TEID7_SHIFT (0U) 4310 #define MSCAN_TEIDR2_TEID14_TEID7(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR2_TEID14_TEID7_SHIFT)) & MSCAN_TEIDR2_TEID14_TEID7_MASK) 4311 /*! @} */ 4312 4313 /*! @name TEIDR3 - Transmit Extended Identifier Register 3 */ 4314 /*! @{ */ 4315 #define MSCAN_TEIDR3_TERTR_MASK (0x1U) 4316 #define MSCAN_TEIDR3_TERTR_SHIFT (0U) 4317 /*! TERTR - Remote Transmission Request 4318 * 0b0..Data frame. 4319 * 0b1..Remote frame. 4320 */ 4321 #define MSCAN_TEIDR3_TERTR(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR3_TERTR_SHIFT)) & MSCAN_TEIDR3_TERTR_MASK) 4322 #define MSCAN_TEIDR3_TEID6_TEID0_MASK (0xFEU) 4323 #define MSCAN_TEIDR3_TEID6_TEID0_SHIFT (1U) 4324 #define MSCAN_TEIDR3_TEID6_TEID0(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEIDR3_TEID6_TEID0_SHIFT)) & MSCAN_TEIDR3_TEID6_TEID0_MASK) 4325 /*! @} */ 4326 4327 /*! @name TEDSR - Transmit Extended Data Segment Register N */ 4328 /*! @{ */ 4329 #define MSCAN_TEDSR_TDB_MASK (0xFFU) 4330 #define MSCAN_TEDSR_TDB_SHIFT (0U) 4331 #define MSCAN_TEDSR_TDB(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TEDSR_TDB_SHIFT)) & MSCAN_TEDSR_TDB_MASK) 4332 /*! @} */ 4333 4334 /* The count of MSCAN_TEDSR */ 4335 #define MSCAN_TEDSR_COUNT (8U) 4336 4337 /*! @name TDLR - Transmit Data Length Register */ 4338 /*! @{ */ 4339 #define MSCAN_TDLR_TDLC_MASK (0xFU) 4340 #define MSCAN_TDLR_TDLC_SHIFT (0U) 4341 /*! TDLC - Data Length Code Bits 4342 * 0b0000..0 4343 * 0b0001..1 4344 * 0b0010..2 4345 * 0b0011..3 4346 * 0b0100..4 4347 * 0b0101..5 4348 * 0b0110..6 4349 * 0b0111..7 4350 * 0b1000..8 4351 */ 4352 #define MSCAN_TDLR_TDLC(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TDLR_TDLC_SHIFT)) & MSCAN_TDLR_TDLC_MASK) 4353 /*! @} */ 4354 4355 /*! @name TBPR - Transmit Buffer Priority Register */ 4356 /*! @{ */ 4357 #define MSCAN_TBPR_PRIO_MASK (0xFFU) 4358 #define MSCAN_TBPR_PRIO_SHIFT (0U) 4359 #define MSCAN_TBPR_PRIO(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TBPR_PRIO_SHIFT)) & MSCAN_TBPR_PRIO_MASK) 4360 /*! @} */ 4361 4362 /*! @name TTSRH - Transmit Time Stamp Register High */ 4363 /*! @{ */ 4364 #define MSCAN_TTSRH_TTS_MASK (0xFFU) 4365 #define MSCAN_TTSRH_TTS_SHIFT (0U) 4366 #define MSCAN_TTSRH_TTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TTSRH_TTS_SHIFT)) & MSCAN_TTSRH_TTS_MASK) 4367 /*! @} */ 4368 4369 /*! @name TTSRL - Transmit Time Stamp Register Low */ 4370 /*! @{ */ 4371 #define MSCAN_TTSRL_TTS_MASK (0xFFU) 4372 #define MSCAN_TTSRL_TTS_SHIFT (0U) 4373 #define MSCAN_TTSRL_TTS(x) (((uint8_t)(((uint8_t)(x)) << MSCAN_TTSRL_TTS_SHIFT)) & MSCAN_TTSRL_TTS_MASK) 4374 /*! @} */ 4375 4376 4377 /*! 4378 * @} 4379 */ /* end of group MSCAN_Register_Masks */ 4380 4381 4382 /* MSCAN - Peripheral instance base addresses */ 4383 /** Peripheral MSCAN base address */ 4384 #define MSCAN_BASE (0x40024000u) 4385 /** Peripheral MSCAN base pointer */ 4386 #define MSCAN ((MSCAN_Type *)MSCAN_BASE) 4387 /** Array initializer of MSCAN peripheral base addresses */ 4388 #define MSCAN_BASE_ADDRS { MSCAN_BASE } 4389 /** Array initializer of MSCAN peripheral base pointers */ 4390 #define MSCAN_BASE_PTRS { MSCAN } 4391 /** Interrupt vectors for the MSCAN peripheral type */ 4392 #define MSCAN_RX_IRQS { MSCAN_1_IRQn } 4393 #define MSCAN_TX_IRQS { MSCAN_2_IRQn } 4394 #define MSCAN_ERR_IRQS { MSCAN_2_IRQn } 4395 #define MSCAN_WAKE_UP_IRQS { MSCAN_2_IRQn } 4396 4397 /*! 4398 * @} 4399 */ /* end of group MSCAN_Peripheral_Access_Layer */ 4400 4401 4402 /* ---------------------------------------------------------------------------- 4403 -- OSC Peripheral Access Layer 4404 ---------------------------------------------------------------------------- */ 4405 4406 /*! 4407 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 4408 * @{ 4409 */ 4410 4411 /** OSC - Register Layout Typedef */ 4412 typedef struct { 4413 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 4414 } OSC_Type; 4415 4416 /* ---------------------------------------------------------------------------- 4417 -- OSC Register Masks 4418 ---------------------------------------------------------------------------- */ 4419 4420 /*! 4421 * @addtogroup OSC_Register_Masks OSC Register Masks 4422 * @{ 4423 */ 4424 4425 /*! @name CR - OSC Control Register */ 4426 /*! @{ */ 4427 #define OSC_CR_OSCINIT_MASK (0x1U) 4428 #define OSC_CR_OSCINIT_SHIFT (0U) 4429 /*! OSCINIT - OSC Initialization 4430 * 0b0..Oscillator initialization is not complete. 4431 * 0b1..Oscillator initialization is completed. 4432 */ 4433 #define OSC_CR_OSCINIT(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCINIT_SHIFT)) & OSC_CR_OSCINIT_MASK) 4434 #define OSC_CR_HGO_MASK (0x2U) 4435 #define OSC_CR_HGO_SHIFT (1U) 4436 /*! HGO - High Gain Oscillator Select 4437 * 0b0..Low-power mode 4438 * 0b1..High-gain mode 4439 */ 4440 #define OSC_CR_HGO(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_HGO_SHIFT)) & OSC_CR_HGO_MASK) 4441 #define OSC_CR_RANGE_MASK (0x4U) 4442 #define OSC_CR_RANGE_SHIFT (2U) 4443 /*! RANGE - Frequency Range Select 4444 * 0b0..Low frequency range of 32 kHz. 4445 * 0b1..High frequency range of 4-24 MHz. 4446 */ 4447 #define OSC_CR_RANGE(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_RANGE_SHIFT)) & OSC_CR_RANGE_MASK) 4448 #define OSC_CR_OSCOS_MASK (0x10U) 4449 #define OSC_CR_OSCOS_SHIFT (4U) 4450 /*! OSCOS - OSC Output Select 4451 * 0b0..External clock source from EXTAL pin is selected. 4452 * 0b1..Oscillator clock source is selected. 4453 */ 4454 #define OSC_CR_OSCOS(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCOS_SHIFT)) & OSC_CR_OSCOS_MASK) 4455 #define OSC_CR_OSCSTEN_MASK (0x20U) 4456 #define OSC_CR_OSCSTEN_SHIFT (5U) 4457 /*! OSCSTEN - OSC Enable in Stop mode 4458 * 0b0..OSC clock is disabled in Stop mode. 4459 * 0b1..OSC clock stays enabled in Stop mode. 4460 */ 4461 #define OSC_CR_OSCSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCSTEN_SHIFT)) & OSC_CR_OSCSTEN_MASK) 4462 #define OSC_CR_OSCEN_MASK (0x80U) 4463 #define OSC_CR_OSCEN_SHIFT (7U) 4464 /*! OSCEN - OSC Enable 4465 * 0b0..OSC module is disabled. 4466 * 0b1..OSC module is enabled. 4467 */ 4468 #define OSC_CR_OSCEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_OSCEN_SHIFT)) & OSC_CR_OSCEN_MASK) 4469 /*! @} */ 4470 4471 4472 /*! 4473 * @} 4474 */ /* end of group OSC_Register_Masks */ 4475 4476 4477 /* OSC - Peripheral instance base addresses */ 4478 /** Peripheral OSC base address */ 4479 #define OSC_BASE (0x40065000u) 4480 /** Peripheral OSC base pointer */ 4481 #define OSC ((OSC_Type *)OSC_BASE) 4482 /** Array initializer of OSC peripheral base addresses */ 4483 #define OSC_BASE_ADDRS { OSC_BASE } 4484 /** Array initializer of OSC peripheral base pointers */ 4485 #define OSC_BASE_PTRS { OSC } 4486 4487 /*! 4488 * @} 4489 */ /* end of group OSC_Peripheral_Access_Layer */ 4490 4491 4492 /* ---------------------------------------------------------------------------- 4493 -- PIT Peripheral Access Layer 4494 ---------------------------------------------------------------------------- */ 4495 4496 /*! 4497 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 4498 * @{ 4499 */ 4500 4501 /** PIT - Register Layout Typedef */ 4502 typedef struct { 4503 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 4504 uint8_t RESERVED_0[252]; 4505 struct { /* offset: 0x100, array step: 0x10 */ 4506 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 4507 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 4508 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 4509 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 4510 } CHANNEL[2]; 4511 } PIT_Type; 4512 4513 /* ---------------------------------------------------------------------------- 4514 -- PIT Register Masks 4515 ---------------------------------------------------------------------------- */ 4516 4517 /*! 4518 * @addtogroup PIT_Register_Masks PIT Register Masks 4519 * @{ 4520 */ 4521 4522 /*! @name MCR - PIT Module Control Register */ 4523 /*! @{ */ 4524 #define PIT_MCR_FRZ_MASK (0x1U) 4525 #define PIT_MCR_FRZ_SHIFT (0U) 4526 /*! FRZ - Freeze 4527 * 0b0..Timers continue to run in Debug mode. 4528 * 0b1..Timers are stopped in Debug mode. 4529 */ 4530 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 4531 #define PIT_MCR_MDIS_MASK (0x2U) 4532 #define PIT_MCR_MDIS_SHIFT (1U) 4533 /*! MDIS - Module Disable - (PIT section) 4534 * 0b0..Clock for standard PIT timers is enabled. 4535 * 0b1..Clock for standard PIT timers is disabled. 4536 */ 4537 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 4538 /*! @} */ 4539 4540 /*! @name LDVAL - Timer Load Value Register */ 4541 /*! @{ */ 4542 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 4543 #define PIT_LDVAL_TSV_SHIFT (0U) 4544 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 4545 /*! @} */ 4546 4547 /* The count of PIT_LDVAL */ 4548 #define PIT_LDVAL_COUNT (2U) 4549 4550 /*! @name CVAL - Current Timer Value Register */ 4551 /*! @{ */ 4552 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 4553 #define PIT_CVAL_TVL_SHIFT (0U) 4554 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 4555 /*! @} */ 4556 4557 /* The count of PIT_CVAL */ 4558 #define PIT_CVAL_COUNT (2U) 4559 4560 /*! @name TCTRL - Timer Control Register */ 4561 /*! @{ */ 4562 #define PIT_TCTRL_TEN_MASK (0x1U) 4563 #define PIT_TCTRL_TEN_SHIFT (0U) 4564 /*! TEN - Timer Enable 4565 * 0b0..Timer n is disabled. 4566 * 0b1..Timer n is enabled. 4567 */ 4568 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 4569 #define PIT_TCTRL_TIE_MASK (0x2U) 4570 #define PIT_TCTRL_TIE_SHIFT (1U) 4571 /*! TIE - Timer Interrupt Enable 4572 * 0b0..Interrupt requests from Timer n are disabled. 4573 * 0b1..Interrupt will be requested whenever TIF is set. 4574 */ 4575 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 4576 #define PIT_TCTRL_CHN_MASK (0x4U) 4577 #define PIT_TCTRL_CHN_SHIFT (2U) 4578 /*! CHN - Chain Mode 4579 * 0b0..Timer is not chained. 4580 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. 4581 */ 4582 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 4583 /*! @} */ 4584 4585 /* The count of PIT_TCTRL */ 4586 #define PIT_TCTRL_COUNT (2U) 4587 4588 /*! @name TFLG - Timer Flag Register */ 4589 /*! @{ */ 4590 #define PIT_TFLG_TIF_MASK (0x1U) 4591 #define PIT_TFLG_TIF_SHIFT (0U) 4592 /*! TIF - Timer Interrupt Flag 4593 * 0b0..Timeout has not yet occurred. 4594 * 0b1..Timeout has occurred. 4595 */ 4596 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 4597 /*! @} */ 4598 4599 /* The count of PIT_TFLG */ 4600 #define PIT_TFLG_COUNT (2U) 4601 4602 4603 /*! 4604 * @} 4605 */ /* end of group PIT_Register_Masks */ 4606 4607 4608 /* PIT - Peripheral instance base addresses */ 4609 /** Peripheral PIT base address */ 4610 #define PIT_BASE (0x40037000u) 4611 /** Peripheral PIT base pointer */ 4612 #define PIT ((PIT_Type *)PIT_BASE) 4613 /** Array initializer of PIT peripheral base addresses */ 4614 #define PIT_BASE_ADDRS { PIT_BASE } 4615 /** Array initializer of PIT peripheral base pointers */ 4616 #define PIT_BASE_PTRS { PIT } 4617 /** Interrupt vectors for the PIT peripheral type */ 4618 #define PIT_IRQS { { PIT_CH0_IRQn, PIT_CH1_IRQn } } 4619 4620 /*! 4621 * @} 4622 */ /* end of group PIT_Peripheral_Access_Layer */ 4623 4624 4625 /* ---------------------------------------------------------------------------- 4626 -- PMC Peripheral Access Layer 4627 ---------------------------------------------------------------------------- */ 4628 4629 /*! 4630 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 4631 * @{ 4632 */ 4633 4634 /** PMC - Register Layout Typedef */ 4635 typedef struct { 4636 __IO uint8_t SPMSC1; /**< System Power Management Status and Control 1 Register, offset: 0x0 */ 4637 __IO uint8_t SPMSC2; /**< System Power Management Status and Control 2 Register, offset: 0x1 */ 4638 } PMC_Type; 4639 4640 /* ---------------------------------------------------------------------------- 4641 -- PMC Register Masks 4642 ---------------------------------------------------------------------------- */ 4643 4644 /*! 4645 * @addtogroup PMC_Register_Masks PMC Register Masks 4646 * @{ 4647 */ 4648 4649 /*! @name SPMSC1 - System Power Management Status and Control 1 Register */ 4650 /*! @{ */ 4651 #define PMC_SPMSC1_BGBE_MASK (0x1U) 4652 #define PMC_SPMSC1_BGBE_SHIFT (0U) 4653 /*! BGBE - Bandgap Buffer Enable 4654 * 0b0..Bandgap buffer is disabled. 4655 * 0b1..Bandgap buffer is enabled. 4656 */ 4657 #define PMC_SPMSC1_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_BGBE_SHIFT)) & PMC_SPMSC1_BGBE_MASK) 4658 #define PMC_SPMSC1_LVDE_MASK (0x4U) 4659 #define PMC_SPMSC1_LVDE_SHIFT (2U) 4660 /*! LVDE - Low-Voltage Detect Enable 4661 * 0b0..LVD logic is disabled. 4662 * 0b1..LVD logic is enabled. 4663 */ 4664 #define PMC_SPMSC1_LVDE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDE_SHIFT)) & PMC_SPMSC1_LVDE_MASK) 4665 #define PMC_SPMSC1_LVDSE_MASK (0x8U) 4666 #define PMC_SPMSC1_LVDSE_SHIFT (3U) 4667 /*! LVDSE - Low-Voltage Detect Stop Enable 4668 * 0b0..Low-voltage detect is disabled during Stop mode. 4669 * 0b1..Low-voltage detect is enabled during Stop mode. 4670 */ 4671 #define PMC_SPMSC1_LVDSE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDSE_SHIFT)) & PMC_SPMSC1_LVDSE_MASK) 4672 #define PMC_SPMSC1_LVDRE_MASK (0x10U) 4673 #define PMC_SPMSC1_LVDRE_SHIFT (4U) 4674 /*! LVDRE - Low-Voltage Detect Reset Enable 4675 * 0b0..LVD events do not generate hardware resets. 4676 * 0b1..Forces an MCU reset when an enabled low-voltage detect event occurs. 4677 */ 4678 #define PMC_SPMSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVDRE_SHIFT)) & PMC_SPMSC1_LVDRE_MASK) 4679 #define PMC_SPMSC1_LVWIE_MASK (0x20U) 4680 #define PMC_SPMSC1_LVWIE_SHIFT (5U) 4681 /*! LVWIE - Low-Voltage Warning Interrupt Enable 4682 * 0b0..Hardware interrupt is disabled (use polling). 4683 * 0b1..Requests a hardware interrupt when LVWF = 1. 4684 */ 4685 #define PMC_SPMSC1_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWIE_SHIFT)) & PMC_SPMSC1_LVWIE_MASK) 4686 #define PMC_SPMSC1_LVWACK_MASK (0x40U) 4687 #define PMC_SPMSC1_LVWACK_SHIFT (6U) 4688 #define PMC_SPMSC1_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWACK_SHIFT)) & PMC_SPMSC1_LVWACK_MASK) 4689 #define PMC_SPMSC1_LVWF_MASK (0x80U) 4690 #define PMC_SPMSC1_LVWF_SHIFT (7U) 4691 /*! LVWF - Low-Voltage Warning Flag 4692 * 0b0..Low-voltage warning is not present. 4693 * 0b1..Low-voltage warning is present or was present. 4694 */ 4695 #define PMC_SPMSC1_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC1_LVWF_SHIFT)) & PMC_SPMSC1_LVWF_MASK) 4696 /*! @} */ 4697 4698 /*! @name SPMSC2 - System Power Management Status and Control 2 Register */ 4699 /*! @{ */ 4700 #define PMC_SPMSC2_LVWV_MASK (0x30U) 4701 #define PMC_SPMSC2_LVWV_SHIFT (4U) 4702 /*! LVWV - Low-Voltage Warning Voltage Select 4703 * 0b00..Low trip point is selected (VLVW = VLVW1). 4704 * 0b01..Middle 1 trip point is selected (VLVW = VLVW2). 4705 * 0b10..Middle 2 trip point is selected (VLVW = VLVW3). 4706 * 0b11..High trip point is selected (VLVW = VLVW4). 4707 */ 4708 #define PMC_SPMSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC2_LVWV_SHIFT)) & PMC_SPMSC2_LVWV_MASK) 4709 #define PMC_SPMSC2_LVDV_MASK (0x40U) 4710 #define PMC_SPMSC2_LVDV_SHIFT (6U) 4711 /*! LVDV - Low-Voltage Detect Voltage Select 4712 * 0b0..Low trip point is selected (VLVD = VLVDL). 4713 * 0b1..High trip point is selected (VLVD = VLVDH). 4714 */ 4715 #define PMC_SPMSC2_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_SPMSC2_LVDV_SHIFT)) & PMC_SPMSC2_LVDV_MASK) 4716 /*! @} */ 4717 4718 4719 /*! 4720 * @} 4721 */ /* end of group PMC_Register_Masks */ 4722 4723 4724 /* PMC - Peripheral instance base addresses */ 4725 /** Peripheral PMC base address */ 4726 #define PMC_BASE (0x4007D000u) 4727 /** Peripheral PMC base pointer */ 4728 #define PMC ((PMC_Type *)PMC_BASE) 4729 /** Array initializer of PMC peripheral base addresses */ 4730 #define PMC_BASE_ADDRS { PMC_BASE } 4731 /** Array initializer of PMC peripheral base pointers */ 4732 #define PMC_BASE_PTRS { PMC } 4733 /** Interrupt vectors for the PMC peripheral type */ 4734 #define PMC_IRQS { PMC_IRQn } 4735 4736 /*! 4737 * @} 4738 */ /* end of group PMC_Peripheral_Access_Layer */ 4739 4740 4741 /* ---------------------------------------------------------------------------- 4742 -- PORT Peripheral Access Layer 4743 ---------------------------------------------------------------------------- */ 4744 4745 /*! 4746 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 4747 * @{ 4748 */ 4749 4750 /** PORT - Register Layout Typedef */ 4751 typedef struct { 4752 __IO uint32_t IOFLT0; /**< Port Filter Register 0, offset: 0x0 */ 4753 __IO uint32_t IOFLT1; /**< Port Filter Register 1, offset: 0x4 */ 4754 __IO uint32_t PUE0; /**< Port Pullup Enable Register 0, offset: 0x8 */ 4755 __IO uint32_t PUE1; /**< Port Pullup Enable Register 1, offset: 0xC */ 4756 __IO uint32_t PUE2; /**< Port Pullup Enable Register 2, offset: 0x10 */ 4757 __IO uint32_t HDRVE; /**< Port High Drive Enable Register, offset: 0x14 */ 4758 } PORT_Type; 4759 4760 /* ---------------------------------------------------------------------------- 4761 -- PORT Register Masks 4762 ---------------------------------------------------------------------------- */ 4763 4764 /*! 4765 * @addtogroup PORT_Register_Masks PORT Register Masks 4766 * @{ 4767 */ 4768 4769 /*! @name IOFLT0 - Port Filter Register 0 */ 4770 /*! @{ */ 4771 #define PORT_IOFLT0_FLTA_MASK (0x3U) 4772 #define PORT_IOFLT0_FLTA_SHIFT (0U) 4773 /*! FLTA - Filter Selection for Input from PTA 4774 * 0b00..BUSCLK 4775 * 0b01..FLTDIV1 4776 * 0b10..FLTDIV2 4777 * 0b11..FLTDIV3 4778 */ 4779 #define PORT_IOFLT0_FLTA(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTA_SHIFT)) & PORT_IOFLT0_FLTA_MASK) 4780 #define PORT_IOFLT0_FLTB_MASK (0xCU) 4781 #define PORT_IOFLT0_FLTB_SHIFT (2U) 4782 /*! FLTB - Filter Selection for Input from PTB 4783 * 0b00..BUSCLK 4784 * 0b01..FLTDIV1 4785 * 0b10..FLTDIV2 4786 * 0b11..FLTDIV3 4787 */ 4788 #define PORT_IOFLT0_FLTB(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTB_SHIFT)) & PORT_IOFLT0_FLTB_MASK) 4789 #define PORT_IOFLT0_FLTC_MASK (0x30U) 4790 #define PORT_IOFLT0_FLTC_SHIFT (4U) 4791 /*! FLTC - Filter Selection for Input from PTC 4792 * 0b00..BUSCLK 4793 * 0b01..FLTDIV1 4794 * 0b10..FLTDIV2 4795 * 0b11..FLTDIV3 4796 */ 4797 #define PORT_IOFLT0_FLTC(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTC_SHIFT)) & PORT_IOFLT0_FLTC_MASK) 4798 #define PORT_IOFLT0_FLTD_MASK (0xC0U) 4799 #define PORT_IOFLT0_FLTD_SHIFT (6U) 4800 /*! FLTD - Filter Selection for Input from PTD 4801 * 0b00..BUSCLK 4802 * 0b01..FLTDIV1 4803 * 0b10..FLTDIV2 4804 * 0b11..FLTDIV3 4805 */ 4806 #define PORT_IOFLT0_FLTD(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTD_SHIFT)) & PORT_IOFLT0_FLTD_MASK) 4807 #define PORT_IOFLT0_FLTE_MASK (0x300U) 4808 #define PORT_IOFLT0_FLTE_SHIFT (8U) 4809 /*! FLTE - Filter Selection for Input from PTD 4810 * 0b00..BUSCLK 4811 * 0b01..FLTDIV1 4812 * 0b10..FLTDIV2 4813 * 0b11..FLTDIV3 4814 */ 4815 #define PORT_IOFLT0_FLTE(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTE_SHIFT)) & PORT_IOFLT0_FLTE_MASK) 4816 #define PORT_IOFLT0_FLTF_MASK (0xC00U) 4817 #define PORT_IOFLT0_FLTF_SHIFT (10U) 4818 /*! FLTF - Filter Selection for Input from PTF 4819 * 0b00..BUSCLK 4820 * 0b01..FLTDIV1 4821 * 0b10..FLTDIV2 4822 * 0b11..FLTDIV3 4823 */ 4824 #define PORT_IOFLT0_FLTF(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTF_SHIFT)) & PORT_IOFLT0_FLTF_MASK) 4825 #define PORT_IOFLT0_FLTG_MASK (0x3000U) 4826 #define PORT_IOFLT0_FLTG_SHIFT (12U) 4827 /*! FLTG - Filter Selection for Input from PTG 4828 * 0b00..BUSCLK 4829 * 0b01..FLTDIV1 4830 * 0b10..FLTDIV2 4831 * 0b11..FLTDIV3 4832 */ 4833 #define PORT_IOFLT0_FLTG(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTG_SHIFT)) & PORT_IOFLT0_FLTG_MASK) 4834 #define PORT_IOFLT0_FLTH_MASK (0xC000U) 4835 #define PORT_IOFLT0_FLTH_SHIFT (14U) 4836 /*! FLTH - Filter Selection for Input from PTH 4837 * 0b00..BUSCLK 4838 * 0b01..FLTDIV1 4839 * 0b10..FLTDIV2 4840 * 0b11..FLTDIV3 4841 */ 4842 #define PORT_IOFLT0_FLTH(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTH_SHIFT)) & PORT_IOFLT0_FLTH_MASK) 4843 #define PORT_IOFLT0_FLTRST_MASK (0x30000U) 4844 #define PORT_IOFLT0_FLTRST_SHIFT (16U) 4845 /*! FLTRST - Filter Selection for Input from RESET/IRQ 4846 * 0b00..No filter. 4847 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4848 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4849 * 0b11..FLTDIV3 4850 */ 4851 #define PORT_IOFLT0_FLTRST(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTRST_SHIFT)) & PORT_IOFLT0_FLTRST_MASK) 4852 #define PORT_IOFLT0_FLTKBI0_MASK (0xC0000U) 4853 #define PORT_IOFLT0_FLTKBI0_SHIFT (18U) 4854 /*! FLTKBI0 - Filter selection for Input from KBI0 4855 * 0b00..No filter. 4856 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4857 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4858 * 0b11..FLTDIV3 4859 */ 4860 #define PORT_IOFLT0_FLTKBI0(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTKBI0_SHIFT)) & PORT_IOFLT0_FLTKBI0_MASK) 4861 #define PORT_IOFLT0_FLTKBI1_MASK (0x300000U) 4862 #define PORT_IOFLT0_FLTKBI1_SHIFT (20U) 4863 /*! FLTKBI1 - Filter Selection for Input from KBI1 4864 * 0b00..No filter 4865 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4866 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4867 * 0b11..FLTDIV3 4868 */ 4869 #define PORT_IOFLT0_FLTKBI1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTKBI1_SHIFT)) & PORT_IOFLT0_FLTKBI1_MASK) 4870 #define PORT_IOFLT0_FLTNMI_MASK (0xC00000U) 4871 #define PORT_IOFLT0_FLTNMI_SHIFT (22U) 4872 /*! FLTNMI - Filter Selection for Input from NMI 4873 * 0b00..No filter. 4874 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4875 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4876 * 0b11..FLTDIV3 4877 */ 4878 #define PORT_IOFLT0_FLTNMI(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTNMI_SHIFT)) & PORT_IOFLT0_FLTNMI_MASK) 4879 #define PORT_IOFLT0_FLTDIV1_MASK (0x3000000U) 4880 #define PORT_IOFLT0_FLTDIV1_SHIFT (24U) 4881 /*! FLTDIV1 - Filter Division Set 1 4882 * 0b00..BUSCLK/2 4883 * 0b01..BUSCLK/4 4884 * 0b10..BUSCLK/8 4885 * 0b11..BUSCLK/16 4886 */ 4887 #define PORT_IOFLT0_FLTDIV1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTDIV1_SHIFT)) & PORT_IOFLT0_FLTDIV1_MASK) 4888 #define PORT_IOFLT0_FLTDIV2_MASK (0x1C000000U) 4889 #define PORT_IOFLT0_FLTDIV2_SHIFT (26U) 4890 /*! FLTDIV2 - Filter Division Set 2 4891 * 0b000..BUSCLK/32 4892 * 0b001..BUSCLK/64 4893 * 0b010..BUSCLK/128 4894 * 0b011..BUSCLK/256 4895 * 0b100..BUSCLK/512 4896 * 0b101..BUSCLK/1024 4897 * 0b110..BUSCLK/2048 4898 * 0b111..BUSCLK/4096 4899 */ 4900 #define PORT_IOFLT0_FLTDIV2(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTDIV2_SHIFT)) & PORT_IOFLT0_FLTDIV2_MASK) 4901 #define PORT_IOFLT0_FLTDIV3_MASK (0xE0000000U) 4902 #define PORT_IOFLT0_FLTDIV3_SHIFT (29U) 4903 /*! FLTDIV3 - Filter Division Set 3 4904 * 0b000..LPOCLK 4905 * 0b001..LPOCLK/2 4906 * 0b010..LPOCLK/4 4907 * 0b011..LPOCLK/8 4908 * 0b100..LPOCLK/16 4909 * 0b101..LPOCLK/32 4910 * 0b110..LPOCLK/64 4911 * 0b111..LPOCLK/128 4912 */ 4913 #define PORT_IOFLT0_FLTDIV3(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT0_FLTDIV3_SHIFT)) & PORT_IOFLT0_FLTDIV3_MASK) 4914 /*! @} */ 4915 4916 /*! @name IOFLT1 - Port Filter Register 1 */ 4917 /*! @{ */ 4918 #define PORT_IOFLT1_FLTI_MASK (0x3U) 4919 #define PORT_IOFLT1_FLTI_SHIFT (0U) 4920 /*! FLTI - Filter Selection for Input from PTI 4921 * 0b00..BUSCLK 4922 * 0b01..FLTDIV1 4923 * 0b10..FLTDIV2 4924 * 0b11..FLTDIV3 4925 */ 4926 #define PORT_IOFLT1_FLTI(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTI_SHIFT)) & PORT_IOFLT1_FLTI_MASK) 4927 #define PORT_IOFLT1_FLTIRQ_MASK (0x30U) 4928 #define PORT_IOFLT1_FLTIRQ_SHIFT (4U) 4929 /*! FLTIRQ - Filter Selection for Input from IRQ 4930 * 0b00..No filter 4931 * 0b01..Selects FLTDIV1, and will switch to FLTDIV3 in Stop mode automatically. 4932 * 0b10..Selects FLTDIV2, and will switch to FLTDIV3 in Stop mode automatically. 4933 * 0b11..FLTDIV3 4934 */ 4935 #define PORT_IOFLT1_FLTIRQ(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTIRQ_SHIFT)) & PORT_IOFLT1_FLTIRQ_MASK) 4936 #define PORT_IOFLT1_FLTFTM0_MASK (0xC0U) 4937 #define PORT_IOFLT1_FLTFTM0_SHIFT (6U) 4938 /*! FLTFTM0 - Filter Selection For Input from FTM0CH0/FTM0CH1 4939 * 0b00..No filter 4940 * 0b01..Select FLTDIV1 4941 * 0b10..Select FLTDIV2 4942 * 0b11..Select FLTDIV3 4943 */ 4944 #define PORT_IOFLT1_FLTFTM0(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTFTM0_SHIFT)) & PORT_IOFLT1_FLTFTM0_MASK) 4945 #define PORT_IOFLT1_FLTFTM1_MASK (0x300U) 4946 #define PORT_IOFLT1_FLTFTM1_SHIFT (8U) 4947 /*! FLTFTM1 - Filter Selection For Input from FTM1CH0/FTM1CH1 4948 * 0b00..No filter 4949 * 0b01..Select FLTDIV1 4950 * 0b10..Select FLTDIV2 4951 * 0b11..Select FLTDIV3 4952 */ 4953 #define PORT_IOFLT1_FLTFTM1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTFTM1_SHIFT)) & PORT_IOFLT1_FLTFTM1_MASK) 4954 #define PORT_IOFLT1_FLTPWT_MASK (0xC00U) 4955 #define PORT_IOFLT1_FLTPWT_SHIFT (10U) 4956 /*! FLTPWT - Filter Selection For Input from PWT_IN1/PWT_IN0 4957 * 0b00..No filter 4958 * 0b01..Select FLTDIV1 4959 * 0b10..Select FLTDIV2 4960 * 0b11..Select FLTDIV3 4961 */ 4962 #define PORT_IOFLT1_FLTPWT(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTPWT_SHIFT)) & PORT_IOFLT1_FLTPWT_MASK) 4963 #define PORT_IOFLT1_FLTI2C0_MASK (0x3000U) 4964 #define PORT_IOFLT1_FLTI2C0_SHIFT (12U) 4965 /*! FLTI2C0 - Filter Selection For Input from SCL0/SDA0 4966 * 0b00..No filter 4967 * 0b01..Select FLTDIV1 4968 * 0b10..Select FLTDIV2 4969 * 0b11..Select BUSCLK 4970 */ 4971 #define PORT_IOFLT1_FLTI2C0(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTI2C0_SHIFT)) & PORT_IOFLT1_FLTI2C0_MASK) 4972 #define PORT_IOFLT1_FLTI2C1_MASK (0xC000U) 4973 #define PORT_IOFLT1_FLTI2C1_SHIFT (14U) 4974 /*! FLTI2C1 - Filter Selection For Input from SCL1/SDA1 4975 * 0b00..No filter 4976 * 0b01..Select FLTDIV1 4977 * 0b10..Select FLTDIV2 4978 * 0b11..Select BUSCLK 4979 */ 4980 #define PORT_IOFLT1_FLTI2C1(x) (((uint32_t)(((uint32_t)(x)) << PORT_IOFLT1_FLTI2C1_SHIFT)) & PORT_IOFLT1_FLTI2C1_MASK) 4981 /*! @} */ 4982 4983 /*! @name PUE0 - Port Pullup Enable Register 0 */ 4984 /*! @{ */ 4985 #define PORT_PUE0_PTAPE0_MASK (0x1U) 4986 #define PORT_PUE0_PTAPE0_SHIFT (0U) 4987 /*! PTAPE0 - Pull Enable for Port A Bit 0 4988 * 0b0..Pullup is disabled for port A bit 0. 4989 * 0b1..Pullup is enabled for port A bit 0. 4990 */ 4991 #define PORT_PUE0_PTAPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE0_SHIFT)) & PORT_PUE0_PTAPE0_MASK) 4992 #define PORT_PUE0_PTAPE1_MASK (0x2U) 4993 #define PORT_PUE0_PTAPE1_SHIFT (1U) 4994 /*! PTAPE1 - Pull Enable for Port A Bit 1 4995 * 0b0..Pullup is disabled for port A bit 1. 4996 * 0b1..Pullup is enabled for port A bit 1. 4997 */ 4998 #define PORT_PUE0_PTAPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE1_SHIFT)) & PORT_PUE0_PTAPE1_MASK) 4999 #define PORT_PUE0_PTAPE2_MASK (0x4U) 5000 #define PORT_PUE0_PTAPE2_SHIFT (2U) 5001 /*! PTAPE2 - Pull Enable for Port A Bit 2 5002 * 0b0..Pullup is disabled for port A bit 2. 5003 * 0b1..Pullup is enabled for port A bit 2. 5004 */ 5005 #define PORT_PUE0_PTAPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE2_SHIFT)) & PORT_PUE0_PTAPE2_MASK) 5006 #define PORT_PUE0_PTAPE3_MASK (0x8U) 5007 #define PORT_PUE0_PTAPE3_SHIFT (3U) 5008 /*! PTAPE3 - Pull Enable for Port A Bit 3 5009 * 0b0..Pullup is disabled for port A bit 3. 5010 * 0b1..Pullup is enabled for port A bit 3. 5011 */ 5012 #define PORT_PUE0_PTAPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE3_SHIFT)) & PORT_PUE0_PTAPE3_MASK) 5013 #define PORT_PUE0_PTAPE4_MASK (0x10U) 5014 #define PORT_PUE0_PTAPE4_SHIFT (4U) 5015 /*! PTAPE4 - Pull Enable for Port A Bit 4 5016 * 0b0..Pullup is disabled for port A bit 4. 5017 * 0b1..Pullup is enabled for port A bit 4. 5018 */ 5019 #define PORT_PUE0_PTAPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE4_SHIFT)) & PORT_PUE0_PTAPE4_MASK) 5020 #define PORT_PUE0_PTAPE5_MASK (0x20U) 5021 #define PORT_PUE0_PTAPE5_SHIFT (5U) 5022 /*! PTAPE5 - Pull Enable for Port A Bit 5 5023 * 0b0..Pullup is disabled for port A bit 5. 5024 * 0b1..Pullup is enabled for port A bit 5. 5025 */ 5026 #define PORT_PUE0_PTAPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE5_SHIFT)) & PORT_PUE0_PTAPE5_MASK) 5027 #define PORT_PUE0_PTAPE6_MASK (0x40U) 5028 #define PORT_PUE0_PTAPE6_SHIFT (6U) 5029 /*! PTAPE6 - Pull Enable for Port A Bit 6 5030 * 0b0..Pullup is disabled for port A bit 6. 5031 * 0b1..Pullup is enabled for port A bit 6. 5032 */ 5033 #define PORT_PUE0_PTAPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE6_SHIFT)) & PORT_PUE0_PTAPE6_MASK) 5034 #define PORT_PUE0_PTAPE7_MASK (0x80U) 5035 #define PORT_PUE0_PTAPE7_SHIFT (7U) 5036 /*! PTAPE7 - Pull Enable for Port A Bit 7 5037 * 0b0..Pullup is disabled for port A bit 7. 5038 * 0b1..Pullup is enabled for port A bit 7. 5039 */ 5040 #define PORT_PUE0_PTAPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTAPE7_SHIFT)) & PORT_PUE0_PTAPE7_MASK) 5041 #define PORT_PUE0_PTBPE0_MASK (0x100U) 5042 #define PORT_PUE0_PTBPE0_SHIFT (8U) 5043 /*! PTBPE0 - Pull Enable for Port B Bit 0 5044 * 0b0..Pullup is disabled for port B bit 0. 5045 * 0b1..Pullup is enabled for port B bit 0. 5046 */ 5047 #define PORT_PUE0_PTBPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE0_SHIFT)) & PORT_PUE0_PTBPE0_MASK) 5048 #define PORT_PUE0_PTBPE1_MASK (0x200U) 5049 #define PORT_PUE0_PTBPE1_SHIFT (9U) 5050 /*! PTBPE1 - Pull Enable for Port B Bit 1 5051 * 0b0..Pullup is disabled for port B bit 1. 5052 * 0b1..Pullup is enabled for port B bit 1. 5053 */ 5054 #define PORT_PUE0_PTBPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE1_SHIFT)) & PORT_PUE0_PTBPE1_MASK) 5055 #define PORT_PUE0_PTBPE2_MASK (0x400U) 5056 #define PORT_PUE0_PTBPE2_SHIFT (10U) 5057 /*! PTBPE2 - Pull Enable for Port B Bit 2 5058 * 0b0..Pullup is disabled for port B bit 2. 5059 * 0b1..Pullup is enabled for port B bit 2. 5060 */ 5061 #define PORT_PUE0_PTBPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE2_SHIFT)) & PORT_PUE0_PTBPE2_MASK) 5062 #define PORT_PUE0_PTBPE3_MASK (0x800U) 5063 #define PORT_PUE0_PTBPE3_SHIFT (11U) 5064 /*! PTBPE3 - Pull Enable for Port B Bit 3 5065 * 0b0..Pullup is disabled for port B bit 3. 5066 * 0b1..Pullup is enabled for port B bit 3. 5067 */ 5068 #define PORT_PUE0_PTBPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE3_SHIFT)) & PORT_PUE0_PTBPE3_MASK) 5069 #define PORT_PUE0_PTBPE4_MASK (0x1000U) 5070 #define PORT_PUE0_PTBPE4_SHIFT (12U) 5071 /*! PTBPE4 - Pull Enable for Port B Bit 4 5072 * 0b0..Pullup is disabled for port B bit 4. 5073 * 0b1..Pullup is enabled for port B bit 4. 5074 */ 5075 #define PORT_PUE0_PTBPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE4_SHIFT)) & PORT_PUE0_PTBPE4_MASK) 5076 #define PORT_PUE0_PTBPE5_MASK (0x2000U) 5077 #define PORT_PUE0_PTBPE5_SHIFT (13U) 5078 /*! PTBPE5 - Pull Enable for Port B Bit 5 5079 * 0b0..Pullup is disabled for port B bit 5. 5080 * 0b1..Pullup is enabled for port B bit 5. 5081 */ 5082 #define PORT_PUE0_PTBPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE5_SHIFT)) & PORT_PUE0_PTBPE5_MASK) 5083 #define PORT_PUE0_PTBPE6_MASK (0x4000U) 5084 #define PORT_PUE0_PTBPE6_SHIFT (14U) 5085 /*! PTBPE6 - Pull Enable for Port B Bit 6 5086 * 0b0..Pullup is disabled for port B bit 6. 5087 * 0b1..Pullup is enabled for port B bit 6. 5088 */ 5089 #define PORT_PUE0_PTBPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE6_SHIFT)) & PORT_PUE0_PTBPE6_MASK) 5090 #define PORT_PUE0_PTBPE7_MASK (0x8000U) 5091 #define PORT_PUE0_PTBPE7_SHIFT (15U) 5092 /*! PTBPE7 - Pull Enable for Port B Bit 7 5093 * 0b0..Pullup is disabled for port B bit 7. 5094 * 0b1..Pullup is enabled for port B bit 7. 5095 */ 5096 #define PORT_PUE0_PTBPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTBPE7_SHIFT)) & PORT_PUE0_PTBPE7_MASK) 5097 #define PORT_PUE0_PTCPE0_MASK (0x10000U) 5098 #define PORT_PUE0_PTCPE0_SHIFT (16U) 5099 /*! PTCPE0 - Pull Enable for Port C Bit 0 5100 * 0b0..Pullup is disabled for port C bit 0. 5101 * 0b1..Pullup is enabled for port C bit 0. 5102 */ 5103 #define PORT_PUE0_PTCPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE0_SHIFT)) & PORT_PUE0_PTCPE0_MASK) 5104 #define PORT_PUE0_PTCPE1_MASK (0x20000U) 5105 #define PORT_PUE0_PTCPE1_SHIFT (17U) 5106 /*! PTCPE1 - Pull Enable for Port C Bit 1 5107 * 0b0..Pullup is disabled for port C bit 1. 5108 * 0b1..Pullup is enabled for port C bit 1. 5109 */ 5110 #define PORT_PUE0_PTCPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE1_SHIFT)) & PORT_PUE0_PTCPE1_MASK) 5111 #define PORT_PUE0_PTCPE2_MASK (0x40000U) 5112 #define PORT_PUE0_PTCPE2_SHIFT (18U) 5113 /*! PTCPE2 - Pull Enable for Port C Bit 2 5114 * 0b0..Pullup is disabled for port C bit 2. 5115 * 0b1..Pullup is enabled for port C bit 2. 5116 */ 5117 #define PORT_PUE0_PTCPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE2_SHIFT)) & PORT_PUE0_PTCPE2_MASK) 5118 #define PORT_PUE0_PTCPE3_MASK (0x80000U) 5119 #define PORT_PUE0_PTCPE3_SHIFT (19U) 5120 /*! PTCPE3 - Pull Enable for Port C Bit 3 5121 * 0b0..Pullup is disabled for port C bit 3. 5122 * 0b1..Pullup is enabled for port C bit 3. 5123 */ 5124 #define PORT_PUE0_PTCPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE3_SHIFT)) & PORT_PUE0_PTCPE3_MASK) 5125 #define PORT_PUE0_PTCPE4_MASK (0x100000U) 5126 #define PORT_PUE0_PTCPE4_SHIFT (20U) 5127 /*! PTCPE4 - Pull Enable for Port C Bit 4 5128 * 0b0..Pullup is disabled for port C bit 4. 5129 * 0b1..Pullup is enabled for port C bit 4. 5130 */ 5131 #define PORT_PUE0_PTCPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE4_SHIFT)) & PORT_PUE0_PTCPE4_MASK) 5132 #define PORT_PUE0_PTCPE5_MASK (0x200000U) 5133 #define PORT_PUE0_PTCPE5_SHIFT (21U) 5134 /*! PTCPE5 - Pull Enable for Port C Bit 5 5135 * 0b0..Pullup is disabled for port C bit 5. 5136 * 0b1..Pullup is enabled for port C bit 5. 5137 */ 5138 #define PORT_PUE0_PTCPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE5_SHIFT)) & PORT_PUE0_PTCPE5_MASK) 5139 #define PORT_PUE0_PTCPE6_MASK (0x400000U) 5140 #define PORT_PUE0_PTCPE6_SHIFT (22U) 5141 /*! PTCPE6 - Pull Enable for Port C Bit 6 5142 * 0b0..Pullup is disabled for port C bit 6. 5143 * 0b1..Pullup is enabled for port C bit 6. 5144 */ 5145 #define PORT_PUE0_PTCPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE6_SHIFT)) & PORT_PUE0_PTCPE6_MASK) 5146 #define PORT_PUE0_PTCPE7_MASK (0x800000U) 5147 #define PORT_PUE0_PTCPE7_SHIFT (23U) 5148 /*! PTCPE7 - Pull Enable for Port C Bit 7 5149 * 0b0..Pullup is disabled for port C bit 7. 5150 * 0b1..Pullup is enabled for port C bit 7. 5151 */ 5152 #define PORT_PUE0_PTCPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTCPE7_SHIFT)) & PORT_PUE0_PTCPE7_MASK) 5153 #define PORT_PUE0_PTDPE0_MASK (0x1000000U) 5154 #define PORT_PUE0_PTDPE0_SHIFT (24U) 5155 /*! PTDPE0 - Pull Enable for Port D Bit 0 5156 * 0b0..Pullup is disabled for port D bit 0. 5157 * 0b1..Pullup is enabled for port D bit 0. 5158 */ 5159 #define PORT_PUE0_PTDPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE0_SHIFT)) & PORT_PUE0_PTDPE0_MASK) 5160 #define PORT_PUE0_PTDPE1_MASK (0x2000000U) 5161 #define PORT_PUE0_PTDPE1_SHIFT (25U) 5162 /*! PTDPE1 - Pull Enable for Port D Bit 1 5163 * 0b0..Pullup is disabled for port D bit 1. 5164 * 0b1..Pullup is enabled for port D bit 1. 5165 */ 5166 #define PORT_PUE0_PTDPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE1_SHIFT)) & PORT_PUE0_PTDPE1_MASK) 5167 #define PORT_PUE0_PTDPE2_MASK (0x4000000U) 5168 #define PORT_PUE0_PTDPE2_SHIFT (26U) 5169 /*! PTDPE2 - Pull Enable for Port D Bit 2 5170 * 0b0..Pullup is disabled for port D bit 2. 5171 * 0b1..Pullup is enabled for port D bit 2. 5172 */ 5173 #define PORT_PUE0_PTDPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE2_SHIFT)) & PORT_PUE0_PTDPE2_MASK) 5174 #define PORT_PUE0_PTDPE3_MASK (0x8000000U) 5175 #define PORT_PUE0_PTDPE3_SHIFT (27U) 5176 /*! PTDPE3 - Pull Enable for Port D Bit 3 5177 * 0b0..Pullup is disabled for port D bit 3. 5178 * 0b1..Pullup is enabled for port D bit 3. 5179 */ 5180 #define PORT_PUE0_PTDPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE3_SHIFT)) & PORT_PUE0_PTDPE3_MASK) 5181 #define PORT_PUE0_PTDPE4_MASK (0x10000000U) 5182 #define PORT_PUE0_PTDPE4_SHIFT (28U) 5183 /*! PTDPE4 - Pull Enable for Port D Bit 4 5184 * 0b0..Pullup is disabled for port D bit 4. 5185 * 0b1..Pullup is enabled for port D bit 4. 5186 */ 5187 #define PORT_PUE0_PTDPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE4_SHIFT)) & PORT_PUE0_PTDPE4_MASK) 5188 #define PORT_PUE0_PTDPE5_MASK (0x20000000U) 5189 #define PORT_PUE0_PTDPE5_SHIFT (29U) 5190 /*! PTDPE5 - Pull Enable for Port D Bit 5 5191 * 0b0..Pullup is disabled for port D bit 5. 5192 * 0b1..Pullup is enabled for port D bit 5. 5193 */ 5194 #define PORT_PUE0_PTDPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE5_SHIFT)) & PORT_PUE0_PTDPE5_MASK) 5195 #define PORT_PUE0_PTDPE6_MASK (0x40000000U) 5196 #define PORT_PUE0_PTDPE6_SHIFT (30U) 5197 /*! PTDPE6 - Pull Enable for Port D Bit 6 5198 * 0b0..Pullup is disabled for port D bit 6. 5199 * 0b1..Pullup is enabled for port D bit 6. 5200 */ 5201 #define PORT_PUE0_PTDPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE6_SHIFT)) & PORT_PUE0_PTDPE6_MASK) 5202 #define PORT_PUE0_PTDPE7_MASK (0x80000000U) 5203 #define PORT_PUE0_PTDPE7_SHIFT (31U) 5204 /*! PTDPE7 - Pull Enable for Port D Bit 7 5205 * 0b0..Pullup is disabled for port D bit 7. 5206 * 0b1..Pullup is enabled for port D bit 7. 5207 */ 5208 #define PORT_PUE0_PTDPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE0_PTDPE7_SHIFT)) & PORT_PUE0_PTDPE7_MASK) 5209 /*! @} */ 5210 5211 /*! @name PUE1 - Port Pullup Enable Register 1 */ 5212 /*! @{ */ 5213 #define PORT_PUE1_PTEPE0_MASK (0x1U) 5214 #define PORT_PUE1_PTEPE0_SHIFT (0U) 5215 /*! PTEPE0 - Pull Enable for Port E Bit 0 5216 * 0b0..Pullup is disabled for port E bit 0. 5217 * 0b1..Pullup is enabled for port E bit 0. 5218 */ 5219 #define PORT_PUE1_PTEPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE0_SHIFT)) & PORT_PUE1_PTEPE0_MASK) 5220 #define PORT_PUE1_PTEPE1_MASK (0x2U) 5221 #define PORT_PUE1_PTEPE1_SHIFT (1U) 5222 /*! PTEPE1 - Pull Enable for Port E Bit 1 5223 * 0b0..Pullup is disabled for port E bit 1. 5224 * 0b1..Pullup is enabled for port E bit 1. 5225 */ 5226 #define PORT_PUE1_PTEPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE1_SHIFT)) & PORT_PUE1_PTEPE1_MASK) 5227 #define PORT_PUE1_PTEPE2_MASK (0x4U) 5228 #define PORT_PUE1_PTEPE2_SHIFT (2U) 5229 /*! PTEPE2 - Pull Enable for Port E Bit 2 5230 * 0b0..Pullup is disabled for port E bit 2. 5231 * 0b1..Pullup is enabled for port E bit 2. 5232 */ 5233 #define PORT_PUE1_PTEPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE2_SHIFT)) & PORT_PUE1_PTEPE2_MASK) 5234 #define PORT_PUE1_PTEPE3_MASK (0x8U) 5235 #define PORT_PUE1_PTEPE3_SHIFT (3U) 5236 /*! PTEPE3 - Pull Enable for Port E Bit 3 5237 * 0b0..Pullup is disabled for port E bit 3. 5238 * 0b1..Pullup is enabled for port E bit 3. 5239 */ 5240 #define PORT_PUE1_PTEPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE3_SHIFT)) & PORT_PUE1_PTEPE3_MASK) 5241 #define PORT_PUE1_PTEPE4_MASK (0x10U) 5242 #define PORT_PUE1_PTEPE4_SHIFT (4U) 5243 /*! PTEPE4 - Pull Enable for Port E Bit 4 5244 * 0b0..Pullup is disabled for port E bit 4. 5245 * 0b1..Pullup is enabled for port E bit 4. 5246 */ 5247 #define PORT_PUE1_PTEPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE4_SHIFT)) & PORT_PUE1_PTEPE4_MASK) 5248 #define PORT_PUE1_PTEPE5_MASK (0x20U) 5249 #define PORT_PUE1_PTEPE5_SHIFT (5U) 5250 /*! PTEPE5 - Pull Enable for Port E Bit 5 5251 * 0b0..Pullup is disabled for port E bit 5. 5252 * 0b1..Pullup is enabled for port E bit 5. 5253 */ 5254 #define PORT_PUE1_PTEPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE5_SHIFT)) & PORT_PUE1_PTEPE5_MASK) 5255 #define PORT_PUE1_PTEPE6_MASK (0x40U) 5256 #define PORT_PUE1_PTEPE6_SHIFT (6U) 5257 /*! PTEPE6 - Pull Enable for Port E Bit 6 5258 * 0b0..Pullup is disabled for port E bit 6. 5259 * 0b1..Pullup is enabled for port E bit 6. 5260 */ 5261 #define PORT_PUE1_PTEPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE6_SHIFT)) & PORT_PUE1_PTEPE6_MASK) 5262 #define PORT_PUE1_PTEPE7_MASK (0x80U) 5263 #define PORT_PUE1_PTEPE7_SHIFT (7U) 5264 /*! PTEPE7 - Pull Enable for Port E Bit 7 5265 * 0b0..Pullup is disabled for port E bit 7. 5266 * 0b1..Pullup is enabled for port E bit 7. 5267 */ 5268 #define PORT_PUE1_PTEPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTEPE7_SHIFT)) & PORT_PUE1_PTEPE7_MASK) 5269 #define PORT_PUE1_PTFPE0_MASK (0x100U) 5270 #define PORT_PUE1_PTFPE0_SHIFT (8U) 5271 /*! PTFPE0 - Pull Enable for Port F Bit 0 5272 * 0b0..Pullup is disabled for port F bit 0. 5273 * 0b1..Pullup is enabled for port F bit 0. 5274 */ 5275 #define PORT_PUE1_PTFPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE0_SHIFT)) & PORT_PUE1_PTFPE0_MASK) 5276 #define PORT_PUE1_PTFPE1_MASK (0x200U) 5277 #define PORT_PUE1_PTFPE1_SHIFT (9U) 5278 /*! PTFPE1 - Pull Enable for Port F Bit 1 5279 * 0b0..Pullup is disabled for port F bit 1. 5280 * 0b1..Pullup is enabled for port F bit 1. 5281 */ 5282 #define PORT_PUE1_PTFPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE1_SHIFT)) & PORT_PUE1_PTFPE1_MASK) 5283 #define PORT_PUE1_PTFPE2_MASK (0x400U) 5284 #define PORT_PUE1_PTFPE2_SHIFT (10U) 5285 /*! PTFPE2 - Pull Enable for Port F Bit 2 5286 * 0b0..Pullup is disabled for port F bit 2. 5287 * 0b1..Pullup is enabled for port F bit 2. 5288 */ 5289 #define PORT_PUE1_PTFPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE2_SHIFT)) & PORT_PUE1_PTFPE2_MASK) 5290 #define PORT_PUE1_PTFPE3_MASK (0x800U) 5291 #define PORT_PUE1_PTFPE3_SHIFT (11U) 5292 /*! PTFPE3 - Pull Enable for Port F Bit 3 5293 * 0b0..Pullup is disabled for port F bit 3. 5294 * 0b1..Pullup is enabled for port F bit 3. 5295 */ 5296 #define PORT_PUE1_PTFPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE3_SHIFT)) & PORT_PUE1_PTFPE3_MASK) 5297 #define PORT_PUE1_PTFPE4_MASK (0x1000U) 5298 #define PORT_PUE1_PTFPE4_SHIFT (12U) 5299 /*! PTFPE4 - Pull Enable for Port F Bit 4 5300 * 0b0..Pullup is disabled for port F bit 4. 5301 * 0b1..Pullup is enabled for port F bit 4. 5302 */ 5303 #define PORT_PUE1_PTFPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE4_SHIFT)) & PORT_PUE1_PTFPE4_MASK) 5304 #define PORT_PUE1_PTFPE5_MASK (0x2000U) 5305 #define PORT_PUE1_PTFPE5_SHIFT (13U) 5306 /*! PTFPE5 - Pull Enable for Port F Bit 5 5307 * 0b0..Pullup is disabled for port F bit 5. 5308 * 0b1..Pullup is enabled for port F bit 5. 5309 */ 5310 #define PORT_PUE1_PTFPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE5_SHIFT)) & PORT_PUE1_PTFPE5_MASK) 5311 #define PORT_PUE1_PTFPE6_MASK (0x4000U) 5312 #define PORT_PUE1_PTFPE6_SHIFT (14U) 5313 /*! PTFPE6 - Pull Enable for Port F Bit 6 5314 * 0b0..Pullup is disabled for port F bit 6. 5315 * 0b1..Pullup is enabled for port F bit 6. 5316 */ 5317 #define PORT_PUE1_PTFPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE6_SHIFT)) & PORT_PUE1_PTFPE6_MASK) 5318 #define PORT_PUE1_PTFPE7_MASK (0x8000U) 5319 #define PORT_PUE1_PTFPE7_SHIFT (15U) 5320 /*! PTFPE7 - Pull Enable for Port F Bit 7 5321 * 0b0..Pullup is disabled for port F bit 7. 5322 * 0b1..Pullup is enabled for port F bit 7. 5323 */ 5324 #define PORT_PUE1_PTFPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTFPE7_SHIFT)) & PORT_PUE1_PTFPE7_MASK) 5325 #define PORT_PUE1_PTGPE0_MASK (0x10000U) 5326 #define PORT_PUE1_PTGPE0_SHIFT (16U) 5327 /*! PTGPE0 - Pull Enable for Port G Bit 0 5328 * 0b0..Pullup is disabled for port G bit 0. 5329 * 0b1..Pullup is enabled for port G bit 0. 5330 */ 5331 #define PORT_PUE1_PTGPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE0_SHIFT)) & PORT_PUE1_PTGPE0_MASK) 5332 #define PORT_PUE1_PTGPE1_MASK (0x20000U) 5333 #define PORT_PUE1_PTGPE1_SHIFT (17U) 5334 /*! PTGPE1 - Pull Enable for Port G Bit 1 5335 * 0b0..Pullup is disabled for port G bit 1. 5336 * 0b1..Pullup is enabled for port G bit 1. 5337 */ 5338 #define PORT_PUE1_PTGPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE1_SHIFT)) & PORT_PUE1_PTGPE1_MASK) 5339 #define PORT_PUE1_PTGPE2_MASK (0x40000U) 5340 #define PORT_PUE1_PTGPE2_SHIFT (18U) 5341 /*! PTGPE2 - Pull Enable for Port G Bit 2 5342 * 0b0..Pullup is disabled for port G bit 2. 5343 * 0b1..Pullup is enabled for port G bit 2. 5344 */ 5345 #define PORT_PUE1_PTGPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE2_SHIFT)) & PORT_PUE1_PTGPE2_MASK) 5346 #define PORT_PUE1_PTGPE3_MASK (0x80000U) 5347 #define PORT_PUE1_PTGPE3_SHIFT (19U) 5348 /*! PTGPE3 - Pull Enable for Port G Bit 3 5349 * 0b0..Pullup is disabled for port G bit 3. 5350 * 0b1..Pullup is enabled for port G bit 3. 5351 */ 5352 #define PORT_PUE1_PTGPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE3_SHIFT)) & PORT_PUE1_PTGPE3_MASK) 5353 #define PORT_PUE1_PTGPE4_MASK (0x100000U) 5354 #define PORT_PUE1_PTGPE4_SHIFT (20U) 5355 /*! PTGPE4 - Pull Enable for Port G Bit 4 5356 * 0b0..Pullup is disabled for port G bit 4. 5357 * 0b1..Pullup is enabled for port G bit 4. 5358 */ 5359 #define PORT_PUE1_PTGPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE4_SHIFT)) & PORT_PUE1_PTGPE4_MASK) 5360 #define PORT_PUE1_PTGPE5_MASK (0x200000U) 5361 #define PORT_PUE1_PTGPE5_SHIFT (21U) 5362 /*! PTGPE5 - Pull Enable for Port G Bit 5 5363 * 0b0..Pullup is disabled for port G bit 5. 5364 * 0b1..Pullup is enabled for port G bit 5. 5365 */ 5366 #define PORT_PUE1_PTGPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE5_SHIFT)) & PORT_PUE1_PTGPE5_MASK) 5367 #define PORT_PUE1_PTGPE6_MASK (0x400000U) 5368 #define PORT_PUE1_PTGPE6_SHIFT (22U) 5369 /*! PTGPE6 - Pull Enable for Port G Bit 6 5370 * 0b0..Pullup is disabled for port G bit 6. 5371 * 0b1..Pullup is enabled for port G bit 6. 5372 */ 5373 #define PORT_PUE1_PTGPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE6_SHIFT)) & PORT_PUE1_PTGPE6_MASK) 5374 #define PORT_PUE1_PTGPE7_MASK (0x800000U) 5375 #define PORT_PUE1_PTGPE7_SHIFT (23U) 5376 /*! PTGPE7 - Pull Enable for Port G Bit 7 5377 * 0b0..Pullup is disabled for port G bit 7. 5378 * 0b1..Pullup is enabled for port G bit 7. 5379 */ 5380 #define PORT_PUE1_PTGPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTGPE7_SHIFT)) & PORT_PUE1_PTGPE7_MASK) 5381 #define PORT_PUE1_PTHPE0_MASK (0x1000000U) 5382 #define PORT_PUE1_PTHPE0_SHIFT (24U) 5383 /*! PTHPE0 - Pull Enable for Port H Bit 0 5384 * 0b0..Pullup is disabled for port H bit 0. 5385 * 0b1..Pullup is enabled for port H bit 0. 5386 */ 5387 #define PORT_PUE1_PTHPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE0_SHIFT)) & PORT_PUE1_PTHPE0_MASK) 5388 #define PORT_PUE1_PTHPE1_MASK (0x2000000U) 5389 #define PORT_PUE1_PTHPE1_SHIFT (25U) 5390 /*! PTHPE1 - Pull Enable for Port H Bit 1 5391 * 0b0..Pullup is disabled for port H bit 1. 5392 * 0b1..Pullup is enabled for port H bit 1. 5393 */ 5394 #define PORT_PUE1_PTHPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE1_SHIFT)) & PORT_PUE1_PTHPE1_MASK) 5395 #define PORT_PUE1_PTHPE2_MASK (0x4000000U) 5396 #define PORT_PUE1_PTHPE2_SHIFT (26U) 5397 /*! PTHPE2 - Pull Enable for Port H Bit 2 5398 * 0b0..Pullup is disabled for port H bit 2. 5399 * 0b1..Pullup is enabled for port H bit 2. 5400 */ 5401 #define PORT_PUE1_PTHPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE2_SHIFT)) & PORT_PUE1_PTHPE2_MASK) 5402 #define PORT_PUE1_PTHPE3_MASK (0x8000000U) 5403 #define PORT_PUE1_PTHPE3_SHIFT (27U) 5404 /*! PTHPE3 - Pull Enable for Port H Bit 3 5405 * 0b0..Pullup is disabled for port H bit 3. 5406 * 0b1..Pullup is enabled for port H bit 3. 5407 */ 5408 #define PORT_PUE1_PTHPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE3_SHIFT)) & PORT_PUE1_PTHPE3_MASK) 5409 #define PORT_PUE1_PTHPE4_MASK (0x10000000U) 5410 #define PORT_PUE1_PTHPE4_SHIFT (28U) 5411 /*! PTHPE4 - Pull Enable for Port H Bit 4 5412 * 0b0..Pullup is disabled for port H bit 4. 5413 * 0b1..Pullup is enabled for port H bit 4. 5414 */ 5415 #define PORT_PUE1_PTHPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE4_SHIFT)) & PORT_PUE1_PTHPE4_MASK) 5416 #define PORT_PUE1_PTHPE5_MASK (0x20000000U) 5417 #define PORT_PUE1_PTHPE5_SHIFT (29U) 5418 /*! PTHPE5 - Pull Enable for Port H Bit 5 5419 * 0b0..Pullup is disabled for port H bit 5. 5420 * 0b1..Pullup is enabled for port H bit 5. 5421 */ 5422 #define PORT_PUE1_PTHPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE5_SHIFT)) & PORT_PUE1_PTHPE5_MASK) 5423 #define PORT_PUE1_PTHPE6_MASK (0x40000000U) 5424 #define PORT_PUE1_PTHPE6_SHIFT (30U) 5425 /*! PTHPE6 - Pull Enable for Port H Bit 6 5426 * 0b0..Pullup is disabled for port H bit 6. 5427 * 0b1..Pullup is enabled for port H bit 6. 5428 */ 5429 #define PORT_PUE1_PTHPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE6_SHIFT)) & PORT_PUE1_PTHPE6_MASK) 5430 #define PORT_PUE1_PTHPE7_MASK (0x80000000U) 5431 #define PORT_PUE1_PTHPE7_SHIFT (31U) 5432 /*! PTHPE7 - Pull Enable for Port H Bit 7 5433 * 0b0..Pullup is disabled for port H bit 7. 5434 * 0b1..Pullup is enabled for port H bit 7. 5435 */ 5436 #define PORT_PUE1_PTHPE7(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE1_PTHPE7_SHIFT)) & PORT_PUE1_PTHPE7_MASK) 5437 /*! @} */ 5438 5439 /*! @name PUE2 - Port Pullup Enable Register 2 */ 5440 /*! @{ */ 5441 #define PORT_PUE2_PTIPE0_MASK (0x1U) 5442 #define PORT_PUE2_PTIPE0_SHIFT (0U) 5443 /*! PTIPE0 - Pull Enable for Port I Bit 0 5444 * 0b0..Pullup is disabled for port I bit 0. 5445 * 0b1..Pullup is enabled for port I bit 0. 5446 */ 5447 #define PORT_PUE2_PTIPE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE0_SHIFT)) & PORT_PUE2_PTIPE0_MASK) 5448 #define PORT_PUE2_PTIPE1_MASK (0x2U) 5449 #define PORT_PUE2_PTIPE1_SHIFT (1U) 5450 /*! PTIPE1 - Pull Enable for Port I Bit 1 5451 * 0b0..Pullup is disabled for port I bit 1. 5452 * 0b1..Pullup is enabled for port I bit 1. 5453 */ 5454 #define PORT_PUE2_PTIPE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE1_SHIFT)) & PORT_PUE2_PTIPE1_MASK) 5455 #define PORT_PUE2_PTIPE2_MASK (0x4U) 5456 #define PORT_PUE2_PTIPE2_SHIFT (2U) 5457 /*! PTIPE2 - Pull Enable for Port I Bit 2 5458 * 0b0..Pullup is disabled for port I bit 2. 5459 * 0b1..Pullup is enabled for port I bit 2. 5460 */ 5461 #define PORT_PUE2_PTIPE2(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE2_SHIFT)) & PORT_PUE2_PTIPE2_MASK) 5462 #define PORT_PUE2_PTIPE3_MASK (0x8U) 5463 #define PORT_PUE2_PTIPE3_SHIFT (3U) 5464 /*! PTIPE3 - Pull Enable for Port I Bit 3 5465 * 0b0..Pullup is disabled for port I bit 3. 5466 * 0b1..Pullup is enabled for port I bit 3. 5467 */ 5468 #define PORT_PUE2_PTIPE3(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE3_SHIFT)) & PORT_PUE2_PTIPE3_MASK) 5469 #define PORT_PUE2_PTIPE4_MASK (0x10U) 5470 #define PORT_PUE2_PTIPE4_SHIFT (4U) 5471 /*! PTIPE4 - Pull Enable for Port I Bit 4 5472 * 0b0..Pullup is disabled for port I bit 4. 5473 * 0b1..Pullup is enabled for port I bit 4. 5474 */ 5475 #define PORT_PUE2_PTIPE4(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE4_SHIFT)) & PORT_PUE2_PTIPE4_MASK) 5476 #define PORT_PUE2_PTIPE5_MASK (0x20U) 5477 #define PORT_PUE2_PTIPE5_SHIFT (5U) 5478 /*! PTIPE5 - Pull Enable for Port I Bit 5 5479 * 0b0..Pullup is disabled for port I bit 5. 5480 * 0b1..Pullup is enabled for port I bit 5. 5481 */ 5482 #define PORT_PUE2_PTIPE5(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE5_SHIFT)) & PORT_PUE2_PTIPE5_MASK) 5483 #define PORT_PUE2_PTIPE6_MASK (0x40U) 5484 #define PORT_PUE2_PTIPE6_SHIFT (6U) 5485 /*! PTIPE6 - Pull Enable for Port I Bit 6 5486 * 0b0..Pullup is disabled for port I bit 6. 5487 * 0b1..Pullup is enabled for port I bit 6. 5488 */ 5489 #define PORT_PUE2_PTIPE6(x) (((uint32_t)(((uint32_t)(x)) << PORT_PUE2_PTIPE6_SHIFT)) & PORT_PUE2_PTIPE6_MASK) 5490 /*! @} */ 5491 5492 /*! @name HDRVE - Port High Drive Enable Register */ 5493 /*! @{ */ 5494 #define PORT_HDRVE_PTB4_MASK (0x1U) 5495 #define PORT_HDRVE_PTB4_SHIFT (0U) 5496 /*! PTB4 - High Current Drive Capability of PTB4 5497 * 0b0..PTB4 is disabled to offer high current drive capability. 5498 * 0b1..PTB4 is enabled to offer high current drive capability. 5499 */ 5500 #define PORT_HDRVE_PTB4(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTB4_SHIFT)) & PORT_HDRVE_PTB4_MASK) 5501 #define PORT_HDRVE_PTB5_MASK (0x2U) 5502 #define PORT_HDRVE_PTB5_SHIFT (1U) 5503 /*! PTB5 - High Current Drive Capability of PTB5 5504 * 0b0..PTB5 is disabled to offer high current drive capability. 5505 * 0b1..PTB5 is enabled to offer high current drive capability. 5506 */ 5507 #define PORT_HDRVE_PTB5(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTB5_SHIFT)) & PORT_HDRVE_PTB5_MASK) 5508 #define PORT_HDRVE_PTD0_MASK (0x4U) 5509 #define PORT_HDRVE_PTD0_SHIFT (2U) 5510 /*! PTD0 - High Current Drive Capability of PTD0 5511 * 0b0..PTD0 is disabled to offer high current drive capability. 5512 * 0b1..PTD0 is enabled to offer high current drive capability. 5513 */ 5514 #define PORT_HDRVE_PTD0(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTD0_SHIFT)) & PORT_HDRVE_PTD0_MASK) 5515 #define PORT_HDRVE_PTD1_MASK (0x8U) 5516 #define PORT_HDRVE_PTD1_SHIFT (3U) 5517 /*! PTD1 - High Current Drive Capability of PTD1 5518 * 0b0..PTD1 is disabled to offer high current drive capability. 5519 * 0b1..PTD1 is enable to offer high current drive capability. 5520 */ 5521 #define PORT_HDRVE_PTD1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTD1_SHIFT)) & PORT_HDRVE_PTD1_MASK) 5522 #define PORT_HDRVE_PTE0_MASK (0x10U) 5523 #define PORT_HDRVE_PTE0_SHIFT (4U) 5524 /*! PTE0 - High Current Drive Capability of PTE0 5525 * 0b0..PTE0 is disabled to offer high current drive capability. 5526 * 0b1..PTE0 is enable to offer high current drive capability. 5527 */ 5528 #define PORT_HDRVE_PTE0(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTE0_SHIFT)) & PORT_HDRVE_PTE0_MASK) 5529 #define PORT_HDRVE_PTE1_MASK (0x20U) 5530 #define PORT_HDRVE_PTE1_SHIFT (5U) 5531 /*! PTE1 - High Current Drive Capability of PTE1 5532 * 0b0..PTE1 is disabled to offer high current drive capability. 5533 * 0b1..PTE1 is enabled to offer high current drive capability. 5534 */ 5535 #define PORT_HDRVE_PTE1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTE1_SHIFT)) & PORT_HDRVE_PTE1_MASK) 5536 #define PORT_HDRVE_PTH0_MASK (0x40U) 5537 #define PORT_HDRVE_PTH0_SHIFT (6U) 5538 /*! PTH0 - High Current Drive Capability of PTH0 5539 * 0b0..PTH0 is disabled to offer high current drive capability. 5540 * 0b1..PTH0 is enabled to offer high current drive capability. 5541 */ 5542 #define PORT_HDRVE_PTH0(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTH0_SHIFT)) & PORT_HDRVE_PTH0_MASK) 5543 #define PORT_HDRVE_PTH1_MASK (0x80U) 5544 #define PORT_HDRVE_PTH1_SHIFT (7U) 5545 /*! PTH1 - High Current Drive Capability of PTH1 5546 * 0b0..PTH1 is disabled to offer high current drive capability. 5547 * 0b1..PTH1 is enabled to offer high current drive capability. 5548 */ 5549 #define PORT_HDRVE_PTH1(x) (((uint32_t)(((uint32_t)(x)) << PORT_HDRVE_PTH1_SHIFT)) & PORT_HDRVE_PTH1_MASK) 5550 /*! @} */ 5551 5552 5553 /*! 5554 * @} 5555 */ /* end of group PORT_Register_Masks */ 5556 5557 5558 /* PORT - Peripheral instance base addresses */ 5559 /** Peripheral PORT base address */ 5560 #define PORT_BASE (0x40049000u) 5561 /** Peripheral PORT base pointer */ 5562 #define PORT ((PORT_Type *)PORT_BASE) 5563 /** Array initializer of PORT peripheral base addresses */ 5564 #define PORT_BASE_ADDRS { PORT_BASE } 5565 /** Array initializer of PORT peripheral base pointers */ 5566 #define PORT_BASE_PTRS { PORT } 5567 5568 /*! 5569 * @} 5570 */ /* end of group PORT_Peripheral_Access_Layer */ 5571 5572 5573 /* ---------------------------------------------------------------------------- 5574 -- PWT Peripheral Access Layer 5575 ---------------------------------------------------------------------------- */ 5576 5577 /*! 5578 * @addtogroup PWT_Peripheral_Access_Layer PWT Peripheral Access Layer 5579 * @{ 5580 */ 5581 5582 /** PWT - Register Layout Typedef */ 5583 typedef struct { 5584 __IO uint32_t R1; /**< Pulse Width Timer Register 1, offset: 0x0 */ 5585 __I uint32_t R2; /**< Pulse Width Timer Register 2, offset: 0x4 */ 5586 } PWT_Type; 5587 5588 /* ---------------------------------------------------------------------------- 5589 -- PWT Register Masks 5590 ---------------------------------------------------------------------------- */ 5591 5592 /*! 5593 * @addtogroup PWT_Register_Masks PWT Register Masks 5594 * @{ 5595 */ 5596 5597 /*! @name R1 - Pulse Width Timer Register 1 */ 5598 /*! @{ */ 5599 #define PWT_R1_PWTOV_MASK (0x1U) 5600 #define PWT_R1_PWTOV_SHIFT (0U) 5601 /*! PWTOV - PWT Counter Overflow 5602 * 0b0..PWT counter no overflow. 5603 * 0b1..PWT counter runs from 0xFFFF to 0x0000. 5604 */ 5605 #define PWT_R1_PWTOV(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTOV_SHIFT)) & PWT_R1_PWTOV_MASK) 5606 #define PWT_R1_PWTRDY_MASK (0x2U) 5607 #define PWT_R1_PWTRDY_SHIFT (1U) 5608 /*! PWTRDY - PWT Pulse Width Valid 5609 * 0b0..PWT pulse width register(s) is not up-to-date. 5610 * 0b1..PWT pulse width register(s) has been updated. 5611 */ 5612 #define PWT_R1_PWTRDY(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTRDY_SHIFT)) & PWT_R1_PWTRDY_MASK) 5613 #define PWT_R1_PWTSR_MASK (0x8U) 5614 #define PWT_R1_PWTSR_SHIFT (3U) 5615 /*! PWTSR - PWT Soft Reset 5616 * 0b0..No action taken. 5617 * 0b1..Writing 1 to this field will perform soft reset to PWT. 5618 */ 5619 #define PWT_R1_PWTSR(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTSR_SHIFT)) & PWT_R1_PWTSR_MASK) 5620 #define PWT_R1_POVIE_MASK (0x10U) 5621 #define PWT_R1_POVIE_SHIFT (4U) 5622 /*! POVIE - PWT Counter Overflow Interrupt Enable 5623 * 0b0..Disable PWT to generate interrupt when PWTOV is set. 5624 * 0b1..Enable PWT to generate interrupt when PWTOV is set. 5625 */ 5626 #define PWT_R1_POVIE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_POVIE_SHIFT)) & PWT_R1_POVIE_MASK) 5627 #define PWT_R1_PRDYIE_MASK (0x20U) 5628 #define PWT_R1_PRDYIE_SHIFT (5U) 5629 /*! PRDYIE - PWT Pulse Width Data Ready Interrupt Enable 5630 * 0b0..Disable PWT to generate interrupt when PWTRDY is set. 5631 * 0b1..Enable PWT to generate interrupt when PWTRDY is set. 5632 */ 5633 #define PWT_R1_PRDYIE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PRDYIE_SHIFT)) & PWT_R1_PRDYIE_MASK) 5634 #define PWT_R1_PWTIE_MASK (0x40U) 5635 #define PWT_R1_PWTIE_SHIFT (6U) 5636 /*! PWTIE - PWT Module Interrupt Enable 5637 * 0b0..Disables the PWT to generate interrupt. 5638 * 0b1..Enables the PWT to generate interrupt. 5639 */ 5640 #define PWT_R1_PWTIE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTIE_SHIFT)) & PWT_R1_PWTIE_MASK) 5641 #define PWT_R1_PWTEN_MASK (0x80U) 5642 #define PWT_R1_PWTEN_SHIFT (7U) 5643 /*! PWTEN - PWT Module Enable 5644 * 0b0..The PWT is disabled. 5645 * 0b1..The PWT is enabled. 5646 */ 5647 #define PWT_R1_PWTEN(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PWTEN_SHIFT)) & PWT_R1_PWTEN_MASK) 5648 #define PWT_R1_PRE_MASK (0x700U) 5649 #define PWT_R1_PRE_SHIFT (8U) 5650 /*! PRE - PWT Clock Prescaler (CLKPRE) Setting 5651 * 0b000..Clock divided by 1. 5652 * 0b001..Clock divided by 2. 5653 * 0b010..Clock divided by 4. 5654 * 0b011..Clock divided by 8. 5655 * 0b100..Clock divided by 16. 5656 * 0b101..Clock divided by 32. 5657 * 0b110..Clock divided by 64. 5658 * 0b111..Clock divided by 128. 5659 */ 5660 #define PWT_R1_PRE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PRE_SHIFT)) & PWT_R1_PRE_MASK) 5661 #define PWT_R1_EDGE_MASK (0x1800U) 5662 #define PWT_R1_EDGE_SHIFT (11U) 5663 /*! EDGE - PWT Input Edge Sensitivity 5664 * 0b00..The first falling-edge starts the pulse width measurement, and on all the subsequent falling edges, the pulse width is captured. 5665 * 0b01..The first rising edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured. 5666 * 0b10..The first falling edge starts the pulse width measurement, and on all the subsequent rising and falling edges, the pulse width is captured. 5667 * 0b11..The first-rising edge starts the pulse width measurement, and on all the subsequent rising edges, the pulse width is captured. 5668 */ 5669 #define PWT_R1_EDGE(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_EDGE_SHIFT)) & PWT_R1_EDGE_MASK) 5670 #define PWT_R1_PINSEL_MASK (0x6000U) 5671 #define PWT_R1_PINSEL_SHIFT (13U) 5672 /*! PINSEL - PWT Pulse Inputs Selection 5673 * 0b00..PWTIN[0] is enabled. 5674 * 0b01..PWTIN[1] is enabled. 5675 * 0b10..PWTIN[2] enabled. 5676 * 0b11..PWTIN[3] enabled. 5677 */ 5678 #define PWT_R1_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PINSEL_SHIFT)) & PWT_R1_PINSEL_MASK) 5679 #define PWT_R1_PCLKS_MASK (0x8000U) 5680 #define PWT_R1_PCLKS_SHIFT (15U) 5681 /*! PCLKS - PWT Clock Source Selection 5682 * 0b0..TIMER_CLK is selected as the clock source of PWT counter. 5683 * 0b1..Alternative clock is selected as the clock source of PWT counter. 5684 */ 5685 #define PWT_R1_PCLKS(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PCLKS_SHIFT)) & PWT_R1_PCLKS_MASK) 5686 #define PWT_R1_PPW_MASK (0xFFFF0000U) 5687 #define PWT_R1_PPW_SHIFT (16U) 5688 #define PWT_R1_PPW(x) (((uint32_t)(((uint32_t)(x)) << PWT_R1_PPW_SHIFT)) & PWT_R1_PPW_MASK) 5689 /*! @} */ 5690 5691 /*! @name R2 - Pulse Width Timer Register 2 */ 5692 /*! @{ */ 5693 #define PWT_R2_NPW_MASK (0xFFFFU) 5694 #define PWT_R2_NPW_SHIFT (0U) 5695 #define PWT_R2_NPW(x) (((uint32_t)(((uint32_t)(x)) << PWT_R2_NPW_SHIFT)) & PWT_R2_NPW_MASK) 5696 #define PWT_R2_PWTC_MASK (0xFFFF0000U) 5697 #define PWT_R2_PWTC_SHIFT (16U) 5698 #define PWT_R2_PWTC(x) (((uint32_t)(((uint32_t)(x)) << PWT_R2_PWTC_SHIFT)) & PWT_R2_PWTC_MASK) 5699 /*! @} */ 5700 5701 5702 /*! 5703 * @} 5704 */ /* end of group PWT_Register_Masks */ 5705 5706 5707 /* PWT - Peripheral instance base addresses */ 5708 /** Peripheral PWT base address */ 5709 #define PWT_BASE (0x40033000u) 5710 /** Peripheral PWT base pointer */ 5711 #define PWT ((PWT_Type *)PWT_BASE) 5712 /** Array initializer of PWT peripheral base addresses */ 5713 #define PWT_BASE_ADDRS { PWT_BASE } 5714 /** Array initializer of PWT peripheral base pointers */ 5715 #define PWT_BASE_PTRS { PWT } 5716 /** Interrupt vectors for the PWT peripheral type */ 5717 #define PWT_IRQS { PWT_IRQn } 5718 5719 /*! 5720 * @} 5721 */ /* end of group PWT_Peripheral_Access_Layer */ 5722 5723 5724 /* ---------------------------------------------------------------------------- 5725 -- ROM Peripheral Access Layer 5726 ---------------------------------------------------------------------------- */ 5727 5728 /*! 5729 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 5730 * @{ 5731 */ 5732 5733 /** ROM - Register Layout Typedef */ 5734 typedef struct { 5735 __I uint32_t ENTRY[1]; /**< Entry, array offset: 0x0, array step: 0x4 */ 5736 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0x4 */ 5737 uint8_t RESERVED_0[4036]; 5738 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 5739 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 5740 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 5741 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 5742 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 5743 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 5744 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 5745 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 5746 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 5747 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 5748 } ROM_Type; 5749 5750 /* ---------------------------------------------------------------------------- 5751 -- ROM Register Masks 5752 ---------------------------------------------------------------------------- */ 5753 5754 /*! 5755 * @addtogroup ROM_Register_Masks ROM Register Masks 5756 * @{ 5757 */ 5758 5759 /*! @name ENTRY - Entry */ 5760 /*! @{ */ 5761 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 5762 #define ROM_ENTRY_ENTRY_SHIFT (0U) 5763 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 5764 /*! @} */ 5765 5766 /* The count of ROM_ENTRY */ 5767 #define ROM_ENTRY_COUNT (1U) 5768 5769 /*! @name TABLEMARK - End of Table Marker Register */ 5770 /*! @{ */ 5771 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 5772 #define ROM_TABLEMARK_MARK_SHIFT (0U) 5773 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 5774 /*! @} */ 5775 5776 /*! @name SYSACCESS - System Access Register */ 5777 /*! @{ */ 5778 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 5779 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 5780 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 5781 /*! @} */ 5782 5783 /*! @name PERIPHID4 - Peripheral ID Register */ 5784 /*! @{ */ 5785 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 5786 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 5787 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 5788 /*! @} */ 5789 5790 /*! @name PERIPHID5 - Peripheral ID Register */ 5791 /*! @{ */ 5792 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 5793 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 5794 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 5795 /*! @} */ 5796 5797 /*! @name PERIPHID6 - Peripheral ID Register */ 5798 /*! @{ */ 5799 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 5800 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 5801 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 5802 /*! @} */ 5803 5804 /*! @name PERIPHID7 - Peripheral ID Register */ 5805 /*! @{ */ 5806 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 5807 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 5808 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 5809 /*! @} */ 5810 5811 /*! @name PERIPHID0 - Peripheral ID Register */ 5812 /*! @{ */ 5813 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 5814 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 5815 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 5816 /*! @} */ 5817 5818 /*! @name PERIPHID1 - Peripheral ID Register */ 5819 /*! @{ */ 5820 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 5821 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 5822 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 5823 /*! @} */ 5824 5825 /*! @name PERIPHID2 - Peripheral ID Register */ 5826 /*! @{ */ 5827 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 5828 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 5829 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 5830 /*! @} */ 5831 5832 /*! @name PERIPHID3 - Peripheral ID Register */ 5833 /*! @{ */ 5834 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 5835 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 5836 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 5837 /*! @} */ 5838 5839 /*! @name COMPID - Component ID Register */ 5840 /*! @{ */ 5841 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 5842 #define ROM_COMPID_COMPID_SHIFT (0U) 5843 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 5844 /*! @} */ 5845 5846 /* The count of ROM_COMPID */ 5847 #define ROM_COMPID_COUNT (4U) 5848 5849 5850 /*! 5851 * @} 5852 */ /* end of group ROM_Register_Masks */ 5853 5854 5855 /* ROM - Peripheral instance base addresses */ 5856 /** Peripheral ROM base address */ 5857 #define ROM_BASE (0xF0002000u) 5858 /** Peripheral ROM base pointer */ 5859 #define ROM ((ROM_Type *)ROM_BASE) 5860 /** Array initializer of ROM peripheral base addresses */ 5861 #define ROM_BASE_ADDRS { ROM_BASE } 5862 /** Array initializer of ROM peripheral base pointers */ 5863 #define ROM_BASE_PTRS { ROM } 5864 5865 /*! 5866 * @} 5867 */ /* end of group ROM_Peripheral_Access_Layer */ 5868 5869 5870 /* ---------------------------------------------------------------------------- 5871 -- RTC Peripheral Access Layer 5872 ---------------------------------------------------------------------------- */ 5873 5874 /*! 5875 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 5876 * @{ 5877 */ 5878 5879 /** RTC - Register Layout Typedef */ 5880 typedef struct { 5881 __IO uint32_t SC; /**< RTC Status and Control Register, offset: 0x0 */ 5882 __IO uint32_t MOD; /**< RTC Modulo Register, offset: 0x4 */ 5883 __I uint32_t CNT; /**< RTC Counter Register, offset: 0x8 */ 5884 } RTC_Type; 5885 5886 /* ---------------------------------------------------------------------------- 5887 -- RTC Register Masks 5888 ---------------------------------------------------------------------------- */ 5889 5890 /*! 5891 * @addtogroup RTC_Register_Masks RTC Register Masks 5892 * @{ 5893 */ 5894 5895 /*! @name SC - RTC Status and Control Register */ 5896 /*! @{ */ 5897 #define RTC_SC_RTCO_MASK (0x10U) 5898 #define RTC_SC_RTCO_SHIFT (4U) 5899 /*! RTCO - Real-Time Counter Output 5900 * 0b0..Real-time counter output disabled. 5901 * 0b1..Real-time counter output enabled. 5902 */ 5903 #define RTC_SC_RTCO(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCO_SHIFT)) & RTC_SC_RTCO_MASK) 5904 #define RTC_SC_RTIE_MASK (0x40U) 5905 #define RTC_SC_RTIE_SHIFT (6U) 5906 /*! RTIE - Real-Time Interrupt Enable 5907 * 0b0..Real-time interrupt requests are disabled. Use software polling. 5908 * 0b1..Real-time interrupt requests are enabled. 5909 */ 5910 #define RTC_SC_RTIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTIE_SHIFT)) & RTC_SC_RTIE_MASK) 5911 #define RTC_SC_RTIF_MASK (0x80U) 5912 #define RTC_SC_RTIF_SHIFT (7U) 5913 /*! RTIF - Real-Time Interrupt Flag 5914 * 0b0..RTC counter has not reached the value in the RTC modulo register. 5915 * 0b1..RTC counter has reached the value in the RTC modulo register. 5916 */ 5917 #define RTC_SC_RTIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTIF_SHIFT)) & RTC_SC_RTIF_MASK) 5918 #define RTC_SC_RTCPS_MASK (0x700U) 5919 #define RTC_SC_RTCPS_SHIFT (8U) 5920 /*! RTCPS - Real-Time Clock Prescaler Select 5921 * 0b000..Off 5922 * 0b001..If RTCLKS = x0, it is 1; if RTCLKS = x1, it is 128. 5923 * 0b010..If RTCLKS = x0, it is 2; if RTCLKS = x1, it is 256. 5924 * 0b011..If RTCLKS = x0, it is 4; if RTCLKS = x1, it is 512. 5925 * 0b100..If RTCLKS = x0, it is 8; if RTCLKS = x1, it is 1024. 5926 * 0b101..If RTCLKS = x0, it is 16; if RTCLKS = x1, it is 2048. 5927 * 0b110..If RTCLKS = x0, it is 32; if RTCLKS = x1, it is 100. 5928 * 0b111..If RTCLKS = x0, it is 64; if RTCLKS = x1, it is 1000. 5929 */ 5930 #define RTC_SC_RTCPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCPS_SHIFT)) & RTC_SC_RTCPS_MASK) 5931 #define RTC_SC_RTCLKS_MASK (0xC000U) 5932 #define RTC_SC_RTCLKS_SHIFT (14U) 5933 /*! RTCLKS - Real-Time Clock Source Select 5934 * 0b00..External clock source. 5935 * 0b01..Real-time clock source is 1 kHz (LPOCLK). 5936 * 0b10..Internal reference clock (ICSIRCLK). 5937 * 0b11..Bus clock. 5938 */ 5939 #define RTC_SC_RTCLKS(x) (((uint32_t)(((uint32_t)(x)) << RTC_SC_RTCLKS_SHIFT)) & RTC_SC_RTCLKS_MASK) 5940 /*! @} */ 5941 5942 /*! @name MOD - RTC Modulo Register */ 5943 /*! @{ */ 5944 #define RTC_MOD_MOD_MASK (0xFFFFU) 5945 #define RTC_MOD_MOD_SHIFT (0U) 5946 #define RTC_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << RTC_MOD_MOD_SHIFT)) & RTC_MOD_MOD_MASK) 5947 /*! @} */ 5948 5949 /*! @name CNT - RTC Counter Register */ 5950 /*! @{ */ 5951 #define RTC_CNT_CNT_MASK (0xFFFFU) 5952 #define RTC_CNT_CNT_SHIFT (0U) 5953 #define RTC_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << RTC_CNT_CNT_SHIFT)) & RTC_CNT_CNT_MASK) 5954 /*! @} */ 5955 5956 5957 /*! 5958 * @} 5959 */ /* end of group RTC_Register_Masks */ 5960 5961 5962 /* RTC - Peripheral instance base addresses */ 5963 /** Peripheral RTC base address */ 5964 #define RTC_BASE (0x4003D000u) 5965 /** Peripheral RTC base pointer */ 5966 #define RTC ((RTC_Type *)RTC_BASE) 5967 /** Array initializer of RTC peripheral base addresses */ 5968 #define RTC_BASE_ADDRS { RTC_BASE } 5969 /** Array initializer of RTC peripheral base pointers */ 5970 #define RTC_BASE_PTRS { RTC } 5971 /** Interrupt vectors for the RTC peripheral type */ 5972 #define RTC_IRQS { RTC_IRQn } 5973 5974 /*! 5975 * @} 5976 */ /* end of group RTC_Peripheral_Access_Layer */ 5977 5978 5979 /* ---------------------------------------------------------------------------- 5980 -- SIM Peripheral Access Layer 5981 ---------------------------------------------------------------------------- */ 5982 5983 /*! 5984 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 5985 * @{ 5986 */ 5987 5988 /** SIM - Register Layout Typedef */ 5989 typedef struct { 5990 __I uint32_t SRSID; /**< System Reset Status and ID Register, offset: 0x0 */ 5991 __IO uint32_t SOPT0; /**< System Options Register 0, offset: 0x4 */ 5992 __IO uint32_t SOPT1; /**< System Options Register, offset: 0x8 */ 5993 __IO uint32_t PINSEL0; /**< Pin Selection Register 0, offset: 0xC */ 5994 __IO uint32_t PINSEL1; /**< Pin Selection Register 1, offset: 0x10 */ 5995 __IO uint32_t SCGC; /**< System Clock Gating Control Register, offset: 0x14 */ 5996 __I uint32_t UUIDL; /**< Universally Unique Identifier Low Register, offset: 0x18 */ 5997 __I uint32_t UUIDML; /**< Universally Unique Identifier Middle Low Register, offset: 0x1C */ 5998 __I uint32_t UUIDMH; /**< Universally Unique Identifier Middle High Register, offset: 0x20 */ 5999 __IO uint32_t CLKDIV; /**< Clock Divider Register, offset: 0x24 */ 6000 } SIM_Type; 6001 6002 /* ---------------------------------------------------------------------------- 6003 -- SIM Register Masks 6004 ---------------------------------------------------------------------------- */ 6005 6006 /*! 6007 * @addtogroup SIM_Register_Masks SIM Register Masks 6008 * @{ 6009 */ 6010 6011 /*! @name SRSID - System Reset Status and ID Register */ 6012 /*! @{ */ 6013 #define SIM_SRSID_LVD_MASK (0x2U) 6014 #define SIM_SRSID_LVD_SHIFT (1U) 6015 /*! LVD - Low Voltage Detect 6016 * 0b0..Reset is not caused by LVD trip or POR. 6017 * 0b1..Reset is caused by LVD trip or POR. 6018 */ 6019 #define SIM_SRSID_LVD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LVD_SHIFT)) & SIM_SRSID_LVD_MASK) 6020 #define SIM_SRSID_LOC_MASK (0x4U) 6021 #define SIM_SRSID_LOC_SHIFT (2U) 6022 /*! LOC - Internal Clock Source Module Reset 6023 * 0b0..Reset is not caused by the ICS module. 6024 * 0b1..Reset is caused by the ICS module. 6025 */ 6026 #define SIM_SRSID_LOC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LOC_SHIFT)) & SIM_SRSID_LOC_MASK) 6027 #define SIM_SRSID_WDOG_MASK (0x20U) 6028 #define SIM_SRSID_WDOG_SHIFT (5U) 6029 /*! WDOG - Watchdog (WDOG) 6030 * 0b0..Reset is not caused by WDOG timeout. 6031 * 0b1..Reset is caused by WDOG timeout. 6032 */ 6033 #define SIM_SRSID_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_WDOG_SHIFT)) & SIM_SRSID_WDOG_MASK) 6034 #define SIM_SRSID_PIN_MASK (0x40U) 6035 #define SIM_SRSID_PIN_SHIFT (6U) 6036 /*! PIN - External Reset Pin 6037 * 0b0..Reset is not caused by external reset pin. 6038 * 0b1..Reset came from external reset pin. 6039 */ 6040 #define SIM_SRSID_PIN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_PIN_SHIFT)) & SIM_SRSID_PIN_MASK) 6041 #define SIM_SRSID_POR_MASK (0x80U) 6042 #define SIM_SRSID_POR_SHIFT (7U) 6043 /*! POR - Power-On Reset 6044 * 0b0..Reset not caused by POR. 6045 * 0b1..POR caused reset. 6046 */ 6047 #define SIM_SRSID_POR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_POR_SHIFT)) & SIM_SRSID_POR_MASK) 6048 #define SIM_SRSID_LOCKUP_MASK (0x200U) 6049 #define SIM_SRSID_LOCKUP_SHIFT (9U) 6050 /*! LOCKUP - Core Lockup 6051 * 0b0..Reset is not caused by core LOCKUP event. 6052 * 0b1..Reset is caused by core LOCKUP event. 6053 */ 6054 #define SIM_SRSID_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_LOCKUP_SHIFT)) & SIM_SRSID_LOCKUP_MASK) 6055 #define SIM_SRSID_SW_MASK (0x400U) 6056 #define SIM_SRSID_SW_SHIFT (10U) 6057 /*! SW - Software 6058 * 0b0..Reset is not caused by software setting of SYSRESETREQ bit. 6059 * 0b1..Reset caused by software setting of SYSRESETREQ bit 6060 */ 6061 #define SIM_SRSID_SW(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SW_SHIFT)) & SIM_SRSID_SW_MASK) 6062 #define SIM_SRSID_MDMAP_MASK (0x800U) 6063 #define SIM_SRSID_MDMAP_SHIFT (11U) 6064 /*! MDMAP - MDM-AP System Reset Request 6065 * 0b0..Reset is not caused by host debugger system setting of the System Reset Request bit. 6066 * 0b1..Reset is caused by host debugger system setting of the System Reset Request bit. 6067 */ 6068 #define SIM_SRSID_MDMAP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_MDMAP_SHIFT)) & SIM_SRSID_MDMAP_MASK) 6069 #define SIM_SRSID_SACKERR_MASK (0x2000U) 6070 #define SIM_SRSID_SACKERR_SHIFT (13U) 6071 /*! SACKERR - Stop Mode Acknowledge Error Reset 6072 * 0b0..Reset is not caused by peripheral failure to acknowledge attempt to enter Stop mode. 6073 * 0b1..Reset is caused by peripheral failure to acknowledge attempt to enter Stop mode. 6074 */ 6075 #define SIM_SRSID_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SACKERR_SHIFT)) & SIM_SRSID_SACKERR_MASK) 6076 #define SIM_SRSID_PINID_MASK (0xF0000U) 6077 #define SIM_SRSID_PINID_SHIFT (16U) 6078 /*! PINID - Device Pin ID 6079 * 0b0000..8-pin 6080 * 0b0001..16-pin 6081 * 0b0010..20-pin 6082 * 0b0011..24-pin 6083 * 0b0100..32-pin 6084 * 0b0101..44-pin 6085 * 0b0110..48-pin 6086 * 0b0111..64-pin 6087 * 0b1000..80-pin 6088 * 0b1010..100-pin 6089 */ 6090 #define SIM_SRSID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_PINID_SHIFT)) & SIM_SRSID_PINID_MASK) 6091 #define SIM_SRSID_RevID_MASK (0xF00000U) 6092 #define SIM_SRSID_RevID_SHIFT (20U) 6093 #define SIM_SRSID_RevID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_RevID_SHIFT)) & SIM_SRSID_RevID_MASK) 6094 #define SIM_SRSID_SUBFAMID_MASK (0xF000000U) 6095 #define SIM_SRSID_SUBFAMID_SHIFT (24U) 6096 /*! SUBFAMID - Kinetis sub-family ID 6097 * 0b0100..KEx4 sub-family 6098 * 0b0110..KEx6 sub-family 6099 */ 6100 #define SIM_SRSID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_SUBFAMID_SHIFT)) & SIM_SRSID_SUBFAMID_MASK) 6101 #define SIM_SRSID_FAMID_MASK (0xF0000000U) 6102 #define SIM_SRSID_FAMID_SHIFT (28U) 6103 /*! FAMID - Kinetis family ID 6104 * 0b0000..KE0x family. 6105 */ 6106 #define SIM_SRSID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SRSID_FAMID_SHIFT)) & SIM_SRSID_FAMID_MASK) 6107 /*! @} */ 6108 6109 /*! @name SOPT0 - System Options Register 0 */ 6110 /*! @{ */ 6111 #define SIM_SOPT0_NMIE_MASK (0x2U) 6112 #define SIM_SOPT0_NMIE_SHIFT (1U) 6113 /*! NMIE - NMI Pin Enable 6114 * 0b0..PTB4/KBI0_P12/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as PTB4, KBI0_P12, FTM2_CH4, SPI0_MISO or ACMP1_IN2. 6115 * 0b1..PTB4/KBI0_P12/FTM2_CH4/SPI0_MISO/ACMP1_IN2/NMI pin functions as NMI. 6116 */ 6117 #define SIM_SOPT0_NMIE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_NMIE_SHIFT)) & SIM_SOPT0_NMIE_MASK) 6118 #define SIM_SOPT0_RSTPE_MASK (0x4U) 6119 #define SIM_SOPT0_RSTPE_SHIFT (2U) 6120 /*! RSTPE - RESET Pin Enable 6121 * 0b0..PTA5/KBI0_P5/IRQ/TCLK0/RESET pin functions as PTA5/KBI0_P5/IRQ/TCLK0. 6122 * 0b1..PTA5/KBI0_P5/IRQ/TCLK0/RESET pin functions as RESET. 6123 */ 6124 #define SIM_SOPT0_RSTPE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_RSTPE_SHIFT)) & SIM_SOPT0_RSTPE_MASK) 6125 #define SIM_SOPT0_SWDE_MASK (0x8U) 6126 #define SIM_SOPT0_SWDE_SHIFT (3U) 6127 /*! SWDE - Single Wire Debug Port Pin Enable 6128 * 0b0..PTA4/KBI0_P4/ACMP0_OUT/SWD_DIO as PTA4 or ACMP0_OUT function, PTC4/KBI0_P20/RTC_CLKOUT/FTM1_CH0/ACMP0_IN2/SWD_CLK as PTC4, KBI0_P20, RTC_CLKOUT, FTM1_CH0, OR ACMP0_IN2 function. 6129 * 0b1..PTA4/KBI0_P4/ACMP0_OUT/SWD_DIO as SWD_DIO function, PTC4/KBI0_P20/RTC_CLKOUT/FTM1_CH0/ACMP0_IN2/SWD_CLK as SWD_CLK function. 6130 */ 6131 #define SIM_SOPT0_SWDE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_SWDE_SHIFT)) & SIM_SOPT0_SWDE_MASK) 6132 #define SIM_SOPT0_ACTRG_MASK (0x20U) 6133 #define SIM_SOPT0_ACTRG_SHIFT (5U) 6134 /*! ACTRG - ACMP Trigger FTM2 selection 6135 * 0b0..ACMP0 out 6136 * 0b1..ACMP1 out 6137 */ 6138 #define SIM_SOPT0_ACTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_ACTRG_SHIFT)) & SIM_SOPT0_ACTRG_MASK) 6139 #define SIM_SOPT0_RXDFE_MASK (0x300U) 6140 #define SIM_SOPT0_RXDFE_SHIFT (8U) 6141 /*! RXDFE - UART0 RxD Filter Select 6142 * 0b00..RXD0 input signal is connected to UART0 module directly. 6143 * 0b01..RXD0 input signal is filtered by ACMP0, then injected to UART0. 6144 * 0b10..RXD0 input signal is filtered by ACMP1, then injected to UART0. 6145 * 0b11..Reserved. 6146 */ 6147 #define SIM_SOPT0_RXDFE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_RXDFE_SHIFT)) & SIM_SOPT0_RXDFE_MASK) 6148 #define SIM_SOPT0_RTCC_MASK (0x400U) 6149 #define SIM_SOPT0_RTCC_SHIFT (10U) 6150 /*! RTCC - Real-Time Counter Capture 6151 * 0b0..RTC overflow is not connected to FTM1 input channel 1. 6152 * 0b1..RTC overflow is connected to FTM1 input channel 1. 6153 */ 6154 #define SIM_SOPT0_RTCC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_RTCC_SHIFT)) & SIM_SOPT0_RTCC_MASK) 6155 #define SIM_SOPT0_ACIC_MASK (0x800U) 6156 #define SIM_SOPT0_ACIC_SHIFT (11U) 6157 /*! ACIC - Analog Comparator to Input Capture Enable 6158 * 0b0..ACMP0 output is not connected to FTM1 input channel 0. 6159 * 0b1..ACMP0 output is connected to FTM1 input channel 0. 6160 */ 6161 #define SIM_SOPT0_ACIC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_ACIC_SHIFT)) & SIM_SOPT0_ACIC_MASK) 6162 #define SIM_SOPT0_RXDCE_MASK (0x1000U) 6163 #define SIM_SOPT0_RXDCE_SHIFT (12U) 6164 /*! RXDCE - UART0_RX Capture Select 6165 * 0b0..UART0_RX input signal is connected to the UART0 module only. 6166 * 0b1..UART0_RX input signal is connected to the UART0 module and FTM0 channel 1. 6167 */ 6168 #define SIM_SOPT0_RXDCE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_RXDCE_SHIFT)) & SIM_SOPT0_RXDCE_MASK) 6169 #define SIM_SOPT0_FTMSYNC_MASK (0x4000U) 6170 #define SIM_SOPT0_FTMSYNC_SHIFT (14U) 6171 /*! FTMSYNC - FTM2 Synchronization Select 6172 * 0b0..No synchronization triggered. 6173 * 0b1..Generates a PWM synchronization trigger to the FTM2 modules. 6174 */ 6175 #define SIM_SOPT0_FTMSYNC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_FTMSYNC_SHIFT)) & SIM_SOPT0_FTMSYNC_MASK) 6176 #define SIM_SOPT0_TXDME_MASK (0x8000U) 6177 #define SIM_SOPT0_TXDME_SHIFT (15U) 6178 /*! TXDME - UART0_TX Modulation Select 6179 * 0b0..UART0_TX output is connected to pinout directly. 6180 * 0b1..UART0_TX output is modulated by FTM0 channel 0 before mapped to pinout. 6181 */ 6182 #define SIM_SOPT0_TXDME(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_TXDME_SHIFT)) & SIM_SOPT0_TXDME_MASK) 6183 #define SIM_SOPT0_BUSREF_MASK (0x70000U) 6184 #define SIM_SOPT0_BUSREF_SHIFT (16U) 6185 /*! BUSREF - BUS Clock Output select 6186 * 0b000..Bus 6187 * 0b001..Bus divided by 2 6188 * 0b010..Bus divided by 4 6189 * 0b011..Bus divided by 8 6190 * 0b100..Bus divided by 16 6191 * 0b101..Bus divided by 32 6192 * 0b110..Bus divided by 64 6193 * 0b111..Bus divided by 128 6194 */ 6195 #define SIM_SOPT0_BUSREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_BUSREF_SHIFT)) & SIM_SOPT0_BUSREF_MASK) 6196 #define SIM_SOPT0_CLKOE_MASK (0x80000U) 6197 #define SIM_SOPT0_CLKOE_SHIFT (19U) 6198 /*! CLKOE - Bus Clock Output Enable 6199 * 0b0..Bus clock output is disabled on PTH2. 6200 * 0b1..Bus clock output is enabled on PTH2. 6201 */ 6202 #define SIM_SOPT0_CLKOE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_CLKOE_SHIFT)) & SIM_SOPT0_CLKOE_MASK) 6203 #define SIM_SOPT0_ADHWT_MASK (0x700000U) 6204 #define SIM_SOPT0_ADHWT_SHIFT (20U) 6205 /*! ADHWT - ADC Hardware Trigger Source 6206 * 0b000..RTC overflow as the ADC hardware trigger 6207 * 0b001..FTM0 as the ADC hardware trigger 6208 * 0b010..FTM2 init trigger with 8-bit programmable counter delay 6209 * 0b011..FTM2 match trigger with 8-bit programmable counter delay 6210 * 0b100..PIT channel0 overflow as the ADC hardware trigger 6211 * 0b101..PIT channel1 overflow as the ADC hardware trigger 6212 * 0b110..ACMP0 out as the ADC hardware trigger. 6213 * 0b111..ACMP1 out as the ADC hardware trigger 6214 */ 6215 #define SIM_SOPT0_ADHWT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_ADHWT_SHIFT)) & SIM_SOPT0_ADHWT_MASK) 6216 #define SIM_SOPT0_DLYACT_MASK (0x800000U) 6217 #define SIM_SOPT0_DLYACT_SHIFT (23U) 6218 /*! DLYACT - FTM2 Trigger Delay Active 6219 * 0b0..The delay is inactive. 6220 * 0b1..The delay is active. 6221 */ 6222 #define SIM_SOPT0_DLYACT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_DLYACT_SHIFT)) & SIM_SOPT0_DLYACT_MASK) 6223 #define SIM_SOPT0_DELAY_MASK (0xFF000000U) 6224 #define SIM_SOPT0_DELAY_SHIFT (24U) 6225 #define SIM_SOPT0_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT0_DELAY_SHIFT)) & SIM_SOPT0_DELAY_MASK) 6226 /*! @} */ 6227 6228 /*! @name SOPT1 - System Options Register */ 6229 /*! @{ */ 6230 #define SIM_SOPT1_I2C04WEN_MASK (0x1U) 6231 #define SIM_SOPT1_I2C04WEN_SHIFT (0U) 6232 /*! I2C04WEN - I2C0 4-Wire Interface Enable 6233 * 0b0..I2C0 4-wire interface configuration is disabled. 6234 * 0b1..I2C0 4-wire interface configuration is enabled. 6235 */ 6236 #define SIM_SOPT1_I2C04WEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_I2C04WEN_SHIFT)) & SIM_SOPT1_I2C04WEN_MASK) 6237 #define SIM_SOPT1_I2C0OINV_MASK (0x2U) 6238 #define SIM_SOPT1_I2C0OINV_SHIFT (1U) 6239 /*! I2C0OINV - I2C0 Output Invert 6240 * 0b0..Under I2C0 4-wire interface configuration, SDA_OUT and SCL_OUT are not inverted before output 6241 * 0b1..Under I2C0 4-wire interface configuration, SDA_OUT and SCL_OUT are inverted before output 6242 */ 6243 #define SIM_SOPT1_I2C0OINV(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_I2C0OINV_SHIFT)) & SIM_SOPT1_I2C0OINV_MASK) 6244 #define SIM_SOPT1_ACPWTS_MASK (0x8U) 6245 #define SIM_SOPT1_ACPWTS_SHIFT (3U) 6246 /*! ACPWTS - PWT ACMP_OUT select 6247 * 0b0..ACMP1_OUT is connectted to PWTIN2. 6248 * 0b1..ACMP0_OUT is connectted to PWTIN2. 6249 */ 6250 #define SIM_SOPT1_ACPWTS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_ACPWTS_SHIFT)) & SIM_SOPT1_ACPWTS_MASK) 6251 #define SIM_SOPT1_UARTPWTS_MASK (0x30U) 6252 #define SIM_SOPT1_UARTPWTS_SHIFT (4U) 6253 /*! UARTPWTS - PWT UART RX select 6254 * 0b00..UART0 RX is connectted to PWTIN3. 6255 * 0b01..UART1 RX is connectted to PWTIN3. 6256 * 0b10..UART2 RX is connectted to PWTIN3. 6257 * 0b11..Reserved. 6258 */ 6259 #define SIM_SOPT1_UARTPWTS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_UARTPWTS_SHIFT)) & SIM_SOPT1_UARTPWTS_MASK) 6260 /*! @} */ 6261 6262 /*! @name PINSEL0 - Pin Selection Register 0 */ 6263 /*! @{ */ 6264 #define SIM_PINSEL0_IRQPS_MASK (0x7U) 6265 #define SIM_PINSEL0_IRQPS_SHIFT (0U) 6266 /*! IRQPS - IRQ Port Pin Select 6267 * 0b000..IRQ is mapped on PTA5. 6268 * 0b001..IRQ is mapped on PTI0. 6269 * 0b010..IRQ is mapped on PTI1. 6270 * 0b011..IRQ is mapped on PTI2. 6271 * 0b100..IRQ is mapped on PTI3. 6272 * 0b101..IRQ is mapped on PTI4. 6273 * 0b110..IRQ is mapped on PTI5. 6274 * 0b111..IRQ is mapped on PTI6. 6275 */ 6276 #define SIM_PINSEL0_IRQPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_IRQPS_SHIFT)) & SIM_PINSEL0_IRQPS_MASK) 6277 #define SIM_PINSEL0_RTCPS_MASK (0x10U) 6278 #define SIM_PINSEL0_RTCPS_SHIFT (4U) 6279 /*! RTCPS - RTCO Pin Select 6280 * 0b0..RTCO is mapped on PTC4. 6281 * 0b1..RTCO is mapped on PTC5. 6282 */ 6283 #define SIM_PINSEL0_RTCPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_RTCPS_SHIFT)) & SIM_PINSEL0_RTCPS_MASK) 6284 #define SIM_PINSEL0_I2C0PS_MASK (0x20U) 6285 #define SIM_PINSEL0_I2C0PS_SHIFT (5U) 6286 /*! I2C0PS - I2C0 Port Pin Select 6287 * 0b0..I2C0_SCL and I2C0_SDA are mapped on PTA3 and PTA2, respectively. 6288 * 0b1..I2C0_SCL and I2C0_SDA are mapped on PTB7 and PTB6, respectively. 6289 */ 6290 #define SIM_PINSEL0_I2C0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_I2C0PS_SHIFT)) & SIM_PINSEL0_I2C0PS_MASK) 6291 #define SIM_PINSEL0_SPI0PS_MASK (0x40U) 6292 #define SIM_PINSEL0_SPI0PS_SHIFT (6U) 6293 /*! SPI0PS - SPI0 Pin Select 6294 * 0b0..SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTB2, PTB3, PTB4, and PTB5. 6295 * 0b1..SPI0_SCK, SPI0_MOSI, SPI0_MISO, and SPI0_PCS are mapped on PTE0, PTE1, PTE2, and PTE3. 6296 */ 6297 #define SIM_PINSEL0_SPI0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_SPI0PS_SHIFT)) & SIM_PINSEL0_SPI0PS_MASK) 6298 #define SIM_PINSEL0_UART0PS_MASK (0x80U) 6299 #define SIM_PINSEL0_UART0PS_SHIFT (7U) 6300 /*! UART0PS - UART0 Pin Select 6301 * 0b0..UART0_RX and UART0_TX are mapped on PTB0 and PTB1. 6302 * 0b1..UART0_RX and UART0_TX are mapped on PTA2 and PTA3. 6303 */ 6304 #define SIM_PINSEL0_UART0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_UART0PS_SHIFT)) & SIM_PINSEL0_UART0PS_MASK) 6305 #define SIM_PINSEL0_FTM0PS0_MASK (0x100U) 6306 #define SIM_PINSEL0_FTM0PS0_SHIFT (8U) 6307 /*! FTM0PS0 - FTM0_CH0 Port Pin Select 6308 * 0b0..FTM0_CH0 channels are mapped on PTA0. 6309 * 0b1..FTM0_CH0 channels are mapped on PTB2. 6310 */ 6311 #define SIM_PINSEL0_FTM0PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM0PS0_SHIFT)) & SIM_PINSEL0_FTM0PS0_MASK) 6312 #define SIM_PINSEL0_FTM0PS1_MASK (0x200U) 6313 #define SIM_PINSEL0_FTM0PS1_SHIFT (9U) 6314 /*! FTM0PS1 - FTM0_CH1 Port Pin Select 6315 * 0b0..FTM0_CH1 channels are mapped on PTA1. 6316 * 0b1..FTM0_CH1 channels are mapped on PTB3. 6317 */ 6318 #define SIM_PINSEL0_FTM0PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM0PS1_SHIFT)) & SIM_PINSEL0_FTM0PS1_MASK) 6319 #define SIM_PINSEL0_FTM1PS0_MASK (0x400U) 6320 #define SIM_PINSEL0_FTM1PS0_SHIFT (10U) 6321 /*! FTM1PS0 - FTM1_CH0 Port Pin Select 6322 * 0b0..FTM1_CH0 channels are mapped on PTC4. 6323 * 0b1..FTM1_CH0 channels are mapped on PTH2. 6324 */ 6325 #define SIM_PINSEL0_FTM1PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM1PS0_SHIFT)) & SIM_PINSEL0_FTM1PS0_MASK) 6326 #define SIM_PINSEL0_FTM1PS1_MASK (0x800U) 6327 #define SIM_PINSEL0_FTM1PS1_SHIFT (11U) 6328 /*! FTM1PS1 - FTM1_CH1 Port Pin Select 6329 * 0b0..FTM1_CH1 channels are mapped on PTC5. 6330 * 0b1..FTM1_CH1 channels are mapped on PTE7. 6331 */ 6332 #define SIM_PINSEL0_FTM1PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM1PS1_SHIFT)) & SIM_PINSEL0_FTM1PS1_MASK) 6333 #define SIM_PINSEL0_FTM0CLKPS_MASK (0x3000000U) 6334 #define SIM_PINSEL0_FTM0CLKPS_SHIFT (24U) 6335 /*! FTM0CLKPS - FTM0 TCLK Pin Select 6336 * 0b00..Selects TCLK0 for FTM0 module.. 6337 * 0b01..Selects TCLK1 for FTM0 module. 6338 * 0b10..Selects TCLK2 for FTM0 module. 6339 * 0b11..Reserved. 6340 */ 6341 #define SIM_PINSEL0_FTM0CLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM0CLKPS_SHIFT)) & SIM_PINSEL0_FTM0CLKPS_MASK) 6342 #define SIM_PINSEL0_FTM1CLKPS_MASK (0xC000000U) 6343 #define SIM_PINSEL0_FTM1CLKPS_SHIFT (26U) 6344 /*! FTM1CLKPS - FTM1 TCLK Pin Select 6345 * 0b00..Selects TCLK0 for FTM1 module.. 6346 * 0b01..Selects TCLK1 for FTM1 module. 6347 * 0b10..Selects TCLK2 for FTM1 module. 6348 * 0b11..Reserved. 6349 */ 6350 #define SIM_PINSEL0_FTM1CLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM1CLKPS_SHIFT)) & SIM_PINSEL0_FTM1CLKPS_MASK) 6351 #define SIM_PINSEL0_FTM2CLKPS_MASK (0x30000000U) 6352 #define SIM_PINSEL0_FTM2CLKPS_SHIFT (28U) 6353 /*! FTM2CLKPS - FTM2 TCLK Pin Select 6354 * 0b00..Selects TCLK0 for FTM2 module.. 6355 * 0b01..Selects TCLK1 for FTM2 module. 6356 * 0b10..Selects TCLK2 for FTM2 module. 6357 * 0b11..Reserved. 6358 */ 6359 #define SIM_PINSEL0_FTM2CLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_FTM2CLKPS_SHIFT)) & SIM_PINSEL0_FTM2CLKPS_MASK) 6360 #define SIM_PINSEL0_PWTCLKPS_MASK (0xC0000000U) 6361 #define SIM_PINSEL0_PWTCLKPS_SHIFT (30U) 6362 /*! PWTCLKPS - PWT TCLK Pin Select 6363 * 0b00..Selects TCLK0 for PWT module. 6364 * 0b01..Selects TCLK1 for PWT module. 6365 * 0b10..Selects TCLK2 for PWT module. 6366 * 0b11..Reserved. 6367 */ 6368 #define SIM_PINSEL0_PWTCLKPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL0_PWTCLKPS_SHIFT)) & SIM_PINSEL0_PWTCLKPS_MASK) 6369 /*! @} */ 6370 6371 /*! @name PINSEL1 - Pin Selection Register 1 */ 6372 /*! @{ */ 6373 #define SIM_PINSEL1_FTM2PS0_MASK (0x3U) 6374 #define SIM_PINSEL1_FTM2PS0_SHIFT (0U) 6375 /*! FTM2PS0 - FTM2 Channel 0 Pin Select 6376 * 0b00..FTM2 CH0 mapped on PTC0. 6377 * 0b01..FTM2 CH0 mapped on PTH0. 6378 * 0b10..FTM2 CH0 mapped on PTF0. 6379 * 0b11..Reserved. 6380 */ 6381 #define SIM_PINSEL1_FTM2PS0(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_FTM2PS0_SHIFT)) & SIM_PINSEL1_FTM2PS0_MASK) 6382 #define SIM_PINSEL1_FTM2PS1_MASK (0xCU) 6383 #define SIM_PINSEL1_FTM2PS1_SHIFT (2U) 6384 /*! FTM2PS1 - FTM2 Channel 1 Pin Select 6385 * 0b00..FTM2 CH1 mapped on PTC1. 6386 * 0b01..FTM2 CH1 mapped on PTH1. 6387 * 0b10..FTM2 CH1 mapped on PTF1. 6388 * 0b11..Reserved. 6389 */ 6390 #define SIM_PINSEL1_FTM2PS1(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_FTM2PS1_SHIFT)) & SIM_PINSEL1_FTM2PS1_MASK) 6391 #define SIM_PINSEL1_FTM2PS2_MASK (0x30U) 6392 #define SIM_PINSEL1_FTM2PS2_SHIFT (4U) 6393 /*! FTM2PS2 - FTM2 Channel 2 Pin Select 6394 * 0b00..FTM2 CH2 mapped on PTC2. 6395 * 0b01..FTM2 CH2 mapped on PTD0. 6396 * 0b10..FTM2 CH2 mapped on PTG4. 6397 * 0b11..Reserved. 6398 */ 6399 #define SIM_PINSEL1_FTM2PS2(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_FTM2PS2_SHIFT)) & SIM_PINSEL1_FTM2PS2_MASK) 6400 #define SIM_PINSEL1_FTM2PS3_MASK (0xC0U) 6401 #define SIM_PINSEL1_FTM2PS3_SHIFT (6U) 6402 /*! FTM2PS3 - FTM2 Channel 3 Pin Select 6403 * 0b00..FTM2 CH3 mapped on PTC3. 6404 * 0b01..FTM2 CH3 mapped on PTD1. 6405 * 0b10..FTM2 CH3 mapped on PTG5. 6406 * 0b11..Reserved. 6407 */ 6408 #define SIM_PINSEL1_FTM2PS3(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_FTM2PS3_SHIFT)) & SIM_PINSEL1_FTM2PS3_MASK) 6409 #define SIM_PINSEL1_FTM2PS4_MASK (0x100U) 6410 #define SIM_PINSEL1_FTM2PS4_SHIFT (8U) 6411 /*! FTM2PS4 - FTM2 Channel4 Pin Select 6412 * 0b0..FTM2 CH4 mapped on PTB4. 6413 * 0b1..FTM2 CH4 mapped on PTG6. 6414 */ 6415 #define SIM_PINSEL1_FTM2PS4(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_FTM2PS4_SHIFT)) & SIM_PINSEL1_FTM2PS4_MASK) 6416 #define SIM_PINSEL1_FTM2PS5_MASK (0x200U) 6417 #define SIM_PINSEL1_FTM2PS5_SHIFT (9U) 6418 /*! FTM2PS5 - FTM2 Channel 5 Pin Select 6419 * 0b0..FTM2 CH5 mapped on PTB5. 6420 * 0b1..FTM2 CH5 mapped on PTG7. 6421 */ 6422 #define SIM_PINSEL1_FTM2PS5(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_FTM2PS5_SHIFT)) & SIM_PINSEL1_FTM2PS5_MASK) 6423 #define SIM_PINSEL1_I2C1PS_MASK (0x400U) 6424 #define SIM_PINSEL1_I2C1PS_SHIFT (10U) 6425 /*! I2C1PS - I2C1 Pin Select 6426 * 0b0..I2C1_SCL on PTE1, I2C1_SDA on PTE0. 6427 * 0b1..I2C1_SCL on PTH4, I2C1_SDA on PTH3. 6428 */ 6429 #define SIM_PINSEL1_I2C1PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_I2C1PS_SHIFT)) & SIM_PINSEL1_I2C1PS_MASK) 6430 #define SIM_PINSEL1_SPI1PS_MASK (0x800U) 6431 #define SIM_PINSEL1_SPI1PS_SHIFT (11U) 6432 /*! SPI1PS - SPI1 Pin Select 6433 * 0b0..SPI1_SCK, SPI1_MOSI, SPI1_MISO, and SPI1_PCS are mapped on PTD0, PTD1, PTD2, and PTD3. 6434 * 0b1..SPI1_SCK, SPI1_MOSI, SPI1_MISO, and SPI1_PCS are mapped on PTG4, PTG5, PTG6, and PTG7. 6435 */ 6436 #define SIM_PINSEL1_SPI1PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_SPI1PS_SHIFT)) & SIM_PINSEL1_SPI1PS_MASK) 6437 #define SIM_PINSEL1_UART1PS_MASK (0x1000U) 6438 #define SIM_PINSEL1_UART1PS_SHIFT (12U) 6439 /*! UART1PS - UART1 Pin Select 6440 * 0b0..UART1_TX on PTC7, UART1_RX on PTC6. 6441 * 0b1..UART1_TX on PTF3, UART1_RX on PTF2. 6442 */ 6443 #define SIM_PINSEL1_UART1PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_UART1PS_SHIFT)) & SIM_PINSEL1_UART1PS_MASK) 6444 #define SIM_PINSEL1_UART2PS_MASK (0x2000U) 6445 #define SIM_PINSEL1_UART2PS_SHIFT (13U) 6446 /*! UART2PS - UART2 Pin Select 6447 * 0b0..UART2_TX on PTD7, UART2_RX on PTD6. 6448 * 0b1..UART2_TX on PTI1, UART2_RX on PTI0. 6449 */ 6450 #define SIM_PINSEL1_UART2PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_UART2PS_SHIFT)) & SIM_PINSEL1_UART2PS_MASK) 6451 #define SIM_PINSEL1_PWTIN0PS_MASK (0x4000U) 6452 #define SIM_PINSEL1_PWTIN0PS_SHIFT (14U) 6453 /*! PWTIN0PS - PWTIN0 Pin Select 6454 * 0b0..PWTIN0 on PTD5. 6455 * 0b1..PWTIN0 on PTE2. 6456 */ 6457 #define SIM_PINSEL1_PWTIN0PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_PWTIN0PS_SHIFT)) & SIM_PINSEL1_PWTIN0PS_MASK) 6458 #define SIM_PINSEL1_PWTIN1PS_MASK (0x8000U) 6459 #define SIM_PINSEL1_PWTIN1PS_SHIFT (15U) 6460 /*! PWTIN1PS - PWTIN1 Pin Select 6461 * 0b0..PWTIN1 on PTB0. 6462 * 0b1..PWTIN1 on PTH7. 6463 */ 6464 #define SIM_PINSEL1_PWTIN1PS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_PWTIN1PS_SHIFT)) & SIM_PINSEL1_PWTIN1PS_MASK) 6465 #define SIM_PINSEL1_MSCANPS_MASK (0x10000U) 6466 #define SIM_PINSEL1_MSCANPS_SHIFT (16U) 6467 /*! MSCANPS - MSCAN Pin Select 6468 * 0b0..CAN_TX on PTC7, CAN_RX on PTC6. 6469 * 0b1..CAN_TX on PTE7, CAN_RX on PTH2. 6470 */ 6471 #define SIM_PINSEL1_MSCANPS(x) (((uint32_t)(((uint32_t)(x)) << SIM_PINSEL1_MSCANPS_SHIFT)) & SIM_PINSEL1_MSCANPS_MASK) 6472 /*! @} */ 6473 6474 /*! @name SCGC - System Clock Gating Control Register */ 6475 /*! @{ */ 6476 #define SIM_SCGC_RTC_MASK (0x1U) 6477 #define SIM_SCGC_RTC_SHIFT (0U) 6478 /*! RTC - RTC Clock Gate Control 6479 * 0b0..Bus clock to the RTC module is disabled. 6480 * 0b1..Bus clock to the RTC module is enabled. 6481 */ 6482 #define SIM_SCGC_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_RTC_SHIFT)) & SIM_SCGC_RTC_MASK) 6483 #define SIM_SCGC_PIT_MASK (0x2U) 6484 #define SIM_SCGC_PIT_SHIFT (1U) 6485 /*! PIT - PIT Clock Gate Control 6486 * 0b0..Bus clock to the PIT module is disabled. 6487 * 0b1..Bus clock to the PIT module is enabled. 6488 */ 6489 #define SIM_SCGC_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_PIT_SHIFT)) & SIM_SCGC_PIT_MASK) 6490 #define SIM_SCGC_PWT_MASK (0x10U) 6491 #define SIM_SCGC_PWT_SHIFT (4U) 6492 /*! PWT - PWT Clock Gate Control 6493 * 0b0..Timer clock to the PWT module is disabled. 6494 * 0b1..Timer clock to the PWT module is enabled. 6495 */ 6496 #define SIM_SCGC_PWT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_PWT_SHIFT)) & SIM_SCGC_PWT_MASK) 6497 #define SIM_SCGC_FTM0_MASK (0x20U) 6498 #define SIM_SCGC_FTM0_SHIFT (5U) 6499 /*! FTM0 - FTM0 Clock Gate Control 6500 * 0b0..Bus clock to the FTM0 module is disabled. 6501 * 0b1..Bus clock to the FTM0 module is enabled. 6502 */ 6503 #define SIM_SCGC_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM0_SHIFT)) & SIM_SCGC_FTM0_MASK) 6504 #define SIM_SCGC_FTM1_MASK (0x40U) 6505 #define SIM_SCGC_FTM1_SHIFT (6U) 6506 /*! FTM1 - FTM1 Clock Gate Control 6507 * 0b0..Bus clock to the FTM1 module is disabled. 6508 * 0b1..Bus clock to the FTM1 module is enabled. 6509 */ 6510 #define SIM_SCGC_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM1_SHIFT)) & SIM_SCGC_FTM1_MASK) 6511 #define SIM_SCGC_FTM2_MASK (0x80U) 6512 #define SIM_SCGC_FTM2_SHIFT (7U) 6513 /*! FTM2 - FTM2 Clock Gate Control 6514 * 0b0..Bus clock to the FTM2 module is disabled. 6515 * 0b1..Bus clock to the FTM2 module is enabled. 6516 */ 6517 #define SIM_SCGC_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FTM2_SHIFT)) & SIM_SCGC_FTM2_MASK) 6518 #define SIM_SCGC_CRC_MASK (0x400U) 6519 #define SIM_SCGC_CRC_SHIFT (10U) 6520 /*! CRC - CRC Clock Gate Control 6521 * 0b0..Bus clock to the CRC module is disabled. 6522 * 0b1..Bus clock to the CRC module is enabled. 6523 */ 6524 #define SIM_SCGC_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_CRC_SHIFT)) & SIM_SCGC_CRC_MASK) 6525 #define SIM_SCGC_FLASH_MASK (0x1000U) 6526 #define SIM_SCGC_FLASH_SHIFT (12U) 6527 /*! FLASH - Flash Clock Gate Control 6528 * 0b0..Bus clock to the flash module is disabled. 6529 * 0b1..Bus clock to the flash module is enabled. 6530 */ 6531 #define SIM_SCGC_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_FLASH_SHIFT)) & SIM_SCGC_FLASH_MASK) 6532 #define SIM_SCGC_SWD_MASK (0x2000U) 6533 #define SIM_SCGC_SWD_SHIFT (13U) 6534 /*! SWD - SWD (single wire debugger) Clock Gate Control 6535 * 0b0..Bus clock to the SWD module is disabled. 6536 * 0b1..Bus clock to the SWD module is enabled. 6537 */ 6538 #define SIM_SCGC_SWD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SWD_SHIFT)) & SIM_SCGC_SWD_MASK) 6539 #define SIM_SCGC_MSCAN_MASK (0x8000U) 6540 #define SIM_SCGC_MSCAN_SHIFT (15U) 6541 /*! MSCAN - MSCAN Clock Gate Control 6542 * 0b0..Bus clock to the MSCAN module is disabled. 6543 * 0b1..Bus clock to the MSCAN module is enabled. 6544 */ 6545 #define SIM_SCGC_MSCAN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_MSCAN_SHIFT)) & SIM_SCGC_MSCAN_MASK) 6546 #define SIM_SCGC_I2C0_MASK (0x10000U) 6547 #define SIM_SCGC_I2C0_SHIFT (16U) 6548 /*! I2C0 - I2C0 Clock Gate Control 6549 * 0b0..Bus clock to the I2C0 module is disabled. 6550 * 0b1..Bus clock to the I2C0 module is enabled. 6551 */ 6552 #define SIM_SCGC_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_I2C0_SHIFT)) & SIM_SCGC_I2C0_MASK) 6553 #define SIM_SCGC_I2C1_MASK (0x20000U) 6554 #define SIM_SCGC_I2C1_SHIFT (17U) 6555 /*! I2C1 - I2C1 Clock Gate Control 6556 * 0b0..Bus clock to the I2C1 module is disabled. 6557 * 0b1..Bus clock to the I2C1 module is enabled. 6558 */ 6559 #define SIM_SCGC_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_I2C1_SHIFT)) & SIM_SCGC_I2C1_MASK) 6560 #define SIM_SCGC_SPI0_MASK (0x40000U) 6561 #define SIM_SCGC_SPI0_SHIFT (18U) 6562 /*! SPI0 - SPI0 Clock Gate Control 6563 * 0b0..Bus clock to the SPI0 module is disabled. 6564 * 0b1..Bus clock to the SPI0 module is enabled. 6565 */ 6566 #define SIM_SCGC_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SPI0_SHIFT)) & SIM_SCGC_SPI0_MASK) 6567 #define SIM_SCGC_SPI1_MASK (0x80000U) 6568 #define SIM_SCGC_SPI1_SHIFT (19U) 6569 /*! SPI1 - SPI1 Clock Gate Control 6570 * 0b0..Bus clock to the SPI1 module is disabled. 6571 * 0b1..Bus clock to the SPI1 module is enabled. 6572 */ 6573 #define SIM_SCGC_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_SPI1_SHIFT)) & SIM_SCGC_SPI1_MASK) 6574 #define SIM_SCGC_UART0_MASK (0x100000U) 6575 #define SIM_SCGC_UART0_SHIFT (20U) 6576 /*! UART0 - UART0 Clock Gate Control 6577 * 0b0..Bus clock to the UART0 module is disabled. 6578 * 0b1..Bus clock to the UART0 module is enabled. 6579 */ 6580 #define SIM_SCGC_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART0_SHIFT)) & SIM_SCGC_UART0_MASK) 6581 #define SIM_SCGC_UART1_MASK (0x200000U) 6582 #define SIM_SCGC_UART1_SHIFT (21U) 6583 /*! UART1 - UART1 Clock Gate Control 6584 * 0b0..Bus clock to the UART1 module is disabled. 6585 * 0b1..Bus clock to the UART1 module is enabled. 6586 */ 6587 #define SIM_SCGC_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART1_SHIFT)) & SIM_SCGC_UART1_MASK) 6588 #define SIM_SCGC_UART2_MASK (0x400000U) 6589 #define SIM_SCGC_UART2_SHIFT (22U) 6590 /*! UART2 - UART2 Clock Gate Control 6591 * 0b0..Bus clock to the UART2 module is disabled. 6592 * 0b1..Bus clock to the UART2 module is enabled. 6593 */ 6594 #define SIM_SCGC_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_UART2_SHIFT)) & SIM_SCGC_UART2_MASK) 6595 #define SIM_SCGC_KBI0_MASK (0x1000000U) 6596 #define SIM_SCGC_KBI0_SHIFT (24U) 6597 /*! KBI0 - KBI0 Clock Gate Control 6598 * 0b0..Bus clock to the KBI0 module is disabled. 6599 * 0b1..Bus clock to the KBI0 module is enabled. 6600 */ 6601 #define SIM_SCGC_KBI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_KBI0_SHIFT)) & SIM_SCGC_KBI0_MASK) 6602 #define SIM_SCGC_KBI1_MASK (0x2000000U) 6603 #define SIM_SCGC_KBI1_SHIFT (25U) 6604 /*! KBI1 - KBI1 Clock Gate Control 6605 * 0b0..Bus clock to the KBI1 module is disabled. 6606 * 0b1..Bus clock to the KBI1 module is enabled. 6607 */ 6608 #define SIM_SCGC_KBI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_KBI1_SHIFT)) & SIM_SCGC_KBI1_MASK) 6609 #define SIM_SCGC_IRQ_MASK (0x8000000U) 6610 #define SIM_SCGC_IRQ_SHIFT (27U) 6611 /*! IRQ - IRQ Clock Gate Control 6612 * 0b0..Bus clock to the IRQ module is disabled. 6613 * 0b1..Bus clock to the IRQ module is enabled. 6614 */ 6615 #define SIM_SCGC_IRQ(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_IRQ_SHIFT)) & SIM_SCGC_IRQ_MASK) 6616 #define SIM_SCGC_ADC_MASK (0x20000000U) 6617 #define SIM_SCGC_ADC_SHIFT (29U) 6618 /*! ADC - ADC Clock Gate Control 6619 * 0b0..Bus clock to the ADC module is disabled. 6620 * 0b1..Bus clock to the ADC module is enabled. 6621 */ 6622 #define SIM_SCGC_ADC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ADC_SHIFT)) & SIM_SCGC_ADC_MASK) 6623 #define SIM_SCGC_ACMP0_MASK (0x40000000U) 6624 #define SIM_SCGC_ACMP0_SHIFT (30U) 6625 /*! ACMP0 - ACMP0 Clock Gate Control 6626 * 0b0..Bus clock to the ACMP0 module is disabled. 6627 * 0b1..Bus clock to the ACMP0 module is enabled. 6628 */ 6629 #define SIM_SCGC_ACMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ACMP0_SHIFT)) & SIM_SCGC_ACMP0_MASK) 6630 #define SIM_SCGC_ACMP1_MASK (0x80000000U) 6631 #define SIM_SCGC_ACMP1_SHIFT (31U) 6632 /*! ACMP1 - ACMP1 Clock Gate Control 6633 * 0b0..Bus clock to the ACMP1 module is disabled. 6634 * 0b1..Bus clock to the ACMP1 module is enabled. 6635 */ 6636 #define SIM_SCGC_ACMP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC_ACMP1_SHIFT)) & SIM_SCGC_ACMP1_MASK) 6637 /*! @} */ 6638 6639 /*! @name UUIDL - Universally Unique Identifier Low Register */ 6640 /*! @{ */ 6641 #define SIM_UUIDL_ID_MASK (0xFFFFFFFFU) 6642 #define SIM_UUIDL_ID_SHIFT (0U) 6643 #define SIM_UUIDL_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDL_ID_SHIFT)) & SIM_UUIDL_ID_MASK) 6644 /*! @} */ 6645 6646 /*! @name UUIDML - Universally Unique Identifier Middle Low Register */ 6647 /*! @{ */ 6648 #define SIM_UUIDML_ID_MASK (0xFFFFFFFFU) 6649 #define SIM_UUIDML_ID_SHIFT (0U) 6650 #define SIM_UUIDML_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDML_ID_SHIFT)) & SIM_UUIDML_ID_MASK) 6651 /*! @} */ 6652 6653 /*! @name UUIDMH - Universally Unique Identifier Middle High Register */ 6654 /*! @{ */ 6655 #define SIM_UUIDMH_ID_MASK (0xFFFFU) 6656 #define SIM_UUIDMH_ID_SHIFT (0U) 6657 #define SIM_UUIDMH_ID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UUIDMH_ID_SHIFT)) & SIM_UUIDMH_ID_MASK) 6658 /*! @} */ 6659 6660 /*! @name CLKDIV - Clock Divider Register */ 6661 /*! @{ */ 6662 #define SIM_CLKDIV_OUTDIV3_MASK (0x100000U) 6663 #define SIM_CLKDIV_OUTDIV3_SHIFT (20U) 6664 /*! OUTDIV3 - Clock 3 output divider value 6665 * 0b0..Same as ICSOUTCLK. 6666 * 0b1..ICSOUTCLK divides by 2. 6667 */ 6668 #define SIM_CLKDIV_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV_OUTDIV3_SHIFT)) & SIM_CLKDIV_OUTDIV3_MASK) 6669 #define SIM_CLKDIV_OUTDIV2_MASK (0x1000000U) 6670 #define SIM_CLKDIV_OUTDIV2_SHIFT (24U) 6671 /*! OUTDIV2 - Clock 2 output divider value 6672 * 0b0..Not divided from divider1. 6673 * 0b1..Divide by 2 from divider1. 6674 */ 6675 #define SIM_CLKDIV_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV_OUTDIV2_SHIFT)) & SIM_CLKDIV_OUTDIV2_MASK) 6676 #define SIM_CLKDIV_OUTDIV1_MASK (0x30000000U) 6677 #define SIM_CLKDIV_OUTDIV1_SHIFT (28U) 6678 /*! OUTDIV1 - Clock 1 output divider value 6679 * 0b00..Same as ICSOUTCLK. 6680 * 0b01..ICSOUTCLK divides by 2. 6681 * 0b10..ICSOUTCLK divides by 3. 6682 * 0b11..ICSOUTCLK divides by 4. 6683 */ 6684 #define SIM_CLKDIV_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV_OUTDIV1_SHIFT)) & SIM_CLKDIV_OUTDIV1_MASK) 6685 /*! @} */ 6686 6687 6688 /*! 6689 * @} 6690 */ /* end of group SIM_Register_Masks */ 6691 6692 6693 /* SIM - Peripheral instance base addresses */ 6694 /** Peripheral SIM base address */ 6695 #define SIM_BASE (0x40048000u) 6696 /** Peripheral SIM base pointer */ 6697 #define SIM ((SIM_Type *)SIM_BASE) 6698 /** Array initializer of SIM peripheral base addresses */ 6699 #define SIM_BASE_ADDRS { SIM_BASE } 6700 /** Array initializer of SIM peripheral base pointers */ 6701 #define SIM_BASE_PTRS { SIM } 6702 6703 /*! 6704 * @} 6705 */ /* end of group SIM_Peripheral_Access_Layer */ 6706 6707 6708 /* ---------------------------------------------------------------------------- 6709 -- SPI Peripheral Access Layer 6710 ---------------------------------------------------------------------------- */ 6711 6712 /*! 6713 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 6714 * @{ 6715 */ 6716 6717 /** SPI - Register Layout Typedef */ 6718 typedef struct { 6719 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x0 */ 6720 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x1 */ 6721 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x2 */ 6722 __IO uint8_t S; /**< SPI Status Register, offset: 0x3 */ 6723 uint8_t RESERVED_0[1]; 6724 __IO uint8_t D; /**< SPI Data Register, offset: 0x5 */ 6725 uint8_t RESERVED_1[1]; 6726 __IO uint8_t M; /**< SPI Match Register, offset: 0x7 */ 6727 } SPI_Type; 6728 6729 /* ---------------------------------------------------------------------------- 6730 -- SPI Register Masks 6731 ---------------------------------------------------------------------------- */ 6732 6733 /*! 6734 * @addtogroup SPI_Register_Masks SPI Register Masks 6735 * @{ 6736 */ 6737 6738 /*! @name C1 - SPI Control Register 1 */ 6739 /*! @{ */ 6740 #define SPI_C1_LSBFE_MASK (0x1U) 6741 #define SPI_C1_LSBFE_SHIFT (0U) 6742 /*! LSBFE - LSB First (shifter direction) 6743 * 0b0..SPI serial data transfers start with the most significant bit. 6744 * 0b1..SPI serial data transfers start with the least significant bit. 6745 */ 6746 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 6747 #define SPI_C1_SSOE_MASK (0x2U) 6748 #define SPI_C1_SSOE_SHIFT (1U) 6749 /*! SSOE - Slave Select Output Enable 6750 * 0b0..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input. 6751 * 0b1..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input. 6752 */ 6753 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 6754 #define SPI_C1_CPHA_MASK (0x4U) 6755 #define SPI_C1_CPHA_SHIFT (2U) 6756 /*! CPHA - Clock Phase 6757 * 0b0..First edge on SPSCK occurs at the middle of the first cycle of a data transfer. 6758 * 0b1..First edge on SPSCK occurs at the start of the first cycle of a data transfer. 6759 */ 6760 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 6761 #define SPI_C1_CPOL_MASK (0x8U) 6762 #define SPI_C1_CPOL_SHIFT (3U) 6763 /*! CPOL - Clock Polarity 6764 * 0b0..Active-high SPI clock (idles low) 6765 * 0b1..Active-low SPI clock (idles high) 6766 */ 6767 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 6768 #define SPI_C1_MSTR_MASK (0x10U) 6769 #define SPI_C1_MSTR_SHIFT (4U) 6770 /*! MSTR - Master/Slave Mode Select 6771 * 0b0..SPI module configured as a slave SPI device 6772 * 0b1..SPI module configured as a master SPI device 6773 */ 6774 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 6775 #define SPI_C1_SPTIE_MASK (0x20U) 6776 #define SPI_C1_SPTIE_SHIFT (5U) 6777 /*! SPTIE - SPI Transmit Interrupt Enable 6778 * 0b0..Interrupts from SPTEF inhibited (use polling) 6779 * 0b1..When SPTEF is 1, hardware interrupt requested 6780 */ 6781 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 6782 #define SPI_C1_SPE_MASK (0x40U) 6783 #define SPI_C1_SPE_SHIFT (6U) 6784 /*! SPE - SPI System Enable 6785 * 0b0..SPI system inactive 6786 * 0b1..SPI system enabled 6787 */ 6788 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 6789 #define SPI_C1_SPIE_MASK (0x80U) 6790 #define SPI_C1_SPIE_SHIFT (7U) 6791 /*! SPIE - SPI Interrupt Enable: for SPRF and MODF 6792 * 0b0..Interrupts from SPRF and MODF are inhibited-use polling 6793 * 0b1..Request a hardware interrupt when SPRF or MODF is 1 6794 */ 6795 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 6796 /*! @} */ 6797 6798 /*! @name C2 - SPI Control Register 2 */ 6799 /*! @{ */ 6800 #define SPI_C2_SPC0_MASK (0x1U) 6801 #define SPI_C2_SPC0_SHIFT (0U) 6802 /*! SPC0 - SPI Pin Control 0 6803 * 0b0..SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in. 6804 * 0b1..SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI. 6805 */ 6806 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 6807 #define SPI_C2_SPISWAI_MASK (0x2U) 6808 #define SPI_C2_SPISWAI_SHIFT (1U) 6809 /*! SPISWAI - SPI Stop in Wait Mode 6810 * 0b0..SPI clocks continue to operate in Wait mode. 6811 * 0b1..SPI clocks stop when the MCU enters Wait mode. 6812 */ 6813 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 6814 #define SPI_C2_BIDIROE_MASK (0x8U) 6815 #define SPI_C2_BIDIROE_SHIFT (3U) 6816 /*! BIDIROE - Bidirectional Mode Output Enable 6817 * 0b0..Output driver disabled so SPI data I/O pin acts as an input 6818 * 0b1..SPI I/O pin enabled as an output 6819 */ 6820 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 6821 #define SPI_C2_MODFEN_MASK (0x10U) 6822 #define SPI_C2_MODFEN_SHIFT (4U) 6823 /*! MODFEN - Master Mode-Fault Function Enable 6824 * 0b0..Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 6825 * 0b1..Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output 6826 */ 6827 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 6828 #define SPI_C2_SPMIE_MASK (0x80U) 6829 #define SPI_C2_SPMIE_SHIFT (7U) 6830 /*! SPMIE - SPI Match Interrupt Enable 6831 * 0b0..Interrupts from SPMF inhibited (use polling) 6832 * 0b1..When SPMF is 1, requests a hardware interrupt 6833 */ 6834 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 6835 /*! @} */ 6836 6837 /*! @name BR - SPI Baud Rate Register */ 6838 /*! @{ */ 6839 #define SPI_BR_SPR_MASK (0xFU) 6840 #define SPI_BR_SPR_SHIFT (0U) 6841 /*! SPR - SPI Baud Rate Divisor 6842 * 0b0000..Baud rate divisor is 2. 6843 * 0b0001..Baud rate divisor is 4. 6844 * 0b0010..Baud rate divisor is 8. 6845 * 0b0011..Baud rate divisor is 16. 6846 * 0b0100..Baud rate divisor is 32. 6847 * 0b0101..Baud rate divisor is 64. 6848 * 0b0110..Baud rate divisor is 128. 6849 * 0b0111..Baud rate divisor is 256. 6850 * 0b1000..Baud rate divisor is 512. 6851 */ 6852 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 6853 #define SPI_BR_SPPR_MASK (0x70U) 6854 #define SPI_BR_SPPR_SHIFT (4U) 6855 /*! SPPR - SPI Baud Rate Prescale Divisor 6856 * 0b000..Baud rate prescaler divisor is 1. 6857 * 0b001..Baud rate prescaler divisor is 2. 6858 * 0b010..Baud rate prescaler divisor is 3. 6859 * 0b011..Baud rate prescaler divisor is 4. 6860 * 0b100..Baud rate prescaler divisor is 5. 6861 * 0b101..Baud rate prescaler divisor is 6. 6862 * 0b110..Baud rate prescaler divisor is 7. 6863 * 0b111..Baud rate prescaler divisor is 8. 6864 */ 6865 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 6866 /*! @} */ 6867 6868 /*! @name S - SPI Status Register */ 6869 /*! @{ */ 6870 #define SPI_S_MODF_MASK (0x10U) 6871 #define SPI_S_MODF_SHIFT (4U) 6872 /*! MODF - Master Mode Fault Flag 6873 * 0b0..No mode fault error 6874 * 0b1..Mode fault error detected 6875 */ 6876 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 6877 #define SPI_S_SPTEF_MASK (0x20U) 6878 #define SPI_S_SPTEF_SHIFT (5U) 6879 /*! SPTEF - SPI Transmit Buffer Empty Flag 6880 * 0b0..SPI transmit buffer not empty 6881 * 0b1..SPI transmit buffer empty 6882 */ 6883 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 6884 #define SPI_S_SPMF_MASK (0x40U) 6885 #define SPI_S_SPMF_SHIFT (6U) 6886 /*! SPMF - SPI Match Flag 6887 * 0b0..Value in the receive data buffer does not match the value in the M register 6888 * 0b1..Value in the receive data buffer matches the value in the M register 6889 */ 6890 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 6891 #define SPI_S_SPRF_MASK (0x80U) 6892 #define SPI_S_SPRF_SHIFT (7U) 6893 /*! SPRF - SPI Read Buffer Full Flag 6894 * 0b0..No data available in the receive data buffer 6895 * 0b1..Data available in the receive data buffer 6896 */ 6897 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 6898 /*! @} */ 6899 6900 /*! @name D - SPI Data Register */ 6901 /*! @{ */ 6902 #define SPI_D_Bits_MASK (0xFFU) 6903 #define SPI_D_Bits_SHIFT (0U) 6904 #define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_D_Bits_SHIFT)) & SPI_D_Bits_MASK) 6905 /*! @} */ 6906 6907 /*! @name M - SPI Match Register */ 6908 /*! @{ */ 6909 #define SPI_M_Bits_MASK (0xFFU) 6910 #define SPI_M_Bits_SHIFT (0U) 6911 #define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_M_Bits_SHIFT)) & SPI_M_Bits_MASK) 6912 /*! @} */ 6913 6914 6915 /*! 6916 * @} 6917 */ /* end of group SPI_Register_Masks */ 6918 6919 6920 /* SPI - Peripheral instance base addresses */ 6921 /** Peripheral SPI0 base address */ 6922 #define SPI0_BASE (0x40076000u) 6923 /** Peripheral SPI0 base pointer */ 6924 #define SPI0 ((SPI_Type *)SPI0_BASE) 6925 /** Peripheral SPI1 base address */ 6926 #define SPI1_BASE (0x40077000u) 6927 /** Peripheral SPI1 base pointer */ 6928 #define SPI1 ((SPI_Type *)SPI1_BASE) 6929 /** Array initializer of SPI peripheral base addresses */ 6930 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } 6931 /** Array initializer of SPI peripheral base pointers */ 6932 #define SPI_BASE_PTRS { SPI0, SPI1 } 6933 /** Interrupt vectors for the SPI peripheral type */ 6934 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } 6935 6936 /*! 6937 * @} 6938 */ /* end of group SPI_Peripheral_Access_Layer */ 6939 6940 6941 /* ---------------------------------------------------------------------------- 6942 -- UART Peripheral Access Layer 6943 ---------------------------------------------------------------------------- */ 6944 6945 /*! 6946 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 6947 * @{ 6948 */ 6949 6950 /** UART - Register Layout Typedef */ 6951 typedef struct { 6952 __IO uint8_t BDH; /**< UART Baud Rate Register: High, offset: 0x0 */ 6953 __IO uint8_t BDL; /**< UART Baud Rate Register: Low, offset: 0x1 */ 6954 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 6955 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 6956 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 6957 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 6958 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 6959 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 6960 } UART_Type; 6961 6962 /* ---------------------------------------------------------------------------- 6963 -- UART Register Masks 6964 ---------------------------------------------------------------------------- */ 6965 6966 /*! 6967 * @addtogroup UART_Register_Masks UART Register Masks 6968 * @{ 6969 */ 6970 6971 /*! @name BDH - UART Baud Rate Register: High */ 6972 /*! @{ */ 6973 #define UART_BDH_SBR_MASK (0x1FU) 6974 #define UART_BDH_SBR_SHIFT (0U) 6975 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 6976 #define UART_BDH_SBNS_MASK (0x20U) 6977 #define UART_BDH_SBNS_SHIFT (5U) 6978 /*! SBNS - Stop Bit Number Select 6979 * 0b0..One stop bit. 6980 * 0b1..Two stop bit. 6981 */ 6982 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK) 6983 #define UART_BDH_RXEDGIE_MASK (0x40U) 6984 #define UART_BDH_RXEDGIE_SHIFT (6U) 6985 /*! RXEDGIE - RxD Input Active Edge Interrupt Enable (for RXEDGIF) 6986 * 0b0..Hardware interrupts from UART_S2[RXEDGIF] disabled (use polling). 6987 * 0b1..Hardware interrupt requested when UART_S2[RXEDGIF] flag is 1. 6988 */ 6989 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 6990 #define UART_BDH_LBKDIE_MASK (0x80U) 6991 #define UART_BDH_LBKDIE_SHIFT (7U) 6992 /*! LBKDIE - LIN Break Detect Interrupt Enable (for LBKDIF) 6993 * 0b0..Hardware interrupts from UART_S2[LBKDIF] disabled (use polling). 6994 * 0b1..Hardware interrupt requested when UART_S2[LBKDIF] flag is 1. 6995 */ 6996 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK) 6997 /*! @} */ 6998 6999 /*! @name BDL - UART Baud Rate Register: Low */ 7000 /*! @{ */ 7001 #define UART_BDL_SBR_MASK (0xFFU) 7002 #define UART_BDL_SBR_SHIFT (0U) 7003 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 7004 /*! @} */ 7005 7006 /*! @name C1 - UART Control Register 1 */ 7007 /*! @{ */ 7008 #define UART_C1_PT_MASK (0x1U) 7009 #define UART_C1_PT_SHIFT (0U) 7010 /*! PT - Parity Type 7011 * 0b0..Even parity. 7012 * 0b1..Odd parity. 7013 */ 7014 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 7015 #define UART_C1_PE_MASK (0x2U) 7016 #define UART_C1_PE_SHIFT (1U) 7017 /*! PE - Parity Enable 7018 * 0b0..No hardware parity generation or checking. 7019 * 0b1..Parity enabled. 7020 */ 7021 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 7022 #define UART_C1_ILT_MASK (0x4U) 7023 #define UART_C1_ILT_SHIFT (2U) 7024 /*! ILT - Idle Line Type Select 7025 * 0b0..Idle character bit count starts after start bit. 7026 * 0b1..Idle character bit count starts after stop bit. 7027 */ 7028 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 7029 #define UART_C1_WAKE_MASK (0x8U) 7030 #define UART_C1_WAKE_SHIFT (3U) 7031 /*! WAKE - Receiver Wakeup Method Select 7032 * 0b0..Idle-line wake-up. 7033 * 0b1..Address-mark wake-up. 7034 */ 7035 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 7036 #define UART_C1_M_MASK (0x10U) 7037 #define UART_C1_M_SHIFT (4U) 7038 /*! M - 9-Bit or 8-Bit Mode Select 7039 * 0b0..Normal - start + 8 data bits (lsb first) + stop. 7040 * 0b1..Receiver and transmitter use 9-bit data characters start + 8 data bits (lsb first) + 9th data bit + stop. 7041 */ 7042 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 7043 #define UART_C1_RSRC_MASK (0x20U) 7044 #define UART_C1_RSRC_SHIFT (5U) 7045 /*! RSRC - Receiver Source Select 7046 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the UART does not use the RxD pins. 7047 * 0b1..Single-wire UART mode where the TxD pin is connected to the transmitter output and receiver input. 7048 */ 7049 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 7050 #define UART_C1_UARTSWAI_MASK (0x40U) 7051 #define UART_C1_UARTSWAI_SHIFT (6U) 7052 /*! UARTSWAI - UART Stops in Wait Mode 7053 * 0b0..UART clocks continue to run in Wait mode so the UART can be the source of an interrupt that wakes up the CPU. 7054 * 0b1..UART clocks freeze while CPU is in Wait mode. 7055 */ 7056 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK) 7057 #define UART_C1_LOOPS_MASK (0x80U) 7058 #define UART_C1_LOOPS_SHIFT (7U) 7059 /*! LOOPS - Loop Mode Select 7060 * 0b0..Normal operation - RxD and TxD use separate pins. 7061 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) RxD pin is not used by UART. 7062 */ 7063 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 7064 /*! @} */ 7065 7066 /*! @name C2 - UART Control Register 2 */ 7067 /*! @{ */ 7068 #define UART_C2_SBK_MASK (0x1U) 7069 #define UART_C2_SBK_SHIFT (0U) 7070 /*! SBK - Send Break 7071 * 0b0..Normal transmitter operation. 7072 * 0b1..Queue break character(s) to be sent. 7073 */ 7074 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 7075 #define UART_C2_RWU_MASK (0x2U) 7076 #define UART_C2_RWU_SHIFT (1U) 7077 /*! RWU - Receiver Wakeup Control 7078 * 0b0..Normal UART receiver operation. 7079 * 0b1..UART receiver in standby waiting for wake-up condition. 7080 */ 7081 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 7082 #define UART_C2_RE_MASK (0x4U) 7083 #define UART_C2_RE_SHIFT (2U) 7084 /*! RE - Receiver Enable 7085 * 0b0..Receiver off. 7086 * 0b1..Receiver on. 7087 */ 7088 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 7089 #define UART_C2_TE_MASK (0x8U) 7090 #define UART_C2_TE_SHIFT (3U) 7091 /*! TE - Transmitter Enable 7092 * 0b0..Transmitter off. 7093 * 0b1..Transmitter on. 7094 */ 7095 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 7096 #define UART_C2_ILIE_MASK (0x10U) 7097 #define UART_C2_ILIE_SHIFT (4U) 7098 /*! ILIE - Idle Line Interrupt Enable for IDLE 7099 * 0b0..Hardware interrupts from S1[IDLE] disabled; use polling. 7100 * 0b1..Hardware interrupt requested when S1[IDLE] flag is 1. 7101 */ 7102 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 7103 #define UART_C2_RIE_MASK (0x20U) 7104 #define UART_C2_RIE_SHIFT (5U) 7105 /*! RIE - Receiver Interrupt Enable for RDRF 7106 * 0b0..Hardware interrupts from S1[RDRF] disabled; use polling. 7107 * 0b1..Hardware interrupt requested when S1[RDRF] flag is 1. 7108 */ 7109 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 7110 #define UART_C2_TCIE_MASK (0x40U) 7111 #define UART_C2_TCIE_SHIFT (6U) 7112 /*! TCIE - Transmission Complete Interrupt Enable for TC 7113 * 0b0..Hardware interrupts from TC disabled; use polling. 7114 * 0b1..Hardware interrupt requested when TC flag is 1. 7115 */ 7116 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 7117 #define UART_C2_TIE_MASK (0x80U) 7118 #define UART_C2_TIE_SHIFT (7U) 7119 /*! TIE - Transmit Interrupt Enable for TDRE 7120 * 0b0..Hardware interrupts from TDRE disabled; use polling. 7121 * 0b1..Hardware interrupt requested when TDRE flag is 1. 7122 */ 7123 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 7124 /*! @} */ 7125 7126 /*! @name S1 - UART Status Register 1 */ 7127 /*! @{ */ 7128 #define UART_S1_PF_MASK (0x1U) 7129 #define UART_S1_PF_SHIFT (0U) 7130 /*! PF - Parity Error Flag 7131 * 0b0..No parity error. 7132 * 0b1..Parity error. 7133 */ 7134 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 7135 #define UART_S1_FE_MASK (0x2U) 7136 #define UART_S1_FE_SHIFT (1U) 7137 /*! FE - Framing Error Flag 7138 * 0b0..No framing error detected. This does not guarantee the framing is correct. 7139 * 0b1..Framing error. 7140 */ 7141 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 7142 #define UART_S1_NF_MASK (0x4U) 7143 #define UART_S1_NF_SHIFT (2U) 7144 /*! NF - Noise Flag 7145 * 0b0..No noise detected. 7146 * 0b1..Noise detected in the received character in UART_D. 7147 */ 7148 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 7149 #define UART_S1_OR_MASK (0x8U) 7150 #define UART_S1_OR_SHIFT (3U) 7151 /*! OR - Receiver Overrun Flag 7152 * 0b0..No overrun. 7153 * 0b1..Receive overrun (new UART data lost). 7154 */ 7155 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 7156 #define UART_S1_IDLE_MASK (0x10U) 7157 #define UART_S1_IDLE_SHIFT (4U) 7158 /*! IDLE - Idle Line Flag 7159 * 0b0..No idle line detected. 7160 * 0b1..Idle line was detected. 7161 */ 7162 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 7163 #define UART_S1_RDRF_MASK (0x20U) 7164 #define UART_S1_RDRF_SHIFT (5U) 7165 /*! RDRF - Receive Data Register Full Flag 7166 * 0b0..Receive data register empty. 7167 * 0b1..Receive data register full. 7168 */ 7169 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 7170 #define UART_S1_TC_MASK (0x40U) 7171 #define UART_S1_TC_SHIFT (6U) 7172 /*! TC - Transmission Complete Flag 7173 * 0b0..Transmitter active (sending data, a preamble, or a break). 7174 * 0b1..Transmitter idle (transmission activity complete). 7175 */ 7176 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 7177 #define UART_S1_TDRE_MASK (0x80U) 7178 #define UART_S1_TDRE_SHIFT (7U) 7179 /*! TDRE - Transmit Data Register Empty Flag 7180 * 0b0..Transmit data register (buffer) full. 7181 * 0b1..Transmit data register (buffer) empty. 7182 */ 7183 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 7184 /*! @} */ 7185 7186 /*! @name S2 - UART Status Register 2 */ 7187 /*! @{ */ 7188 #define UART_S2_RAF_MASK (0x1U) 7189 #define UART_S2_RAF_SHIFT (0U) 7190 /*! RAF - Receiver Active Flag 7191 * 0b0..UART receiver idle waiting for a start bit. 7192 * 0b1..UART receiver active (RxD input not idle). 7193 */ 7194 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 7195 #define UART_S2_LBKDE_MASK (0x2U) 7196 #define UART_S2_LBKDE_SHIFT (1U) 7197 /*! LBKDE - LIN Break Detection Enable 7198 * 0b0..Break detection is disabled. 7199 * 0b1..Break detection is enabled (Break character is detected at length 11 bit times (if C1[M] = 0, BDH[SBNS] = 0) or 12 (if C1[M] = 1, BDH[SBNS] = 0 or C1[M] = 0, BDH[SBNS] = 1) or 13 (if C1[M] = 1, BDH[SBNS] = 1)). 7200 */ 7201 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK) 7202 #define UART_S2_BRK13_MASK (0x4U) 7203 #define UART_S2_BRK13_SHIFT (2U) 7204 /*! BRK13 - Break Character Generation Length 7205 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1). 7206 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1). 7207 */ 7208 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 7209 #define UART_S2_RWUID_MASK (0x8U) 7210 #define UART_S2_RWUID_SHIFT (3U) 7211 /*! RWUID - Receive Wake Up Idle Detect 7212 * 0b0..During receive standby state (RWU = 1), S1[IDLE] does not get set upon detection of an idle character. 7213 * 0b1..During receive standby state (RWU = 1), S1[IDLE] gets set upon detection of an idle character. 7214 */ 7215 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 7216 #define UART_S2_RXINV_MASK (0x10U) 7217 #define UART_S2_RXINV_SHIFT (4U) 7218 /*! RXINV - Receive Data Inversion 7219 * 0b0..Receive data not inverted. 7220 * 0b1..Receive data inverted. 7221 */ 7222 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 7223 #define UART_S2_RXEDGIF_MASK (0x40U) 7224 #define UART_S2_RXEDGIF_SHIFT (6U) 7225 /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag 7226 * 0b0..No active edge on the receive pin has occurred. 7227 * 0b1..An active edge on the receive pin has occurred. 7228 */ 7229 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 7230 #define UART_S2_LBKDIF_MASK (0x80U) 7231 #define UART_S2_LBKDIF_SHIFT (7U) 7232 /*! LBKDIF - LIN Break Detect Interrupt Flag 7233 * 0b0..No LIN break character has been detected. 7234 * 0b1..LIN break character has been detected. 7235 */ 7236 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK) 7237 /*! @} */ 7238 7239 /*! @name C3 - UART Control Register 3 */ 7240 /*! @{ */ 7241 #define UART_C3_PEIE_MASK (0x1U) 7242 #define UART_C3_PEIE_SHIFT (0U) 7243 /*! PEIE - Parity Error Interrupt Enable 7244 * 0b0..PF interrupts disabled; use polling). 7245 * 0b1..Hardware interrupt requested when PF is set. 7246 */ 7247 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 7248 #define UART_C3_FEIE_MASK (0x2U) 7249 #define UART_C3_FEIE_SHIFT (1U) 7250 /*! FEIE - Framing Error Interrupt Enable 7251 * 0b0..FE interrupts disabled; use polling). 7252 * 0b1..Hardware interrupt requested when FE is set. 7253 */ 7254 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 7255 #define UART_C3_NEIE_MASK (0x4U) 7256 #define UART_C3_NEIE_SHIFT (2U) 7257 /*! NEIE - Noise Error Interrupt Enable 7258 * 0b0..NF interrupts disabled; use polling). 7259 * 0b1..Hardware interrupt requested when NF is set. 7260 */ 7261 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 7262 #define UART_C3_ORIE_MASK (0x8U) 7263 #define UART_C3_ORIE_SHIFT (3U) 7264 /*! ORIE - Overrun Interrupt Enable 7265 * 0b0..OR interrupts disabled; use polling. 7266 * 0b1..Hardware interrupt requested when OR is set. 7267 */ 7268 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 7269 #define UART_C3_TXINV_MASK (0x10U) 7270 #define UART_C3_TXINV_SHIFT (4U) 7271 /*! TXINV - Transmit Data Inversion 7272 * 0b0..Transmit data not inverted. 7273 * 0b1..Transmit data inverted. 7274 */ 7275 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 7276 #define UART_C3_TXDIR_MASK (0x20U) 7277 #define UART_C3_TXDIR_SHIFT (5U) 7278 /*! TXDIR - TxD Pin Direction in Single-Wire Mode 7279 * 0b0..TxD pin is an input in single-wire mode. 7280 * 0b1..TxD pin is an output in single-wire mode. 7281 */ 7282 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 7283 #define UART_C3_T8_MASK (0x40U) 7284 #define UART_C3_T8_SHIFT (6U) 7285 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 7286 #define UART_C3_R8_MASK (0x80U) 7287 #define UART_C3_R8_SHIFT (7U) 7288 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 7289 /*! @} */ 7290 7291 /*! @name D - UART Data Register */ 7292 /*! @{ */ 7293 #define UART_D_R0T0_MASK (0x1U) 7294 #define UART_D_R0T0_SHIFT (0U) 7295 #define UART_D_R0T0(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R0T0_SHIFT)) & UART_D_R0T0_MASK) 7296 #define UART_D_R1T1_MASK (0x2U) 7297 #define UART_D_R1T1_SHIFT (1U) 7298 #define UART_D_R1T1(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R1T1_SHIFT)) & UART_D_R1T1_MASK) 7299 #define UART_D_R2T2_MASK (0x4U) 7300 #define UART_D_R2T2_SHIFT (2U) 7301 #define UART_D_R2T2(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R2T2_SHIFT)) & UART_D_R2T2_MASK) 7302 #define UART_D_R3T3_MASK (0x8U) 7303 #define UART_D_R3T3_SHIFT (3U) 7304 #define UART_D_R3T3(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R3T3_SHIFT)) & UART_D_R3T3_MASK) 7305 #define UART_D_R4T4_MASK (0x10U) 7306 #define UART_D_R4T4_SHIFT (4U) 7307 #define UART_D_R4T4(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R4T4_SHIFT)) & UART_D_R4T4_MASK) 7308 #define UART_D_R5T5_MASK (0x20U) 7309 #define UART_D_R5T5_SHIFT (5U) 7310 #define UART_D_R5T5(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R5T5_SHIFT)) & UART_D_R5T5_MASK) 7311 #define UART_D_R6T6_MASK (0x40U) 7312 #define UART_D_R6T6_SHIFT (6U) 7313 #define UART_D_R6T6(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R6T6_SHIFT)) & UART_D_R6T6_MASK) 7314 #define UART_D_R7T7_MASK (0x80U) 7315 #define UART_D_R7T7_SHIFT (7U) 7316 #define UART_D_R7T7(x) (((uint8_t)(((uint8_t)(x)) << UART_D_R7T7_SHIFT)) & UART_D_R7T7_MASK) 7317 /*! @} */ 7318 7319 7320 /*! 7321 * @} 7322 */ /* end of group UART_Register_Masks */ 7323 7324 7325 /* UART - Peripheral instance base addresses */ 7326 /** Peripheral UART0 base address */ 7327 #define UART0_BASE (0x4006A000u) 7328 /** Peripheral UART0 base pointer */ 7329 #define UART0 ((UART_Type *)UART0_BASE) 7330 /** Peripheral UART1 base address */ 7331 #define UART1_BASE (0x4006B000u) 7332 /** Peripheral UART1 base pointer */ 7333 #define UART1 ((UART_Type *)UART1_BASE) 7334 /** Peripheral UART2 base address */ 7335 #define UART2_BASE (0x4006C000u) 7336 /** Peripheral UART2 base pointer */ 7337 #define UART2 ((UART_Type *)UART2_BASE) 7338 /** Array initializer of UART peripheral base addresses */ 7339 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE } 7340 /** Array initializer of UART peripheral base pointers */ 7341 #define UART_BASE_PTRS { UART0, UART1, UART2 } 7342 /** Interrupt vectors for the UART peripheral type */ 7343 #define UART_RX_TX_IRQS { UART0_IRQn, UART1_IRQn, UART2_IRQn } 7344 #define UART_ERR_IRQS { UART0_IRQn, UART1_IRQn, UART2_IRQn } 7345 7346 /*! 7347 * @} 7348 */ /* end of group UART_Peripheral_Access_Layer */ 7349 7350 7351 /* ---------------------------------------------------------------------------- 7352 -- WDOG Peripheral Access Layer 7353 ---------------------------------------------------------------------------- */ 7354 7355 /*! 7356 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 7357 * @{ 7358 */ 7359 7360 /** WDOG - Register Layout Typedef */ 7361 typedef struct { 7362 __IO uint8_t CS1; /**< Watchdog Control and Status Register 1, offset: 0x0 */ 7363 __IO uint8_t CS2; /**< Watchdog Control and Status Register 2, offset: 0x1 */ 7364 union { /* offset: 0x2 */ 7365 __IO uint16_t CNT; /**< WDOG_CNT register., offset: 0x2 */ 7366 struct { /* offset: 0x2 */ 7367 __IO uint8_t CNTH; /**< Watchdog Counter Register: High, offset: 0x2 */ 7368 __IO uint8_t CNTL; /**< Watchdog Counter Register: Low, offset: 0x3 */ 7369 } CNT8B; 7370 }; 7371 union { /* offset: 0x4 */ 7372 __IO uint16_t TOVAL; /**< WDOG_TOVAL register., offset: 0x4 */ 7373 struct { /* offset: 0x4 */ 7374 __IO uint8_t TOVALH; /**< Watchdog Timeout Value Register: High, offset: 0x4 */ 7375 __IO uint8_t TOVALL; /**< Watchdog Timeout Value Register: Low, offset: 0x5 */ 7376 } TOVAL8B; 7377 }; 7378 union { /* offset: 0x6 */ 7379 __IO uint16_t WIN; /**< WDOG_WIN register., offset: 0x6 */ 7380 struct { /* offset: 0x6 */ 7381 __IO uint8_t WINH; /**< Watchdog Window Register: High, offset: 0x6 */ 7382 __IO uint8_t WINL; /**< Watchdog Window Register: Low, offset: 0x7 */ 7383 } WIN8B; 7384 }; 7385 } WDOG_Type; 7386 7387 /* ---------------------------------------------------------------------------- 7388 -- WDOG Register Masks 7389 ---------------------------------------------------------------------------- */ 7390 7391 /*! 7392 * @addtogroup WDOG_Register_Masks WDOG Register Masks 7393 * @{ 7394 */ 7395 7396 /*! @name CS1 - Watchdog Control and Status Register 1 */ 7397 /*! @{ */ 7398 #define WDOG_CS1_STOP_MASK (0x1U) 7399 #define WDOG_CS1_STOP_SHIFT (0U) 7400 /*! STOP - Stop Enable 7401 * 0b0..Watchdog disabled in chip stop mode. 7402 * 0b1..Watchdog enabled in chip stop mode. 7403 */ 7404 #define WDOG_CS1_STOP(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_STOP_SHIFT)) & WDOG_CS1_STOP_MASK) 7405 #define WDOG_CS1_WAIT_MASK (0x2U) 7406 #define WDOG_CS1_WAIT_SHIFT (1U) 7407 /*! WAIT - Wait Enable 7408 * 0b0..Watchdog disabled in chip wait mode. 7409 * 0b1..Watchdog enabled in chip wait mode. 7410 */ 7411 #define WDOG_CS1_WAIT(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_WAIT_SHIFT)) & WDOG_CS1_WAIT_MASK) 7412 #define WDOG_CS1_DBG_MASK (0x4U) 7413 #define WDOG_CS1_DBG_SHIFT (2U) 7414 /*! DBG - Debug Enable 7415 * 0b0..Watchdog disabled in chip debug mode. 7416 * 0b1..Watchdog enabled in chip debug mode. 7417 */ 7418 #define WDOG_CS1_DBG(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_DBG_SHIFT)) & WDOG_CS1_DBG_MASK) 7419 #define WDOG_CS1_TST_MASK (0x18U) 7420 #define WDOG_CS1_TST_SHIFT (3U) 7421 /*! TST - Watchdog Test 7422 * 0b00..Watchdog test mode disabled. 7423 * 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should use this setting to indicate that the watchdog is functioning normally in user mode. 7424 * 0b10..Watchdog test mode enabled, only the low byte is used. WDOG_CNTL is compared with WDOG_TOVALL. 7425 * 0b11..Watchdog test mode enabled, only the high byte is used. WDOG_CNTH is compared with WDOG_TOVALH. 7426 */ 7427 #define WDOG_CS1_TST(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_TST_SHIFT)) & WDOG_CS1_TST_MASK) 7428 #define WDOG_CS1_UPDATE_MASK (0x20U) 7429 #define WDOG_CS1_UPDATE_SHIFT (5U) 7430 /*! UPDATE - Allow updates 7431 * 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset. 7432 * 0b1..Updates allowed. Software can modify the watchdog configuration registers within 128 bus clocks after performing the unlock write sequence. 7433 */ 7434 #define WDOG_CS1_UPDATE(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_UPDATE_SHIFT)) & WDOG_CS1_UPDATE_MASK) 7435 #define WDOG_CS1_INT_MASK (0x40U) 7436 #define WDOG_CS1_INT_SHIFT (6U) 7437 /*! INT - Watchdog Interrupt 7438 * 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed. 7439 * 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 128 bus clocks. 7440 */ 7441 #define WDOG_CS1_INT(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_INT_SHIFT)) & WDOG_CS1_INT_MASK) 7442 #define WDOG_CS1_EN_MASK (0x80U) 7443 #define WDOG_CS1_EN_SHIFT (7U) 7444 /*! EN - Watchdog Enable 7445 * 0b0..Watchdog disabled. 7446 * 0b1..Watchdog enabled. 7447 */ 7448 #define WDOG_CS1_EN(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS1_EN_SHIFT)) & WDOG_CS1_EN_MASK) 7449 /*! @} */ 7450 7451 /*! @name CS2 - Watchdog Control and Status Register 2 */ 7452 /*! @{ */ 7453 #define WDOG_CS2_CLK_MASK (0x3U) 7454 #define WDOG_CS2_CLK_SHIFT (0U) 7455 /*! CLK - Watchdog Clock 7456 * 0b00..Bus clock. 7457 * 0b01..1 kHz internal low-power oscillator (LPOCLK). 7458 * 0b10..32 kHz internal oscillator (ICSIRCLK). 7459 * 0b11..External clock source. 7460 */ 7461 #define WDOG_CS2_CLK(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_CLK_SHIFT)) & WDOG_CS2_CLK_MASK) 7462 #define WDOG_CS2_PRES_MASK (0x10U) 7463 #define WDOG_CS2_PRES_SHIFT (4U) 7464 /*! PRES - Watchdog Prescalar 7465 * 0b0..256 prescalar disabled. 7466 * 0b1..256 prescalar enabled. 7467 */ 7468 #define WDOG_CS2_PRES(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_PRES_SHIFT)) & WDOG_CS2_PRES_MASK) 7469 #define WDOG_CS2_FLG_MASK (0x40U) 7470 #define WDOG_CS2_FLG_SHIFT (6U) 7471 /*! FLG - Watchdog Interrupt Flag 7472 * 0b0..No interrupt occurred. 7473 * 0b1..An interrupt occurred. 7474 */ 7475 #define WDOG_CS2_FLG(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_FLG_SHIFT)) & WDOG_CS2_FLG_MASK) 7476 #define WDOG_CS2_WIN_MASK (0x80U) 7477 #define WDOG_CS2_WIN_SHIFT (7U) 7478 /*! WIN - Watchdog Window 7479 * 0b0..Window mode disabled. 7480 * 0b1..Window mode enabled. 7481 */ 7482 #define WDOG_CS2_WIN(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CS2_WIN_SHIFT)) & WDOG_CS2_WIN_MASK) 7483 /*! @} */ 7484 7485 /*! @name CNT - WDOG_CNT register. */ 7486 /*! @{ */ 7487 #define WDOG_CNT_CNTHIGH_MASK (0xFFU) 7488 #define WDOG_CNT_CNTHIGH_SHIFT (0U) 7489 #define WDOG_CNT_CNTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_CNT_CNTHIGH_SHIFT)) & WDOG_CNT_CNTHIGH_MASK) 7490 #define WDOG_CNT_CNTLOW_MASK (0xFF00U) 7491 #define WDOG_CNT_CNTLOW_SHIFT (8U) 7492 #define WDOG_CNT_CNTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_CNT_CNTLOW_SHIFT)) & WDOG_CNT_CNTLOW_MASK) 7493 /*! @} */ 7494 7495 /*! @name CNTH - Watchdog Counter Register: High */ 7496 /*! @{ */ 7497 #define WDOG_CNTH_CNTHIGH_MASK (0xFFU) 7498 #define WDOG_CNTH_CNTHIGH_SHIFT (0U) 7499 #define WDOG_CNTH_CNTHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CNTH_CNTHIGH_SHIFT)) & WDOG_CNTH_CNTHIGH_MASK) 7500 /*! @} */ 7501 7502 /*! @name CNTL - Watchdog Counter Register: Low */ 7503 /*! @{ */ 7504 #define WDOG_CNTL_CNTLOW_MASK (0xFFU) 7505 #define WDOG_CNTL_CNTLOW_SHIFT (0U) 7506 #define WDOG_CNTL_CNTLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_CNTL_CNTLOW_SHIFT)) & WDOG_CNTL_CNTLOW_MASK) 7507 /*! @} */ 7508 7509 /*! @name TOVAL - WDOG_TOVAL register. */ 7510 /*! @{ */ 7511 #define WDOG_TOVAL_TOVALHIGH_MASK (0xFFU) 7512 #define WDOG_TOVAL_TOVALHIGH_SHIFT (0U) 7513 #define WDOG_TOVAL_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVAL_TOVALHIGH_SHIFT)) & WDOG_TOVAL_TOVALHIGH_MASK) 7514 #define WDOG_TOVAL_TOVALLOW_MASK (0xFF00U) 7515 #define WDOG_TOVAL_TOVALLOW_SHIFT (8U) 7516 #define WDOG_TOVAL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVAL_TOVALLOW_SHIFT)) & WDOG_TOVAL_TOVALLOW_MASK) 7517 /*! @} */ 7518 7519 /*! @name TOVALH - Watchdog Timeout Value Register: High */ 7520 /*! @{ */ 7521 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFU) 7522 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) 7523 #define WDOG_TOVALH_TOVALHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) 7524 /*! @} */ 7525 7526 /*! @name TOVALL - Watchdog Timeout Value Register: Low */ 7527 /*! @{ */ 7528 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFU) 7529 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) 7530 #define WDOG_TOVALL_TOVALLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) 7531 /*! @} */ 7532 7533 /*! @name WIN - WDOG_WIN register. */ 7534 /*! @{ */ 7535 #define WDOG_WIN_WINHIGH_MASK (0xFFU) 7536 #define WDOG_WIN_WINHIGH_SHIFT (0U) 7537 #define WDOG_WIN_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WIN_WINHIGH_SHIFT)) & WDOG_WIN_WINHIGH_MASK) 7538 #define WDOG_WIN_WINLOW_MASK (0xFF00U) 7539 #define WDOG_WIN_WINLOW_SHIFT (8U) 7540 #define WDOG_WIN_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WIN_WINLOW_SHIFT)) & WDOG_WIN_WINLOW_MASK) 7541 /*! @} */ 7542 7543 /*! @name WINH - Watchdog Window Register: High */ 7544 /*! @{ */ 7545 #define WDOG_WINH_WINHIGH_MASK (0xFFU) 7546 #define WDOG_WINH_WINHIGH_SHIFT (0U) 7547 #define WDOG_WINH_WINHIGH(x) (((uint8_t)(((uint8_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) 7548 /*! @} */ 7549 7550 /*! @name WINL - Watchdog Window Register: Low */ 7551 /*! @{ */ 7552 #define WDOG_WINL_WINLOW_MASK (0xFFU) 7553 #define WDOG_WINL_WINLOW_SHIFT (0U) 7554 #define WDOG_WINL_WINLOW(x) (((uint8_t)(((uint8_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) 7555 /*! @} */ 7556 7557 7558 /*! 7559 * @} 7560 */ /* end of group WDOG_Register_Masks */ 7561 7562 7563 /* WDOG - Peripheral instance base addresses */ 7564 /** Peripheral WDOG base address */ 7565 #define WDOG_BASE (0x40052000u) 7566 /** Peripheral WDOG base pointer */ 7567 #define WDOG ((WDOG_Type *)WDOG_BASE) 7568 /** Array initializer of WDOG peripheral base addresses */ 7569 #define WDOG_BASE_ADDRS { WDOG_BASE } 7570 /** Array initializer of WDOG peripheral base pointers */ 7571 #define WDOG_BASE_PTRS { WDOG } 7572 /** Interrupt vectors for the WDOG peripheral type */ 7573 #define WDOG_IRQS { WDOG_IRQn } 7574 #define WDOG_UPDATE_KEY1 (0x20C5U) 7575 #define WDOG_UPDATE_KEY_H1 (0x20U) 7576 #define WDOG_UPDATE_KEY_L1 (0xC5U) 7577 #define WDOG_UPDATE_KEY2 (0x28D9U) 7578 #define WDOG_UPDATE_KEY_H2 (0x28U) 7579 #define WDOG_UPDATE_KEY_L2 (0xD9U) 7580 #define WDOG_REFRESH_KEY1 (0x02A6U) 7581 #define WDOG_REFRESH_KEY_H1 (0x02U) 7582 #define WDOG_REFRESH_KEY_L1 (0xA6U) 7583 #define WDOG_REFRESH_KEY2 (0x80B4U) 7584 #define WDOG_REFRESH_KEY_H2 (0x80U) 7585 #define WDOG_REFRESH_KEY_L2 (0xB4U) 7586 7587 7588 /*! 7589 * @} 7590 */ /* end of group WDOG_Peripheral_Access_Layer */ 7591 7592 7593 /* 7594 ** End of section using anonymous unions 7595 */ 7596 7597 #if defined(__ARMCC_VERSION) 7598 #if (__ARMCC_VERSION >= 6010050) 7599 #pragma clang diagnostic pop 7600 #else 7601 #pragma pop 7602 #endif 7603 #elif defined(__CWCC__) 7604 #pragma pop 7605 #elif defined(__GNUC__) 7606 /* leave anonymous unions enabled */ 7607 #elif defined(__IAR_SYSTEMS_ICC__) 7608 #pragma language=default 7609 #else 7610 #error Not supported compiler type 7611 #endif 7612 7613 /*! 7614 * @} 7615 */ /* end of group Peripheral_access_layer */ 7616 7617 7618 /* ---------------------------------------------------------------------------- 7619 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 7620 ---------------------------------------------------------------------------- */ 7621 7622 /*! 7623 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 7624 * @{ 7625 */ 7626 7627 #if defined(__ARMCC_VERSION) 7628 #if (__ARMCC_VERSION >= 6010050) 7629 #pragma clang system_header 7630 #endif 7631 #elif defined(__IAR_SYSTEMS_ICC__) 7632 #pragma system_include 7633 #endif 7634 7635 /** 7636 * @brief Mask and left-shift a bit field value for use in a register bit range. 7637 * @param field Name of the register bit field. 7638 * @param value Value of the bit field. 7639 * @return Masked and shifted value. 7640 */ 7641 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 7642 /** 7643 * @brief Mask and right-shift a register value to extract a bit field value. 7644 * @param field Name of the register bit field. 7645 * @param value Value of the register. 7646 * @return Masked and shifted bit field value. 7647 */ 7648 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 7649 7650 /*! 7651 * @} 7652 */ /* end of group Bit_Field_Generic_Macros */ 7653 7654 7655 /* ---------------------------------------------------------------------------- 7656 -- SDK Compatibility 7657 ---------------------------------------------------------------------------- */ 7658 7659 /*! 7660 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 7661 * @{ 7662 */ 7663 7664 /* No SDK compatibility issues. */ 7665 7666 /*! 7667 * @} 7668 */ /* end of group SDK_Compatibility_Symbols */ 7669 7670 7671 #endif /* _MKE06Z4_H_ */ 7672 7673
