1 /*! 2 \file gd32e50x.h 3 \brief general definitions for GD32E50x 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_H 38 #define GD32E50X_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 /* define GD32E50X */ 45 #if !defined (GD32EPRT) && !defined (GD32E50X_HD) && !defined (GD32E50X_XD) && !defined (GD32E50X_CL) && !defined (GD32E508) 46 #error "Please select chip type in project configuration" 47 /* #define GD32EPRT */ 48 /* #define GD32E50X_HD */ 49 /* #define GD32E50X_XD */ 50 /* #define GD32E50X_CL */ 51 /* #define GD32E508 */ 52 #endif /* define GD32E50X */ 53 54 #if !defined (GD32E50X) 55 #error "Please select the target GD32E50x device used in your application (in gd32e50x.h file)" 56 #endif /* undefine GD32E50X tip */ 57 58 /* define value of high speed crystal oscillator (HXTAL) in Hz */ 59 #if !defined HXTAL_VALUE 60 #if defined (GD32E50X_CL) || defined (GD32E508) 61 #define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */ 62 #else 63 #define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 32M *!< value of the external oscillator in Hz*/ 64 #endif /* HXTAL_VALUE */ 65 #endif /* high speed crystal oscillator value */ 66 67 /* define startup timeout value of high speed crystal oscillator (HXTAL) */ 68 #if !defined (HXTAL_STARTUP_TIMEOUT) 69 #define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF) 70 #endif /* high speed crystal oscillator startup timeout */ 71 72 /* define value of internal 8MHz RC oscillator (IRC8M) in Hz */ 73 #if !defined (IRC8M_VALUE) 74 #define IRC8M_VALUE ((uint32_t)8000000) 75 #endif /* internal 8MHz RC oscillator value */ 76 77 /* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */ 78 #if !defined (IRC8M_STARTUP_TIMEOUT) 79 #define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500) 80 #endif /* internal 8MHz RC oscillator startup timeout */ 81 82 /* define value of internal 48MHz RC oscillator (IRC48M) in Hz */ 83 #if !defined (IRC48M_VALUE) 84 #define IRC48M_VALUE ((uint32_t)48000000) 85 #endif /* internal 48MHz RC oscillator value */ 86 87 /* define value of internal 40KHz RC oscillator(IRC40K) in Hz */ 88 #if !defined (IRC40K_VALUE) 89 #define IRC40K_VALUE ((uint32_t)40000) 90 #endif /* internal 40KHz RC oscillator value */ 91 92 /* define value of low speed crystal oscillator (LXTAL)in Hz */ 93 #if !defined (LXTAL_VALUE) 94 #define LXTAL_VALUE ((uint32_t)32768) 95 #endif /* low speed crystal oscillator value */ 96 97 /* GD32E50x firmware library version number V1.0 */ 98 #define __GD32E50X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ 99 #define __GD32E50X_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */ 100 #define __GD32E50X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ 101 #define __GD32E50X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */ 102 #define __GD32E50X_STDPERIPH_VERSION ((__GD32E50X_STDPERIPH_VERSION_MAIN << 24)\ 103 |(__GD32E50X_STDPERIPH_VERSION_SUB1 << 16)\ 104 |(__GD32E50X_STDPERIPH_VERSION_SUB2 << 8)\ 105 |(__GD32E50X_STDPERIPH_VERSION_RC)) 106 107 /* configuration of the Cortex-M33 processor and core peripherals */ 108 #define __CM33_REV 0x0003U /*!< Core revision r0p3 */ 109 #define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */ 110 #define __MPU_PRESENT 1U /*!< MPU is present */ 111 #define __VTOR_PRESENT 1U /*!< VTOR is present */ 112 #define __NVIC_PRIO_BITS 4U /*!< Number of Bits used for Priority Levels */ 113 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ 114 #define __FPU_PRESENT 1 /*!< FPU present */ 115 #define __DSP_PRESENT 1 /*!< DSP present */ 116 117 /* define interrupt number */ 118 typedef enum IRQn 119 { 120 /* Cortex-M33 processor exceptions numbers */ 121 NonMaskableInt_IRQn = -14, /*!< non mask-able interrupt */ 122 HardFault_IRQn = -13, /*!< hard-fault interrupt */ 123 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M33 memory management interrupt */ 124 BusFault_IRQn = -11, /*!< 5 Cortex-M33 bus fault interrupt */ 125 UsageFault_IRQn = -10, /*!< 6 Cortex-M33 usage fault interrupt */ 126 SVCall_IRQn = -5, /*!< 11 Cortex-M33 sv call interrupt */ 127 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M33 debug monitor interrupt */ 128 PendSV_IRQn = -2, /*!< 14 Cortex-M33 pend sv interrupt */ 129 SysTick_IRQn = -1, /*!< 15 Cortex-M33 system tick interrupt */ 130 /* interrupt numbers */ 131 WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */ 132 LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */ 133 TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */ 134 RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */ 135 FMC_IRQn = 4, /*!< FMC interrupt */ 136 RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */ 137 EXTI0_IRQn = 6, /*!< EXTI line 0 interrupt */ 138 EXTI1_IRQn = 7, /*!< EXTI line 1 interrupt */ 139 EXTI2_IRQn = 8, /*!< EXTI line 2 interrupt */ 140 EXTI3_IRQn = 9, /*!< EXTI line 3 interrupt */ 141 EXTI4_IRQn = 10, /*!< EXTI line 4 interrupt */ 142 DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */ 143 DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */ 144 DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */ 145 DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */ 146 DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */ 147 DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */ 148 DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */ 149 ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */ 150 151 #ifdef GD32EPRT 152 USBD_HP_IRQn = 19, /*!< USBD High Priority interrupts */ 153 USBD_LP_IRQn = 20, /*!< USBD Low Priority interrupts */ 154 EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ 155 TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */ 156 TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */ 157 TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt */ 158 TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ 159 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 160 TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ 161 TIMER3_IRQn = 30, /*!< TIMER3 interrupt */ 162 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 163 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 164 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 165 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 166 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 167 SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */ 168 USART0_IRQn = 37, /*!< USART0 interrupt */ 169 USART1_IRQn = 38, /*!< USART1 interrupt */ 170 USART2_IRQn = 39, /*!< USART2 interrupt */ 171 EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ 172 RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ 173 USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ 174 TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupt */ 175 TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupt */ 176 TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt */ 177 TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ 178 ADC2_IRQn = 47, /*!< ADC2 global interrupt */ 179 EXMC_IRQn = 48, /*!< EXMC global interrupt */ 180 TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ 181 SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */ 182 UART3_IRQn = 52, /*!< UART3 global interrupt */ 183 UART4_IRQn = 53, /*!< UART4 global interrupt */ 184 TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */ 185 TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ 186 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ 187 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ 188 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ 189 DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ 190 ENET_IRQn = 61, /*!< ENET global interrupt */ 191 ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ 192 I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */ 193 I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */ 194 USART5_IRQn = 84, /*!< USART5 interrupt */ 195 I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */ 196 USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */ 197 #endif /* GD32EPRT */ 198 199 #ifdef GD32E50X_HD 200 USBD_HP_CAN0_TX_IRQn = 19, /*!< USBD High Priority or CAN0 TX interrupts */ 201 USBD_LP_CAN0_RX0_IRQn = 20, /*!< USBD Low Priority or CAN0 RX0 interrupts */ 202 CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ 203 CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ 204 EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ 205 TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */ 206 TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */ 207 TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt */ 208 TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ 209 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 210 TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ 211 TIMER3_IRQn = 30, /*!< TIMER3 interrupt */ 212 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 213 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 214 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 215 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 216 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 217 SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */ 218 USART0_IRQn = 37, /*!< USART0 interrupt */ 219 USART1_IRQn = 38, /*!< USART1 interrupt */ 220 USART2_IRQn = 39, /*!< USART2 interrupt */ 221 EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ 222 RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ 223 USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */ 224 TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupt */ 225 TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupt */ 226 TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt */ 227 TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ 228 ADC2_IRQn = 47, /*!< ADC2 global interrupt */ 229 EXMC_IRQn = 48, /*!< EXMC global interrupt */ 230 SDIO_IRQn = 49, /*!< SDIO global interrupt */ 231 TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ 232 SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */ 233 UART3_IRQn = 52, /*!< UART3 global interrupt */ 234 UART4_IRQn = 53, /*!< UART4 global interrupt */ 235 TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */ 236 TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ 237 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ 238 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ 239 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ 240 DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */ 241 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 242 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 243 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 244 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 245 SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */ 246 SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */ 247 SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */ 248 SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */ 249 SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */ 250 SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */ 251 SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */ 252 I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */ 253 I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */ 254 USART5_IRQn = 84, /*!< USART5 interrupt */ 255 I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */ 256 USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */ 257 #endif /* GD32E50X_HD */ 258 259 #ifdef GD32E50X_XD 260 USBD_HP_CAN0_TX_IRQn = 19, /*!< USBD High Priority or CAN0 TX interrupts */ 261 USBD_LP_CAN0_RX0_IRQn = 20, /*!< USBD Low Priority or CAN0 RX0 interrupts */ 262 CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ 263 CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ 264 EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ 265 TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */ 266 TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */ 267 TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */ 268 TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ 269 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 270 TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ 271 TIMER3_IRQn = 30, /*!< TIMER3 interrupt */ 272 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 273 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 274 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 275 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 276 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 277 SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */ 278 USART0_IRQn = 37, /*!< USART0 interrupt */ 279 USART1_IRQn = 38, /*!< USART1 interrupt */ 280 USART2_IRQn = 39, /*!< USART2 interrupt */ 281 EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ 282 RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ 283 USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */ 284 TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */ 285 TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */ 286 TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */ 287 TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ 288 ADC2_IRQn = 47, /*!< ADC2 global interrupt */ 289 EXMC_IRQn = 48, /*!< EXMC global interrupt */ 290 SDIO_IRQn = 49, /*!< SDIO global interrupt */ 291 TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ 292 SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */ 293 UART3_IRQn = 52, /*!< UART3 global interrupt */ 294 UART4_IRQn = 53, /*!< UART4 global interrupt */ 295 TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */ 296 TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ 297 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ 298 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ 299 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ 300 DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */ 301 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 302 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 303 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 304 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 305 SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */ 306 SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */ 307 SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */ 308 SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */ 309 SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */ 310 SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */ 311 SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */ 312 I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */ 313 I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */ 314 USART5_IRQn = 84, /*!< USART5 interrupt */ 315 I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */ 316 USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */ 317 #endif /* GD32E50X_XD */ 318 319 #ifdef GD32E50X_CL 320 CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ 321 CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ 322 CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ 323 CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ 324 EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ 325 TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */ 326 TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */ 327 TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */ 328 TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ 329 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 330 TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ 331 TIMER3_IRQn = 30, /*!< TIMER3 interrupt */ 332 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 333 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 334 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 335 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 336 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 337 SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */ 338 USART0_IRQn = 37, /*!< USART0 interrupt */ 339 USART1_IRQn = 38, /*!< USART1 interrupt */ 340 USART2_IRQn = 39, /*!< USART2 interrupt */ 341 EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ 342 RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ 343 USBHS_WKUP_IRQn = 42, /*!< USBHS wakeup interrupt */ 344 TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */ 345 TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */ 346 TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */ 347 TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ 348 EXMC_IRQn = 48, /*!< EXMC global interrupt */ 349 TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ 350 SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */ 351 UART3_IRQn = 52, /*!< UART3 global interrupt */ 352 UART4_IRQn = 53, /*!< UART4 global interrupt */ 353 TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */ 354 TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ 355 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ 356 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ 357 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ 358 DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ 359 DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ 360 ENET_IRQn = 61, /*!< ENET global interrupt */ 361 ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ 362 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 363 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 364 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 365 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 366 USBHS_IRQn = 67, /*!< USBHS global interrupt */ 367 SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */ 368 SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */ 369 SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */ 370 SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */ 371 SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */ 372 USBHS_EP1_OUT_IRQn = 74, /*!< USBHS end point 1 out interrupt */ 373 USBHS_EP1_IN_IRQn = 75, /*!< USBHS end point 1 in interrupt */ 374 SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */ 375 SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */ 376 CAN2_TX_IRQn = 78, /*!< CAN2 TX interrupt */ 377 CAN2_RX0_IRQn = 79, /*!< CAN2 RX0 interrupt */ 378 CAN2_RX1_IRQn = 80, /*!< CAN2 RX1 interrupt */ 379 CAN2_EWMC_IRQn = 81, /*!< CAN2 EWMC interrupt */ 380 I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */ 381 I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */ 382 USART5_IRQn = 84, /*!< USART5 global interrupt */ 383 I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */ 384 USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */ 385 TMU_IRQn = 87, /*!< TMU interrupt */ 386 #endif /* GD32E50X_CL */ 387 388 #ifdef GD32E508 389 CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */ 390 CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */ 391 CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */ 392 CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */ 393 EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */ 394 TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */ 395 TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */ 396 TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */ 397 TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */ 398 TIMER1_IRQn = 28, /*!< TIMER1 interrupt */ 399 TIMER2_IRQn = 29, /*!< TIMER2 interrupt */ 400 TIMER3_IRQn = 30, /*!< TIMER3 interrupt */ 401 I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */ 402 I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */ 403 I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */ 404 I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */ 405 SPI0_IRQn = 35, /*!< SPI0 interrupt */ 406 SPI1_I2S1ADD_IRQn = 36, /*!< SPI1 or I2S1ADD interrupt */ 407 USART0_IRQn = 37, /*!< USART0 interrupt */ 408 USART1_IRQn = 38, /*!< USART1 interrupt */ 409 USART2_IRQn = 39, /*!< USART2 interrupt */ 410 EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */ 411 RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */ 412 USBHS_WKUP_IRQn = 42, /*!< USBHS wakeup interrupt */ 413 TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */ 414 TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */ 415 TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */ 416 TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */ 417 EXMC_IRQn = 48, /*!< EXMC global interrupt */ 418 TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */ 419 SPI2_I2S2ADD_IRQn = 51, /*!< SPI2 or I2S2ADD global interrupt */ 420 UART3_IRQn = 52, /*!< UART3 global interrupt */ 421 UART4_IRQn = 53, /*!< UART4 global interrupt */ 422 TIMER5_DAC_IRQn = 54, /*!< TIMER5 or DAC global interrupt */ 423 TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */ 424 DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */ 425 DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */ 426 DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */ 427 DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */ 428 DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */ 429 ENET_IRQn = 61, /*!< ENET global interrupt */ 430 ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */ 431 CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */ 432 CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */ 433 CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */ 434 CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */ 435 USBHS_IRQn = 67, /*!< USBHS global interrupt */ 436 SHRTIMER_IRQ2_IRQn = 69, /*!< SHRTIMER_IRQ2 interrupt */ 437 SHRTIMER_IRQ3_IRQn = 70, /*!< SHRTIMER_IRQ3 interrupt */ 438 SHRTIMER_IRQ4_IRQn = 71, /*!< SHRTIMER_IRQ4 interrupt */ 439 SHRTIMER_IRQ5_IRQn = 72, /*!< SHRTIMER_IRQ5 interrupt */ 440 SHRTIMER_IRQ6_IRQn = 73, /*!< SHRTIMER_IRQ6 interrupt */ 441 USBHS_EP1_OUT_IRQn = 74, /*!< USBHS end point 1 out interrupt */ 442 USBHS_EP1_IN_IRQn = 75, /*!< USBHS end point 1 in interrupt */ 443 SHRTIMER_IRQ0_IRQn = 76, /*!< SHRTIMER_IRQ0 interrupt */ 444 SHRTIMER_IRQ1_IRQn = 77, /*!< SHRTIMER_IRQ1 interrupt */ 445 CAN2_TX_IRQn = 78, /*!< CAN2 TX interrupt */ 446 CAN2_RX0_IRQn = 79, /*!< CAN2 RX0 interrupt */ 447 CAN2_RX1_IRQn = 80, /*!< CAN2 RX1 interrupt */ 448 CAN2_EWMC_IRQn = 81, /*!< CAN2 EWMC interrupt */ 449 I2C2_EV_IRQn = 82, /*!< I2C2 EV interrupt */ 450 I2C2_ER_IRQn = 83, /*!< I2C2 ER interrupt */ 451 USART5_IRQn = 84, /*!< USART5 global interrupt */ 452 I2C2_WKUP_IRQn = 85, /*!< I2C2 Wakeup interrupt */ 453 USART5_WKUP_IRQn = 86, /*!< USART5 Wakeup interrupt */ 454 TMU_IRQn = 87, /*!< TMU interrupt */ 455 #endif /* GD32E508 */ 456 } IRQn_Type; 457 458 /* includes */ 459 #include "core_cm33.h" 460 #include "system_gd32e50x.h" 461 #include <stdint.h> 462 463 /* enum definitions */ 464 typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus; 465 typedef enum {RESET = 0, SET = !RESET} FlagStatus; 466 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus; 467 468 /* bit operations */ 469 #define REG64(addr) (*(volatile uint64_t *)(uint32_t)(addr)) 470 #define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr)) 471 #define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr)) 472 #define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr)) 473 #ifndef BIT 474 #define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x))) 475 #endif 476 #define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end)))) 477 #define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start)) 478 479 /* main flash and SRAM memory map */ 480 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */ 481 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */ 482 483 /* peripheral memory map */ 484 #define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */ 485 #define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */ 486 #define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */ 487 #define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */ 488 489 /* advanced peripheral bus 1 memory map */ 490 #define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */ 491 #define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */ 492 #define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */ 493 #define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */ 494 #define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S_add base address */ 495 #define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */ 496 #define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */ 497 #define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */ 498 #define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */ 499 #define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */ 500 #define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */ 501 #define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */ 502 #define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */ 503 #define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */ 504 #define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */ 505 506 /* advanced peripheral bus 2 memory map */ 507 #define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */ 508 #define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */ 509 #define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */ 510 #define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */ 511 #define SHRTIMER_BASE (APB2_BUS_BASE + 0x00007400U) /*!< SHRTIMER base address */ 512 #define CMP_BASE (APB2_BUS_BASE + 0x00007C00U) /*!< CMP base address */ 513 514 /* advanced high performance bus 1 memory map */ 515 #define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */ 516 #define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */ 517 #define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */ 518 #define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */ 519 #define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */ 520 #define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */ 521 #define TMU_BASE (AHB1_BUS_BASE + 0x00068000U) /*!< TMU base address */ 522 #define USBHS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBHS base address */ 523 524 /* advanced high performance bus 3 memory map */ 525 #define EXMC_BASE (AHB3_BUS_BASE + 0x40000000U) /*!< EXMC base address */ 526 527 /* option byte and debug memory map */ 528 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */ 529 #define DBG_BASE ((uint32_t)0xE0044000U) /*!< DBG base address */ 530 #define SQPI_BASE ((uint32_t)0xA0001000U) /*!< SQPI base address */ 531 #include "gd32e50x_libopt.h" 532 533 #ifdef __cplusplus 534 } 535 #endif 536 537 #endif /* GD32E50X_H */ 538
