1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef __HWCRYPTO_REG_H__
15 #define __HWCRYPTO_REG_H__
16 
17 #include "soc.h"
18 
19 /* registers for RSA acceleration via Multiple Precision Integer ops */
20 #define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
21 /* RB & Z use the same memory block, depending on phase of operation */
22 #define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
23 #define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
24 #define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
25 #define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
26 
27 #define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
28 #define RSA_MODEXP_MODE_REG           (DR_REG_RSA_BASE + 0x804)
29 #define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x808)
30 #define RSA_MULT_MODE_REG             (DR_REG_RSA_BASE + 0x80c)
31 #define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x810)
32 
33 #define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x814)
34 #define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x814) /* same */
35 
36 #define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x818)
37 
38 /* Backwards compatibility register names used pre-ESP32S2 */
39 #define RSA_CLEAN_REG                 (RSA_QUERY_CLEAN_REG)
40 #define RSA_INTERRUPT_REG             (RSA_CLEAR_INTERRUPT_REG)
41 #define RSA_START_MODEXP_REG          (RSA_MODEXP_START_REG)
42 
43 /* SHA acceleration registers */
44 #define SHA_TEXT_BASE           ((DR_REG_SHA_BASE) + 0x00)
45 
46 #define SHA_1_START_REG         ((DR_REG_SHA_BASE) + 0x80)
47 #define SHA_1_CONTINUE_REG      ((DR_REG_SHA_BASE) + 0x84)
48 #define SHA_1_LOAD_REG          ((DR_REG_SHA_BASE) + 0x88)
49 #define SHA_1_BUSY_REG          ((DR_REG_SHA_BASE) + 0x8c)
50 
51 #define SHA_256_START_REG       ((DR_REG_SHA_BASE) + 0x90)
52 #define SHA_256_CONTINUE_REG    ((DR_REG_SHA_BASE) + 0x94)
53 #define SHA_256_LOAD_REG        ((DR_REG_SHA_BASE) + 0x98)
54 #define SHA_256_BUSY_REG        ((DR_REG_SHA_BASE) + 0x9c)
55 
56 #define SHA_384_START_REG       ((DR_REG_SHA_BASE) + 0xa0)
57 #define SHA_384_CONTINUE_REG    ((DR_REG_SHA_BASE) + 0xa4)
58 #define SHA_384_LOAD_REG        ((DR_REG_SHA_BASE) + 0xa8)
59 #define SHA_384_BUSY_REG        ((DR_REG_SHA_BASE) + 0xac)
60 
61 #define SHA_512_START_REG       ((DR_REG_SHA_BASE) + 0xb0)
62 #define SHA_512_CONTINUE_REG    ((DR_REG_SHA_BASE) + 0xb4)
63 #define SHA_512_LOAD_REG        ((DR_REG_SHA_BASE) + 0xb8)
64 #define SHA_512_BUSY_REG        ((DR_REG_SHA_BASE) + 0xbc)
65 
66 /* AES acceleration registers */
67 #define AES_START_REG           ((DR_REG_AES_BASE) + 0x00)
68 #define AES_IDLE_REG            ((DR_REG_AES_BASE) + 0x04)
69 #define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x08)
70 #define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x10)
71 #define AES_TEXT_BASE           ((DR_REG_AES_BASE) + 0x30)
72 #define AES_ENDIAN              ((DR_REG_AES_BASE) + 0x40)
73 
74 #endif
75