1 // THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT 2 3 /** 4 * Copyright (c) 2024 Raspberry Pi Ltd. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 // ============================================================================= 9 // Register block : SHA256 10 // Version : 1 11 // Bus type : apb 12 // Description : SHA-256 hash function implementation 13 // ============================================================================= 14 #ifndef _HARDWARE_REGS_SHA256_H 15 #define _HARDWARE_REGS_SHA256_H 16 // ============================================================================= 17 // Register : SHA256_CSR 18 // Description : Control and status register 19 #define SHA256_CSR_OFFSET _u(0x00000000) 20 #define SHA256_CSR_BITS _u(0x00001317) 21 #define SHA256_CSR_RESET _u(0x00001206) 22 // ----------------------------------------------------------------------------- 23 // Field : SHA256_CSR_BSWAP 24 // Description : Enable byte swapping of 32-bit values at the point they are 25 // committed to the SHA message scheduler. 26 // 27 // This block's bus interface assembles byte/halfword data into 28 // message words in little-endian order, so that DMAing the same 29 // buffer with different transfer sizes always gives the same 30 // result on a little-endian system like RP2350. 31 // 32 // However, when marshalling bytes into blocks, SHA expects that 33 // the first byte is the *most significant* in each message word. 34 // To resolve this, once the bus interface has accumulated 32 bits 35 // of data (either a word write, two halfword writes in little- 36 // endian order, or four byte writes in little-endian order) the 37 // final value can be byte-swapped before passing to the actual 38 // SHA core. 39 // 40 // This feature is enabled by default because using the SHA core 41 // to checksum byte buffers is expected to be more common than 42 // having preformatted SHA message words lying around. 43 #define SHA256_CSR_BSWAP_RESET _u(0x1) 44 #define SHA256_CSR_BSWAP_BITS _u(0x00001000) 45 #define SHA256_CSR_BSWAP_MSB _u(12) 46 #define SHA256_CSR_BSWAP_LSB _u(12) 47 #define SHA256_CSR_BSWAP_ACCESS "RW" 48 // ----------------------------------------------------------------------------- 49 // Field : SHA256_CSR_DMA_SIZE 50 // Description : Configure DREQ logic for the correct DMA data size. Must be 51 // configured before the DMA channel is triggered. 52 // 53 // The SHA-256 core's DREQ logic requests one entire block of data 54 // at once, since there is no FIFO, and data goes straight into 55 // the core's message schedule and digest hardware. Therefore, 56 // when transferring data with DMA, CSR_DMA_SIZE must be 57 // configured in advance so that the correct number of transfers 58 // can be requested per block. 59 // 0x0 -> 8bit 60 // 0x1 -> 16bit 61 // 0x2 -> 32bit 62 #define SHA256_CSR_DMA_SIZE_RESET _u(0x2) 63 #define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300) 64 #define SHA256_CSR_DMA_SIZE_MSB _u(9) 65 #define SHA256_CSR_DMA_SIZE_LSB _u(8) 66 #define SHA256_CSR_DMA_SIZE_ACCESS "RW" 67 #define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0) 68 #define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1) 69 #define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2) 70 // ----------------------------------------------------------------------------- 71 // Field : SHA256_CSR_ERR_WDATA_NOT_RDY 72 // Description : Set when a write occurs whilst the SHA-256 core is not ready 73 // for data (WDATA_RDY is low). Write one to clear. 74 #define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0) 75 #define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010) 76 #define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4) 77 #define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4) 78 #define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC" 79 // ----------------------------------------------------------------------------- 80 // Field : SHA256_CSR_SUM_VLD 81 // Description : If 1, the SHA-256 checksum presented in registers SUM0 through 82 // SUM7 is currently valid. 83 // 84 // Goes low when WDATA is first written, then returns high once 16 85 // words have been written and the digest of the current 512-bit 86 // block has subsequently completed. 87 #define SHA256_CSR_SUM_VLD_RESET _u(0x1) 88 #define SHA256_CSR_SUM_VLD_BITS _u(0x00000004) 89 #define SHA256_CSR_SUM_VLD_MSB _u(2) 90 #define SHA256_CSR_SUM_VLD_LSB _u(2) 91 #define SHA256_CSR_SUM_VLD_ACCESS "RO" 92 // ----------------------------------------------------------------------------- 93 // Field : SHA256_CSR_WDATA_RDY 94 // Description : If 1, the SHA-256 core is ready to accept more data through the 95 // WDATA register. 96 // 97 // After writing 16 words, this flag will go low for 57 cycles 98 // whilst the core completes its digest. 99 #define SHA256_CSR_WDATA_RDY_RESET _u(0x1) 100 #define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002) 101 #define SHA256_CSR_WDATA_RDY_MSB _u(1) 102 #define SHA256_CSR_WDATA_RDY_LSB _u(1) 103 #define SHA256_CSR_WDATA_RDY_ACCESS "RO" 104 // ----------------------------------------------------------------------------- 105 // Field : SHA256_CSR_START 106 // Description : Write 1 to prepare the SHA-256 core for a new checksum. 107 // 108 // The SUMx registers are initialised to the proper values 109 // (fractional bits of square roots of first 8 primes) and 110 // internal counters are cleared. This immediately forces 111 // WDATA_RDY and SUM_VLD high. 112 // 113 // START must be written before initiating a DMA transfer to the 114 // SHA-256 core, because the core will always request 16 transfers 115 // at a time (1 512-bit block). Additionally, the DMA channel 116 // should be configured for a multiple of 16 32-bit transfers. 117 #define SHA256_CSR_START_RESET _u(0x0) 118 #define SHA256_CSR_START_BITS _u(0x00000001) 119 #define SHA256_CSR_START_MSB _u(0) 120 #define SHA256_CSR_START_LSB _u(0) 121 #define SHA256_CSR_START_ACCESS "SC" 122 // ============================================================================= 123 // Register : SHA256_WDATA 124 // Description : Write data register 125 // After pulsing START and writing 16 words of data to this 126 // register, WDATA_RDY will go low and the SHA-256 core will 127 // complete the digest of the current 512-bit block. 128 // 129 // Software is responsible for ensuring the data is correctly 130 // padded and terminated to a whole number of 512-bit blocks. 131 // 132 // After this, WDATA_RDY will return high, and more data can be 133 // written (if any). 134 // 135 // This register supports word, halfword and byte writes, so that 136 // DMA from non-word-aligned buffers can be supported. The total 137 // amount of data per block remains the same (16 words, 32 138 // halfwords or 64 bytes) and byte/halfword transfers must not be 139 // mixed within a block. 140 #define SHA256_WDATA_OFFSET _u(0x00000004) 141 #define SHA256_WDATA_BITS _u(0xffffffff) 142 #define SHA256_WDATA_RESET _u(0x00000000) 143 #define SHA256_WDATA_MSB _u(31) 144 #define SHA256_WDATA_LSB _u(0) 145 #define SHA256_WDATA_ACCESS "WF" 146 // ============================================================================= 147 // Register : SHA256_SUM0 148 // Description : 256-bit checksum result. Contents are undefined when 149 // CSR_SUM_VLD is 0. 150 #define SHA256_SUM0_OFFSET _u(0x00000008) 151 #define SHA256_SUM0_BITS _u(0xffffffff) 152 #define SHA256_SUM0_RESET _u(0x00000000) 153 #define SHA256_SUM0_MSB _u(31) 154 #define SHA256_SUM0_LSB _u(0) 155 #define SHA256_SUM0_ACCESS "RO" 156 // ============================================================================= 157 // Register : SHA256_SUM1 158 // Description : 256-bit checksum result. Contents are undefined when 159 // CSR_SUM_VLD is 0. 160 #define SHA256_SUM1_OFFSET _u(0x0000000c) 161 #define SHA256_SUM1_BITS _u(0xffffffff) 162 #define SHA256_SUM1_RESET _u(0x00000000) 163 #define SHA256_SUM1_MSB _u(31) 164 #define SHA256_SUM1_LSB _u(0) 165 #define SHA256_SUM1_ACCESS "RO" 166 // ============================================================================= 167 // Register : SHA256_SUM2 168 // Description : 256-bit checksum result. Contents are undefined when 169 // CSR_SUM_VLD is 0. 170 #define SHA256_SUM2_OFFSET _u(0x00000010) 171 #define SHA256_SUM2_BITS _u(0xffffffff) 172 #define SHA256_SUM2_RESET _u(0x00000000) 173 #define SHA256_SUM2_MSB _u(31) 174 #define SHA256_SUM2_LSB _u(0) 175 #define SHA256_SUM2_ACCESS "RO" 176 // ============================================================================= 177 // Register : SHA256_SUM3 178 // Description : 256-bit checksum result. Contents are undefined when 179 // CSR_SUM_VLD is 0. 180 #define SHA256_SUM3_OFFSET _u(0x00000014) 181 #define SHA256_SUM3_BITS _u(0xffffffff) 182 #define SHA256_SUM3_RESET _u(0x00000000) 183 #define SHA256_SUM3_MSB _u(31) 184 #define SHA256_SUM3_LSB _u(0) 185 #define SHA256_SUM3_ACCESS "RO" 186 // ============================================================================= 187 // Register : SHA256_SUM4 188 // Description : 256-bit checksum result. Contents are undefined when 189 // CSR_SUM_VLD is 0. 190 #define SHA256_SUM4_OFFSET _u(0x00000018) 191 #define SHA256_SUM4_BITS _u(0xffffffff) 192 #define SHA256_SUM4_RESET _u(0x00000000) 193 #define SHA256_SUM4_MSB _u(31) 194 #define SHA256_SUM4_LSB _u(0) 195 #define SHA256_SUM4_ACCESS "RO" 196 // ============================================================================= 197 // Register : SHA256_SUM5 198 // Description : 256-bit checksum result. Contents are undefined when 199 // CSR_SUM_VLD is 0. 200 #define SHA256_SUM5_OFFSET _u(0x0000001c) 201 #define SHA256_SUM5_BITS _u(0xffffffff) 202 #define SHA256_SUM5_RESET _u(0x00000000) 203 #define SHA256_SUM5_MSB _u(31) 204 #define SHA256_SUM5_LSB _u(0) 205 #define SHA256_SUM5_ACCESS "RO" 206 // ============================================================================= 207 // Register : SHA256_SUM6 208 // Description : 256-bit checksum result. Contents are undefined when 209 // CSR_SUM_VLD is 0. 210 #define SHA256_SUM6_OFFSET _u(0x00000020) 211 #define SHA256_SUM6_BITS _u(0xffffffff) 212 #define SHA256_SUM6_RESET _u(0x00000000) 213 #define SHA256_SUM6_MSB _u(31) 214 #define SHA256_SUM6_LSB _u(0) 215 #define SHA256_SUM6_ACCESS "RO" 216 // ============================================================================= 217 // Register : SHA256_SUM7 218 // Description : 256-bit checksum result. Contents are undefined when 219 // CSR_SUM_VLD is 0. 220 #define SHA256_SUM7_OFFSET _u(0x00000024) 221 #define SHA256_SUM7_BITS _u(0xffffffff) 222 #define SHA256_SUM7_RESET _u(0x00000000) 223 #define SHA256_SUM7_MSB _u(31) 224 #define SHA256_SUM7_LSB _u(0) 225 #define SHA256_SUM7_ACCESS "RO" 226 // ============================================================================= 227 #endif // _HARDWARE_REGS_SHA256_H 228 229
