1  /*
2   * Copyright (c) 2015, Freescale Semiconductor, Inc.
3   * Copyright 2016-2019 NXP
4   * All rights reserved.
5   *
6   * SPDX-License-Identifier: BSD-3-Clause
7   */
8  
9  #ifndef _FSL_SGTL5000_H_
10  #define _FSL_SGTL5000_H_
11  
12  #include "fsl_codec_i2c.h"
13  
14  /*!
15   * @addtogroup sgtl5000
16   * @ingroup codec
17   * @{
18   */
19  
20  /*******************************************************************************
21   * Definitions
22   ******************************************************************************/
23  /*! @name Driver version */
24  /*@{*/
25  /*! @brief CLOCK driver version 2.1.1. */
26  #define FSL_SGTL5000_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
27  /*@}*/
28  
29  /*! @brief Define the register address of sgtl5000. */
30  #define CHIP_ID                            0x0000U
31  #define CHIP_DIG_POWER                     0x0002U
32  #define CHIP_CLK_CTRL                      0x0004U
33  #define CHIP_I2S_CTRL                      0x0006U
34  #define CHIP_SSS_CTRL                      0x000AU
35  #define CHIP_ADCDAC_CTRL                   0x000EU
36  #define CHIP_DAC_VOL                       0x0010U
37  #define CHIP_PAD_STRENGTH                  0x0014U
38  #define CHIP_ANA_ADC_CTRL                  0x0020U
39  #define CHIP_ANA_HP_CTRL                   0x0022U
40  #define CHIP_ANA_CTRL                      0x0024U
41  #define CHIP_LINREG_CTRL                   0x0026U
42  #define CHIP_REF_CTRL                      0x0028U
43  #define CHIP_MIC_CTRL                      0x002AU
44  #define CHIP_LINE_OUT_CTRL                 0x002CU
45  #define CHIP_LINE_OUT_VOL                  0x002EU
46  #define CHIP_ANA_POWER                     0x0030U
47  #define CHIP_PLL_CTRL                      0x0032U
48  #define CHIP_CLK_TOP_CTRL                  0x0034U
49  #define CHIP_ANA_STATUS                    0x0036U
50  #define CHIP_ANA_TEST2                     0x003AU
51  #define CHIP_SHORT_CTRL                    0x003CU
52  #define SGTL5000_DAP_CONTROL               0x0100U
53  #define SGTL5000_DAP_PEQ                   0x0102U
54  #define SGTL5000_DAP_BASS_ENHANCE          0x0104U
55  #define SGTL5000_DAP_BASS_ENHANCE_CTRL     0x0106U
56  #define SGTL5000_DAP_AUDIO_EQ              0x0108U
57  #define SGTL5000_DAP_SGTL_SURROUND         0x010AU
58  #define SGTL5000_DAP_FILTER_COEF_ACCESS    0x010CU
59  #define SGTL5000_DAP_COEF_WR_B0_MSB        0x010EU
60  #define SGTL5000_DAP_COEF_WR_B0_LSB        0x0110U
61  #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0   0x0116U
62  #define SGTL5000_DAP_AUDIO_EQ_BAND1        0x0118U
63  #define SGTL5000_DAP_AUDIO_EQ_BAND2        0x011AU
64  #define SGTL5000_DAP_AUDIO_EQ_BAND3        0x011CU
65  #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4 0x011EU
66  #define SGTL5000_DAP_MAIN_CHAN             0x0120U
67  #define SGTL5000_DAP_MIX_CHAN              0x0122U
68  #define SGTL5000_DAP_AVC_CTRL              0x0124U
69  #define SGTL5000_DAP_AVC_THRESHOLD         0x0126U
70  #define SGTL5000_DAP_AVC_ATTACK            0x0128U
71  #define SGTL5000_DAP_AVC_DECAY             0x012AU
72  #define SGTL5000_DAP_COEF_WR_B1_MSB        0x012CU
73  #define SGTL5000_DAP_COEF_WR_B1_LSB        0x012EU
74  #define SGTL5000_DAP_COEF_WR_B2_MSB        0x0130U
75  #define SGTL5000_DAP_COEF_WR_B2_LSB        0x0132U
76  #define SGTL5000_DAP_COEF_WR_A1_MSB        0x0134U
77  #define SGTL5000_DAP_COEF_WR_A1_LSB        0x0136U
78  #define SGTL5000_DAP_COEF_WR_A2_MSB        0x0138U
79  #define SGTL5000_DAP_COEF_WR_A2_LSB        0x013AU
80  
81  /*
82   * Field Definitions.
83   */
84  
85  /*
86   * SGTL5000_CHIP_DIG_POWER
87   */
88  #define SGTL5000_ADC_ENABLE_CLR_MASK     0xFFBFU
89  #define SGTL5000_ADC_ENABLE_GET_MASK     0x0040U
90  #define SGTL5000_ADC_ENABLE_SHIFT        0x6U
91  #define SGTL5000_DAC_ENABLE_CLR_MASK     0xFFDFU
92  #define SGTL5000_DAC_ENABLE_GET_MASK     0x0020U
93  #define SGTL5000_DAC_ENABLE_SHIFT        0x5U
94  #define SGTL5000_DAP_ENABLE_CLR_MASK     0xFFEFU
95  #define SGTL5000_DAP_ENABLE_GET_MASK     0x0010U
96  #define SGTL5000_DAP_ENABLE_SHIFT        0x4U
97  #define SGTL5000_I2S_OUT_ENABLE_CLR_MASK 0xFFFDU
98  #define SGTL5000_I2S_OUT_ENABLE_GET_MASK 0x0002U
99  #define SGTL5000_I2S_OUT_ENABLE_SHIFT    0x1U
100  #define SGTL5000_I2S_IN_ENABLE_CLR_MASK  0xFFFEU
101  #define SGTL5000_I2S_IN_ENABLE_GET_MASK  0x0001U
102  #define SGTL5000_I2S_IN_ENABLE_SHIFT     0x0U
103  
104  /*
105   * SGTL5000_CHIP_CLK_CTRL
106   */
107  #define SGTL5000_RATE_MODE_CLR_MASK 0xFFCFU
108  #define SGTL5000_RATE_MODE_GET_MASK 0x0030U
109  #define SGTL5000_RATE_MODE_SHIFT    0x4U
110  #define SGTL5000_RATE_MODE_DIV_1    0x0000U
111  #define SGTL5000_RATE_MODE_DIV_2    0x0010U
112  #define SGTL5000_RATE_MODE_DIV_4    0x0020U
113  #define SGTL5000_RATE_MODE_DIV_6    0x0030U
114  #define SGTL5000_SYS_FS_CLR_MASK    0xFFF3U
115  #define SGTL5000_SYS_FS_GET_MASK    0x000CU
116  #define SGTL5000_SYS_FS_SHIFT       0x2U
117  #define SGTL5000_SYS_FS_32k         0x0000U
118  #define SGTL5000_SYS_FS_44_1k       0x0004U
119  #define SGTL5000_SYS_FS_48k         0x0008U
120  #define SGTL5000_SYS_FS_96k         0x000CU
121  #define SGTL5000_MCLK_FREQ_CLR_MASK 0xFFFCU
122  #define SGTL5000_MCLK_FREQ_GET_MASK 0x0003U
123  #define SGTL5000_MCLK_FREQ_SHIFT    0x0U
124  #define SGTL5000_MCLK_FREQ_256FS    0x0000U
125  #define SGTL5000_MCLK_FREQ_384FS    0x0001U
126  #define SGTL5000_MCLK_FREQ_512FS    0x0002U
127  #define SGTL5000_MCLK_FREQ_PLL      0x0003U
128  
129  /*
130   * SGTL5000_CHIP_I2S_CTRL
131   */
132  #define SGTL5000_I2S_SLCKFREQ_CLR_MASK  0xFEFFU
133  #define SGTL5000_I2S_SCLKFREQ_GET_MASK  0x0100U
134  #define SGTL5000_I2S_SCLKFREQ_SHIFT     0x8U
135  #define SGTL5000_I2S_SCLKFREQ_64FS      0x0000U
136  #define SGTL5000_I2S_SCLKFREQ_32FS      0x0100U /* Not for RJ mode */
137  #define SGTL5000_I2S_MS_CLR_MASK        0xFF7FU
138  #define SGTL5000_I2S_MS_GET_MASK        0x0080U
139  #define SGTL5000_I2S_MS_SHIFT           0x7U
140  #define SGTL5000_I2S_MASTER             0x0080U
141  #define SGTL5000_I2S_SLAVE              0x0000U
142  #define SGTL5000_I2S_SCLK_INV_CLR_MASK  0xFFBFU
143  #define SGTL5000_I2S_SCLK_INV_GET_MASK  0x0040U
144  #define SGTL5000_I2S_SCLK_INV_SHIFT     0x6U
145  #define SGTL5000_I2S_VAILD_FALLING_EDGE 0x0040U
146  #define SGTL5000_I2S_VAILD_RISING_EDGE  0x0000U
147  #define SGTL5000_I2S_DLEN_CLR_MASK      0xFFCFU
148  #define SGTL5000_I2S_DLEN_GET_MASK      0x0030U
149  #define SGTL5000_I2S_DLEN_SHIFT         0x4U
150  #define SGTL5000_I2S_DLEN_32            0x0000U
151  #define SGTL5000_I2S_DLEN_24            0x0010U
152  #define SGTL5000_I2S_DLEN_20            0x0020U
153  #define SGTL5000_I2S_DLEN_16            0x0030U
154  #define SGTL5000_I2S_MODE_CLR_MASK      0xFFF3U
155  #define SGTL5000_I2S_MODE_GET_MASK      0x000CU
156  #define SGTL5000_I2S_MODE_SHIFT         0x2U
157  #define SGTL5000_I2S_MODE_I2S_LJ        0x0000U
158  #define SGTL5000_I2S_MODE_RJ            0x0004U
159  #define SGTL5000_I2S_MODE_PCM           0x0008U
160  #define SGTL5000_I2S_LRALIGN_CLR_MASK   0xFFFDU
161  #define SGTL5000_I2S_LRALIGN_GET_MASK   0x0002U
162  #define SGTL5000_I2S_LRALIGN_SHIFT      0x1U
163  #define SGTL5000_I2S_ONE_BIT_DELAY      0x0000U
164  #define SGTL5000_I2S_NO_DELAY           0x0002U
165  #define SGTL5000_I2S_LRPOL_CLR_MASK     0xFFFEU
166  #define SGTL5000_I2S_LRPOL_GET_MASK     0x0001U
167  #define SGTL5000_I2S_LRPOL_SHIFT        0x0U
168  #define SGTL5000_I2S_LEFT_FIRST         0x0000U
169  #define SGTL5000_I2S_RIGHT_FIRST        0x0001U
170  
171  /*
172   * SGTL5000_CHIP_SSS_CTRL
173   */
174  #define SGTL5000_DAP_MIX_LRSWAP_CLR_MASK 0xBFFFU
175  #define SGTL5000_DAP_MIX_LRSWAP_GET_MASK 0x4000U
176  #define SGTL5000_DAP_MIX_LRSWAP_SHIFT    0xEU
177  #define SGTL5000_DAP_LRSWAP_CLR_MASK     0xDFFFU
178  #define SGTL5000_DAP_LRSWAP_GET_MASK     0x2000U
179  #define SGTL5000_DAP_LRSWAP_SHIFT        0xDU
180  #define SGTL5000_DAC_LRSWAP_CLR_MASK     0xEFFFU
181  #define SGTL5000_DAC_LRSWAP_GET_MASK     0x1000U
182  #define SGTL5000_DAC_LRSWAP_SHIFT        0xCU
183  #define SGTL5000_I2S_LRSWAP_CLR_MASK     0xFBFFU
184  #define SGTL5000_I2S_LRSWAP_GET_MASK     0x0400U
185  #define SGTL5000_I2S_LRSWAP_SHIFT        0xAU
186  #define SGTL5000_DAP_MIX_SEL_CLR_MASK    0xFCFFU
187  #define SGTL5000_DAP_MIX_SEL_GET_MASK    0x0300U
188  #define SGTL5000_DAP_MIX_SEL_SHIFT       0x8U
189  #define SGTL5000_DAP_MIX_SEL_ADC         0x0000U
190  #define SGTL5000_DAP_MIX_SEL_I2S_IN      0x0100U
191  #define SGTL5000_DAP_SEL_CLR_MASK        0xFF3FU
192  #define SGTL5000_DAP_SEL_GET_MASK        0x00C0U
193  #define SGTL5000_DAP_SEL_SHIFT           0x6U
194  #define SGTL5000_DAP_SEL_ADC             0x0000U
195  #define SGTL5000_DAP_SEL_I2S_IN          0x0040U
196  #define SGTL5000_DAC_SEL_CLR_MASK        0xFFCFU
197  #define SGTL5000_DAC_SEL_GET_MASK        0x0030U
198  #define SGTL5000_DAC_SEL_SHIFT           0x4U
199  #define SGTL5000_DAC_SEL_ADC             0x0000U
200  #define SGTL5000_DAC_SEL_I2S_IN          0x0010U
201  #define SGTL5000_DAC_SEL_DAP             0x0030U
202  #define SGTL5000_I2S_OUT_SEL_CLR_MASK    0xFFFCU
203  #define SGTL5000_I2S_OUT_SEL_GET_MASK    0x0003U
204  #define SGTL5000_I2S_OUT_SEL_SHIFT       0x0U
205  #define SGTL5000_I2S_OUT_SEL_ADC         0x0000U
206  #define SGTL5000_I2S_OUT_SEL_I2S_IN      0x0001U
207  #define SGTL5000_I2S_OUT_SEL_DAP         0x0003U
208  
209  /*
210   * SGTL5000_CHIP_ADCDAC_CTRL
211   */
212  #define SGTL5000_VOL_BUSY_DAC_RIGHT         0x2000U
213  #define SGTL5000_VOL_BUSY_DAC_LEFT          0x1000U
214  #define SGTL5000_DAC_VOL_RAMP_EN_CLR_MASK   0xFDFFU
215  #define SGTL5000_DAC_VOL_RAMP_EN_GET_MASK   0x0200U
216  #define SGTL5000_DAC_VOL_RAMP_EN_SHIFT      0x9U
217  #define SGTL5000_DAC_VOL_RAMP_EXPO_CLR_MASK 0xFEFFU
218  #define SGTL5000_DAC_VOL_RAMP_EXPO_GET_MASK 0x0100U
219  #define SGTL5000_DAC_VOL_RAMP_EXPO_SHIFT    0x8U
220  #define SGTL5000_DAC_MUTE_RIGHT_CLR_MASK    0xFFF7U
221  #define SGTL5000_DAC_MUTE_RIGHT_GET_MASK    0x0008U
222  #define SGTL5000_DAC_MUTE_RIGHT_SHIFT       0x3U
223  #define SGTL5000_DAC_MUTE_LEFT_CLR_MASK     0xFFFBU
224  #define SGTL5000_DAC_MUTE_LEFT_GET_MASK     0x0004U
225  #define SGTL5000_DAC_MUTE_LEFT_SHIFT        0x2U
226  #define SGTL5000_ADC_HPF_FREEZE_CLR_MASK    0xFFFDU
227  #define SGTL5000_ADC_HPF_FREEZE_GET_MASK    0x0002U
228  #define SGTL5000_ADC_HPF_FREEZE_SHIFT       0x1U
229  #define SGTL5000_ADC_HPF_BYPASS_CLR_MASK    0xFFFEU
230  #define SGTL5000_ADC_HPF_BYPASS_GET_MASK    0x0001U
231  #define SGTL5000_ADC_HPF_BYPASS_SHIFT       0x0U
232  
233  /*
234   * SGTL5000_CHIP_DAC_VOL
235   */
236  #define SGTL5000_DAC_VOL_RIGHT_CLR_MASK 0x00FFU
237  #define SGTL5000_DAC_VOL_RIGHT_GET_MASK 0xFF00U
238  #define SGTL5000_DAC_VOL_RIGHT_SHIFT    0x8U
239  #define SGTL5000_DAC_VOL_LEFT_CLR_MASK  0xFF00U
240  #define SGTL5000_DAC_VOL_LEFT_GET_MASK  0x00FFU
241  #define SGTL5000_DAC_VOL_LEFT_SHIFT     0x0U
242  
243  /*
244   * SGTL5000_CHIP_PAD_STRENGTH
245   */
246  #define SGTL5000_PAD_I2S_LRCLK_CLR_MASK 0xFCFFU
247  #define SGTL5000_PAD_I2S_LRCLK_GET_MASK 0x0300U
248  #define SGTL5000_PAD_I2S_LRCLK_SHIFT    0x8U
249  #define SGTL5000_PAD_I2S_SCLK_CLR_MASK  0xFF3FU
250  #define SGTL5000_PAD_I2S_SCLK_GET_MASK  0x00C0U
251  #define SGTL5000_PAD_I2S_SCLK_SHIFT     0x6U
252  #define SGTL5000_PAD_I2S_DOUT_CLR_MASK  0xFFCFU
253  #define SGTL5000_PAD_I2S_DOUT_GET_MASK  0x0030U
254  #define SGTL5000_PAD_I2S_DOUT_SHIFT     0x4U
255  #define SGTL5000_PAD_I2C_SDA_CLR_MASK   0xFFF3U
256  #define SGTL5000_PAD_I2C_SDA_GET_MASK   0x000CU
257  #define SGTL5000_PAD_I2C_SDA_SHIFT      0x2U
258  #define SGTL5000_PAD_I2C_SCL_CLR_MASK   0xFFFCU
259  #define SGTL5000_PAD_I2C_SCL_GET_MASK   0x0003U
260  #define SGTL5000_PAD_I2C_SCL_SHIFT      0x0U
261  
262  /*
263   * SGTL5000_CHIP_ANA_ADC_CTRL
264   */
265  #define SGTL5000_ADC_VOL_M6DB_CLR_MASK  0xFEFFU
266  #define SGTL5000_ADC_VOL_M6DB_GET_MASK  0x0100U
267  #define SGTL5000_ADC_VOL_M6DB_SHIFT     0x8U
268  #define SGTL5000_ADC_VOL_RIGHT_CLR_MASK 0xFF0FU
269  #define SGTL5000_ADC_VOL_RIGHT_GET_MASK 0x00F0U
270  #define SGTL5000_ADC_VOL_RIGHT_SHIFT    0x4U
271  #define SGTL5000_ADC_VOL_LEFT_CLR_MASK  0xFFF0U
272  #define SGTL5000_ADC_VOL_LEFT_GET_MASK  0x000FU
273  #define SGTL5000_ADC_VOL_LEFT_SHIFT     0x0U
274  
275  /*
276   * SGTL5000_CHIP_ANA_HP_CTRL
277   */
278  #define SGTL5000_HP_VOL_RIGHT_CLR_MASK 0x80FFU
279  #define SGTL5000_HP_VOL_RIGHT_GET_MASK 0x7F00U
280  #define SGTL5000_HP_VOL_RIGHT_SHIFT    0x8U
281  #define SGTL5000_HP_VOL_LEFT_CLR_MASK  0xFF80U
282  #define SGTL5000_HP_VOL_LEFT_GET_MASK  0x007FU
283  #define SGTL5000_HP_VOL_LEFT_SHIFT     0x0U
284  
285  /*
286   * SGTL5000_CHIP_ANA_CTRL
287   */
288  #define SGTL5000_MUTE_LO_GET_MASK    0x0100U
289  #define SGTL5000_MUTE_LO_CLR_MASK    0xFEFFU
290  #define SGTL5000_MUTE_LO_SHIFT       0x8U
291  #define SGTL5000_SEL_HP_GET_MASK     0x0040U
292  #define SGTL5000_SEL_HP_CLR_MASK     0xFFBFU
293  #define SGTL5000_SEL_HP_SHIFT        0x6U
294  #define SGTL5000_SEL_HP_DAC          0x0000U
295  #define SGTL5000_SEL_HP_LINEIN       0x0040U
296  #define SGTL5000_EN_ZCD_HP_GET_MASK  0x0020U
297  #define SGTL5000_EN_ZCD_HP_CLR_MASK  0xFFDFU
298  #define SGTL5000_EN_ZCD_HP_SHIFT     0x5U
299  #define SGTL5000_MUTE_HP_GET_MASK    0x0010U
300  #define SGTL5000_MUTE_HP_CLR_MASK    0xFFEFU
301  #define SGTL5000_MUTE_HP_SHIFT       0x4U
302  #define SGTL5000_SEL_ADC_GET_MASK    0x0004U
303  #define SGTL5000_SEL_ADC_CLR_MASK    0xFFFBU
304  #define SGTL5000_SEL_ADC_SHIFT       0x2U
305  #define SGTL5000_SEL_ADC_MIC         0x0000U
306  #define SGTL5000_SEL_ADC_LINEIN      0x0004U
307  #define SGTL5000_EN_ZCD_ADC_GET_MASK 0x0002U
308  #define SGTL5000_EN_ZCD_ADC_CLR_MASK 0xFFFDU
309  #define SGTL5000_EN_ZCD_ADC_SHIFT    0x1U
310  #define SGTL5000_MUTE_ADC_GET_MASK   0x0001U
311  #define SGTL5000_MUTE_ADC_CLR_MASK   0xFFFEU
312  #define SGTL5000_MUTE_ADC_SHIFT      0x0U
313  
314  /*
315   * SGTL5000_CHIP_LINREG_CTRL
316   */
317  #define SGTL5000_VDDC_MAN_ASSN_CLR_MASK 0xFFBFU
318  #define SGTL5000_VDDC_MAN_ASSN_GET_MASK 0x0040U
319  #define SGTL5000_VDDC_MAN_ASSN_SHIFT    0x6U
320  #define SGTL5000_VDDC_MAN_ASSN_VDDA     0x0000U
321  #define SGTL5000_VDDC_MAN_ASSN_VDDIO    0x0040U
322  #define SGTL5000_VDDC_ASSN_OVRD         0x0020U
323  #define SGTL5000_LINREG_VDDD_CLR_MASK   0xFFF0U
324  #define SGTL5000_LINREG_VDDD_GET_MASK   0x000FU
325  #define SGTL5000_LINREG_VDDD_SHIFT      0x0U
326  
327  /*
328   * SGTL5000_CHIP_REF_CTRL
329   */
330  #define SGTL5000_ANA_GND_MASK    0x01f0U
331  #define SGTL5000_ANA_GND_SHIFT   0x4U
332  #define SGTL5000_ANA_GND_WIDTH   0x5U
333  #define SGTL5000_ANA_GND_BASE    0x320U /* mv */
334  #define SGTL5000_ANA_GND_STP     0x19U  /*mv */
335  #define SGTL5000_BIAS_CTRL_MASK  0x000eU
336  #define SGTL5000_BIAS_CTRL_SHIFT 0x1U
337  #define SGTL5000_BIAS_CTRL_WIDTH 0x3U
338  #define SGTL5000_SMALL_POP       0x0001U
339  
340  /*
341   * SGTL5000_CHIP_MIC_CTRL
342   */
343  #define SGTL5000_BIAS_R__CLR_MASK   0xFCFFU
344  #define SGTL5000_BIAS_R_GET_MASK    0x0300U
345  #define SGTL5000_BIAS_R_SHIFT       0x8U
346  #define SGTL5000_BIAS_R_off         0x0000U
347  #define SGTL5000_BIAS_R_2K          0x0100U
348  #define SGTL5000_BIAS_R_4k          0x0200U
349  #define SGTL5000_BIAS_R_8k          0x0300U
350  #define SGTL5000_BIAS_VOLT_CLR_MASK 0xFF8FU
351  #define SGTL5000_BIAS_VOLT_GET_MASK 0x0070U
352  #define SGTL5000_BIAS_VOLT_SHIFT    0x4U
353  #define SGTL5000_MIC_GAIN_CLR_MASK  0xFFFCU
354  #define SGTL5000_MIC_GAIN_GET_MASK  0x0003U
355  #define SGTL5000_MIC_GAIN_SHIFT     0x0U
356  
357  /*
358   * SGTL5000_CHIP_LINE_OUT_CTRL
359   */
360  #define SGTL5000_LINE_OUT_CURRENT_CLR_MASK 0xF0FFU
361  #define SGTL5000_LINE_OUT_CURRENT_GET_MASK 0x0F00U
362  #define SGTL5000_LINE_OUT_CURRENT_SHIFT    0x8U
363  #define SGTL5000_LINE_OUT_CURRENT_180u     0x0000U
364  #define SGTL5000_LINE_OUT_CURRENT_270u     0x0100U
365  #define SGTL5000_LINE_OUT_CURRENT_360u     0x0300U
366  #define SGTL5000_LINE_OUT_CURRENT_450u     0x0700U
367  #define SGTL5000_LINE_OUT_CURRENT_540u     0x0F00U
368  #define SGTL5000_LINE_OUT_GND_CLR_MASK     0xFFC0U
369  #define SGTL5000_LINE_OUT_GND_GET_MASK     0x003FU
370  #define SGTL5000_LINE_OUT_GND_SHIFT        0x0U
371  #define SGTL5000_LINE_OUT_GND_BASE         0x320U /* mv */
372  #define SGTL5000_LINE_OUT_GND_STP          0x19U
373  #define SGTL5000_LINE_OUT_GND_MAX          0x23U
374  
375  /*
376   * SGTL5000_CHIP_LINE_OUT_VOL
377   */
378  #define SGTL5000_LINE_OUT_VOL_RIGHT_CLR_MASK 0xE0FFU
379  #define SGTL5000_LINE_OUT_VOL_RIGHT_GET_MASK 0x1F00U
380  #define SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT    0x8U
381  #define SGTL5000_LINE_OUT_VOL_LEFT_CLR_MASK  0xFFE0U
382  #define SGTL5000_LINE_OUT_VOL_LEFT_GET_MASK  0x001FU
383  #define SGTL5000_LINE_OUT_VOL_LEFT_SHIFT     0x0U
384  
385  /*
386   * SGTL5000_CHIP_ANA_POWER
387   */
388  #define SGTL5000_RIGHT_DAC_POWERUP_GET_MASK         0x4000U
389  #define SGTL5000_RIGHT_DAC_POWERUP_CLR_MASK         0xBFFFU
390  #define SGTL5000_RIGHT_DAC_POWERUP_SHIFT            0xEU
391  #define SGTL5000_LINREG_SIMPLE_POWERUP_GET_MASK     0x2000U
392  #define SGTL5000_LINREG_SIMPLE_POWERUP_CLR_MASK     0xDFFFU
393  #define SGTL5000_LINREG_SIMPLE_POWERUP_SHIFT        0xDU
394  #define SGTL5000_STARTUP_POWERUP_GET_MASK           0x1000U
395  #define SGTL5000_STARTUP_POWERUP_CLR_MASK           0xEFFFU
396  #define SGTL5000_STARTUP_POWERUP_SHIFT              0xCU
397  #define SGTL5000_VDDC_CHRGPMP_POWERUP_GET_MASK      0x0800U
398  #define SGTL5000_VDDC_CHRGPMP_POWERUP_CLR_MASK      0xF7FFU
399  #define SGTL5000_VDDC_CHRGPMP_POWERUP_SHIFT         0xBU
400  #define SGTL5000_PLL_POWERUP_GET_MASK               0x0400U
401  #define SGTL5000_PLL_POWERUP_CLR_MASK               0xFBFFU
402  #define SGTL5000_PLL_POWERUP_SHIFT                  0xAU
403  #define SGTL5000_LINREG_D_POWERUP_GET_MASK          0x0200U
404  #define SGTL5000_LINREG_D_POWERUP_CLR_MASK          0xFDFFU
405  #define SGTL5000_LINREG_D_POWERUP_SHIFT             0x9U
406  #define SGTL5000_VCOAMP_POWERUP_GET_MASK            0x0100U
407  #define SGTL5000_VCOAMP_POWERUP_CLR_MASK            0xFEFFU
408  #define SGTL5000_VCOAMP_POWERUP_SHIFT               0x8U
409  #define SGTL5000_VAG_POWERUP_GET_MASK               0x0080U
410  #define SGTL5000_VAG_POWERUP_CLR_MASK               0xFF7FU
411  #define SGTL5000_VAG_POWERUP_SHIFT                  0x7U
412  #define SGTL5000_RIGHT_ADC_POWERUP_GET_MASK         0x0040U
413  #define SGTL5000_RIGHT_ADC_POWERUP_CLR_MASK         0xFFBFU
414  #define SGTL5000_RIGHT_ADC_POWERUP_SHIFT            0x6U
415  #define SGTL5000_REFTOP_POWERUP_GET_MASK            0x0020U
416  #define SGTL5000_REFTOP_POWERUP_CLR_MASK            0xFFDFU
417  #define SGTL5000_REFTOP_POWERUP_SHIFT               0x5U
418  #define SGTL5000_HEADPHONE_POWERUP_GET_MASK         0x0010U
419  #define SGTL5000_HEADPHONE_POWERUP_CLR_MASK         0xFFEFU
420  #define SGTL5000_HEADPHONE_POWERUP_SHIFT            0x4U
421  #define SGTL5000_DAC_POWERUP_GET_MASK               0x0008U
422  #define SGTL5000_DAC_POWERUP_CLR_MASK               0xFFF7U
423  #define SGTL5000_DAC_POWERUP_SHIFT                  0x3U
424  #define SGTL5000_CAPLESS_HEADPHONE_POWERUP_GET_MASK 0x0004U
425  #define SGTL5000_CAPLESS_HEADPHONE_POWERUP_CLR_MASK 0xFFFBU
426  #define SGTL5000_CAPLESS_HEADPHONE_POWERUP_SHIFT    0x2U
427  #define SGTL5000_ADC_POWERUP_GET_MASK               0x0002U
428  #define SGTL5000_ADC_POWERUP_CLR_MASK               0xFFFDU
429  #define SGTL5000_ADC_POWERUP_SHIFT                  0x1U
430  #define SGTL5000_LINEOUT_POWERUP_GET_MASK           0x0001U
431  #define SGTL5000_LINEOUT_POWERUP_CLR_MASK           0xFFFEU
432  #define SGTL5000_LINEOUT_POWERUP_SHIFT              0x0U
433  
434  /*
435   * SGTL5000_CHIP_PLL_CTRL
436   */
437  #define SGTL5000_PLL_INT_DIV_CLR_MASK  0x07FFU
438  #define SGTL5000_PLL_INT_DIV_GET_MASK  0xF800U
439  #define SGTL5000_PLL_INT_DIV_SHIFT     0xBU
440  #define SGTL5000_PLL_FRAC_DIV_CLR_MASK 0xF8FFU
441  #define SGTL5000_PLL_FRAC_DIV_GET_MASK 0x0700U
442  #define SGTL5000_PLL_FRAC_DIV_SHIFT    0x0U
443  
444  /*
445   * SGTL5000_CHIP_CLK_TOP_CTRL
446   */
447  #define SGTL5000_ENABLE_INT_OSC_GET_MASK  0x0800U
448  #define SGTL5000_ENABLE_INT_OSC_CLR_MASK  0xF7FFU
449  #define SGTL5000_ENABLE_INT_OSC_SHIFT     0xBU
450  #define SGTL5000_INPUT_FREQ_DIV2_GET_MASK 0x0008U
451  #define SGTL5000_INPUT_FREQ_DIV2_CLR_MASK 0xFFF7U
452  #define SGTL5000_INPUT_FREQ_DIV2_SHIFT    0x3U
453  
454  /*
455   * SGTL5000_CHIP_ANA_STATUS
456   */
457  #define SGTL5000_HP_LRSHORT    0x0200U
458  #define SGTL5000_CAPLESS_SHORT 0x0100U
459  #define SGTL5000_PLL_LOCKED    0x0010U
460  
461  /*
462   * SGTL5000_CHIP_SHORT_CTRL
463   */
464  #define SGTL5000_LVLADJR_CLR_MASK      0x8FFFU
465  #define SGTL5000_LVLADJR_GET_MASK      0x7000U
466  #define SGTL5000_LVLADJR_SHIFT         0xCU
467  #define SGTL5000_LVLADJL_CLR_MASK      0xF8FFU
468  #define SGTL5000_LVLADJL_GET_MASK      0x0700U
469  #define SGTL5000_LVLADJL_SHIFT         0x8U
470  #define SGTL5000_LVLADJC_CLR_MASK      0xFF8FU
471  #define SGTL5000_LVLADJC_GET_MASK      0x0070U
472  #define SGTL5000_LVLADJC_SHIFT         0x4U
473  #define SGTL5000_LR_SHORT_MOD_CLR_MASK 0xFFF3U
474  #define SGTL5000_LR_SHORT_MOD_GET_MASK 0x000CU
475  #define SGTL5000_LR_SHORT_MOD_SHIFT    0x2U
476  #define SGTL5000_CM_SHORT_MOD_CLR_MASK 0xFFFCU
477  #define SGTL5000_CM_SHORT_MOD_GET_MASK 0x0003U
478  #define SGTL5000_CM_SHORT_MOD_SHIFT    0x0U
479  
480  /* DAP control register */
481  #define SGTL5000_DAP_CONTROL_MIX_EN_GET_MASK 0x0010U
482  #define SGTL5000_DAP_CONTROL_MIX_EN_CLR_MASK 0xFFEFU
483  #define SGTL5000_DAP_CONTROL_MIX_EN_SHIFT    0x4U
484  #define SGTL5000_DAP_CONTROL_DAP_EN_GET_MASK 0x0001U
485  #define SGTL5000_DAP_CONTROL_DAP_EN_CLR_MASK 0xFFFEU
486  #define SGTL5000_DAP_CONTROL_DAP_EN_SHIFT    0x0U
487  
488  /*
489   * DAP_PEQ_REG
490   */
491  #define SGTL5000_DAP_PEQ_EN_GET_MASK 0x0007U
492  #define SGTL5000_DAP_PEQ_EN_CLR_MASK 0xFFF8U
493  #define SGTL5000_DAP_PEQ_EN_SHIFT    0x0U
494  
495  /*
496   * DAP_BASS_ENHANCE_REG
497   */
498  #define SGTL5000_DAP_BASS_ENHANCE_MULT_GET_MASK       0xC000U
499  #define SGTL5000_DAP_BASS_ENHANCE_MULT_CLR_MASK       0x3FFFU
500  #define SGTL5000_DAP_BASS_ENHANCE_MULT_SHIFT          0xEU
501  #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_GET_MASK 0x0E00U
502  #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_CLR_MASK 0xF1FFU
503  #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_HPF_SHIFT    0x9U
504  #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_GET_MASK 0x0100U
505  #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_CLR_MASK 0xFEFFU
506  #define SGTL5000_DAP_BASS_ENHANCE_BYPASS_HPF_SHIFT    0x8U
507  #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_GET_MASK     0x0070U
508  #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_CLR_MASK     0xFF8FU
509  #define SGTL5000_DAP_BASS_ENHANCE_CUTOFF_SHIFT        0x4U
510  #define SGTL5000_DAP_BASS_ENHANCE_EN_GET_MASK         0x0001U
511  #define SGTL5000_DAP_BASS_ENHANCE_EN_CLR_MASK         0xFFFEU
512  #define SGTL5000_DAP_BASS_ENHANCE_EN_SHIFT            0x0U
513  
514  /*
515   * DAP_BASS_ENHANCE_CTRL_REG
516   */
517  #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_GET_MASK   0x3F00U
518  #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_CLR_MASK   0xC0FFU
519  #define SGTL5000_DAP_BASS_ENHANCE_CTRL_LR_LEVEL_SHIFT      0x8U
520  #define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_GET_MASK 0x007FU
521  #define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_CLR_MASK 0xFF80U
522  #define SGTL5000_DAP_BASS_ENHANCE_CTRL_BASS_LEVEL_SHIFT    0x0U
523  
524  /*
525   * DAP_AUDIO_EQ_REG
526   */
527  #define SGTL5000_DAP_AUDIO_EQ_EN_GET_MASK 0x0003U
528  #define SGTL5000_DAP_AUDIO_EQ_EN_CLR_MASK 0xFFFCU
529  #define SGTL5000_DAP_AUDIO_EQ_EN_SHIFT    0x0U
530  
531  /*
532   * DAP_SGTL_SURROUND_REG
533   */
534  #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_GET_MASK 0x0070U
535  #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_CLR_MASK 0xFF8FU
536  #define SGTL5000_DAP_SGTL_SURROUND_WIDTH_CONTROL_SHIFT    0x4U
537  #define SGTL5000_DAP_SGTL_SURROUND_SEL_GET_MASK           0x0003U
538  #define SGTL5000_DAP_SGTL_SURROUND_SEL_CLR_MASK           0xFFFCU
539  #define SGTL5000_DAP_SGTL_SURROUND_SEL_SHIFT              0x0U
540  
541  /*
542   * DAP_FILTER_COEF_ACCESS_REG
543   */
544  #define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_GET_MASK 0x1000U
545  #define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_CLR_MASK 0xEFFFU
546  #define SGTL5000_DAP_FILTER_COEF_ACCESS_DEBUG_SHIFT    0xCU
547  #define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_GET_MASK    0x0200U
548  #define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_CLR_MASK    0xFDFFU
549  #define SGTL5000_DAP_FILTER_COEF_ACCESS_RD_SHIFT       0x9U
550  #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_GET_MASK    0x0100U
551  #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_CLR_MASK    0xFEFFU
552  #define SGTL5000_DAP_FILTER_COEF_ACCESS_WR_SHIFT       0x8U
553  #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_GET_MASK 0x00FFU
554  #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_CLR_MASK 0xFF00U
555  #define SGTL5000_DAP_FILTER_COEF_ACCESS_INDEX_SHIFT    0x0U
556  
557  /*
558   *  DAP_COEF_WR_B0_MSB_REG
559   */
560  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_GET_MASK 0x8000U
561  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_CLR_MASK 0x7FFFU
562  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_19_SHIFT    0xFU
563  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_GET_MASK 0x4000U
564  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_CLR_MASK 0xBFFFU
565  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_18_SHIFT    0xEU
566  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_GET_MASK 0x2000U
567  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_CLR_MASK 0xDFFFU
568  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_17_SHIFT    0xDU
569  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_GET_MASK 0x1000U
570  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_CLR_MASK 0xEFFFU
571  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_16_SHIFT    0xCU
572  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_GET_MASK 0x0800U
573  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_CLR_MASK 0xF7FFU
574  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_15_SHIFT    0xBU
575  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_GET_MASK 0x0400U
576  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_CLR_MASK 0xFBFFU
577  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_14_SHIFT    0xAU
578  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_GET_MASK 0x0200U
579  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_CLR_MASK 0xFDFFU
580  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_13_SHIFT    0x9U
581  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_GET_MASK 0x0100U
582  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_CLR_MASK 0xFEFFU
583  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_12_SHIFT    0x8U
584  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_GET_MASK 0x0080U
585  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_CLR_MASK 0xFF7FU
586  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_11_SHIFT    0x7U
587  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_GET_MASK 0x0040U
588  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_CLR_MASK 0xFFBFU
589  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_10_SHIFT    0x6U
590  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_GET_MASK  0x0020U
591  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_CLR_MASK  0xFFDFU
592  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_9_SHIFT     0x5U
593  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_GET_MASK  0x0010U
594  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_CLR_MASK  0xFFEFU
595  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_8_SHIFT     0x4U
596  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_GET_MASK  0x0008U
597  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_CLR_MASK  0xFFF7U
598  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_7_SHIFT     0x3U
599  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_GET_MASK  0x0004U
600  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_CLR_MASK  0xFFFBU
601  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_6_SHIFT     0x2U
602  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_GET_MASK  0x0002U
603  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_CLR_MASK  0xFFFDU
604  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_5_SHIFT     0x1U
605  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_GET_MASK  0x0001U
606  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_CLR_MASK  0xFFFEU
607  #define SGTL5000_DAP_COEF_WR_B0_MSB_BIT_4_SHIFT     0x0U
608  
609  /*
610   * DAP_COEF_WR_B0_LSB_REG
611   */
612  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_GET_MASK 0x0008U
613  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_CLR_MASK 0xFFF7U
614  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_3_SHIFT    0x3U
615  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_GET_MASK 0x0004U
616  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_CLR_MASK 0xFFFBU
617  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_2_SHIFT    0x2U
618  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_GET_MASK 0x0002U
619  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_CLR_MASK 0xFFFDU
620  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_1_SHIFT    0x1U
621  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_GET_MASK 0x0001U
622  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_CLR_MASK 0xFFFEU
623  #define SGTL5000_DAP_COEF_WR_B0_LSB_BIT_0_SHIFT    0x0U
624  
625  /*
626   * DAP_AUDIO_EQ_BASS_BAND0_REG
627   */
628  #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_GET_MASK 0x007FU
629  #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_CLR_MASK 0xFF80U
630  #define SGTL5000_DAP_AUDIO_EQ_BASS_BAND0_VOLUME_SHIFT    0x0U
631  
632  /*
633   * DAP_AUDIO_EQ_BAND1_REG
634   */
635  #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_GET_MASK 0x007FU
636  #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_CLR_MASK 0xFF80U
637  #define SGTL5000_DAP_AUDIO_EQ_BAND1_VOLUME_SHIFT    0x0U
638  
639  /*
640   * DAP_AUDIO_EQ_BAND2_REG
641   */
642  #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_GET_MASK 0x007FU
643  #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_CLR_MASK 0xFF80U
644  #define SGTL5000_DAP_AUDIO_EQ_BAND2_VOLUME_SHIFT    0x0U
645  
646  /*
647   * DAP_AUDIO_EQ_BAND3_REG
648   */
649  #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_GET_MASK 0x007FU
650  #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_CLR_MASK 0xFF80U
651  #define SGTL5000_DAP_AUDIO_EQ_BAND3_VOLUME_SHIFT    0x0U
652  
653  /*
654   * DAP_AUDIO_EQ_TREBLE_BAND4_REG
655   */
656  #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_GET_MASK 0x007FU
657  #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_CLR_MASK 0xFF80U
658  #define SGTL5000_DAP_AUDIO_EQ_TREBLE_BAND4_VOLUME_SHIFT    0x0U
659  
660  /*
661   * DAP_MAIN_CHAN_REG
662   */
663  #define SGTL5000_DAP_MAIN_CHAN_VOL_GET_MASK 0xFFFFU
664  #define SGTL5000_DAP_MAIN_CHAN_VOL_CLR_MASK 0x0000U
665  #define SGTL5000_DAP_MAIN_CHAN_VOL_SHIFT    0x0U
666  
667  /*
668   * DAP_MIX_CHAN_REG
669   */
670  #define SGTL5000_DAP_MIX_CHAN_VOL_GET_MASK 0xFFFFU
671  #define SGTL5000_DAP_MIX_CHAN_VOL_CLR_MASK 0x0000U
672  #define SGTL5000_DAP_MIX_CHAN_VOL_SHIFT    0x0U
673  
674  /*
675   * DAP_AVC_CTRL_REG
676   */
677  #define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_GET_MASK   0x4000U
678  #define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_CLR_MASK   0xBFFFU
679  #define SGTL5000_DAP_AVC_CTRL_APOP_ENABLE_SHIFT      0xEU
680  #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_GET_MASK      0x3000U
681  #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_CLR_MASK      0xCFFFU
682  #define SGTL5000_DAP_AVC_CTRL_MAX_GAIN_SHIFT         0xCU
683  #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_GET_MASK  0x0300U
684  #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_CLR_MASK  0xFCFFU
685  #define SGTL5000_DAP_AVC_CTRL_LBI_RESPONSE_SHIFT     0x8U
686  #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_GET_MASK 0x0020U
687  #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_CLR_MASK 0xFFDFU
688  #define SGTL5000_DAP_AVC_CTRL_HARD_LIMIT_EN_SHIFT    0x5U
689  #define SGTL5000_DAP_AVC_CTRL_STOP_GET_MASK          0x0004U
690  #define SGTL5000_DAP_AVC_CTRL_STOP_SHIFT             0x2U
691  #define SGTL5000_DAP_AVC_CTRL_RUNNING_GET_MASK       0x0002U
692  #define SGTL5000_DAP_AVC_CTRL_RUNNING_SHIFT          0x1U
693  #define SGTL5000_DAP_AVC_CTRL_EN_GET_MASK            0x0001U
694  #define SGTL5000_DAP_AVC_CTRL_EN_CLR_MASK            0xFFFEU
695  #define SGTL5000_DAP_AVC_CTRL_EN_SHIFT               0x0U
696  
697  /*
698   * DAP_AVC_ATTACK_REG
699   */
700  #define SGTL5000_DAP_AVC_ATTACK_RATE_GET_MASK 0x0FFFU
701  #define SGTL5000_DAP_AVC_ATTACK_RATE_CLR_MASK 0xF000U
702  #define SGTL5000_DAP_AVC_ATTACK_RATE_SHIFT    0x0U
703  
704  /*
705   * DAP_AVC_DECAY_REG
706   */
707  #define SGTL5000_DAP_AVC_DECAY_RATE_GET_MASK 0x0FFFU
708  #define SGTL5000_DAP_AVC_DECAY_RATE_CLR_MASK 0xF000U
709  #define SGTL5000_DAP_AVC_DECAY_RATE_SHIFT    0x0U
710  
711  /*
712   * DAP_COEF_WR_B1_LSB_REG
713   */
714  #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_GET_MASK 0x000FU
715  #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_CLR_MASK 0xFFF0U
716  #define SGTL5000_DAP_COEF_WR_B1_LSB_LSB_SHIFT    0x0U
717  
718  /*
719   * DAP_COEF_WR_B2_LSB_REG
720   */
721  #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_GET_MASK 0x000FU
722  #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_CLR_MASK 0xFFF0U
723  #define SGTL5000_DAP_COEF_WR_B2_LSB_LSB_SHIFT    0x0U
724  
725  /*
726   * DAP_COEF_WR_A1_LSB_REG
727   */
728  #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_GET_MASK 0x000FU
729  #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_CLR_MASK 0xFFF0U
730  #define SGTL5000_DAP_COEF_WR_A1_LSB_LSB_SHIFT    0x0U
731  
732  /*
733   * DAP_COEF_WR_A2_LSB_REG
734   */
735  #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_GET_MASK 0x000FU
736  #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_CLR_MASK 0xFFF0U
737  #define SGTL5000_DAP_COEF_WR_A2_LSB_LSB_SHIFT    0x0U
738  
739  /*! @brief SGTL5000 volume setting range */
740  #define SGTL5000_HEADPHONE_MAX_VOLUME_VALUE 0x7FU
741  #define SGTL5000_HEADPHONE_MIN_VOLUME_VALUE 0U
742  #define SGTL5000_LINE_OUT_MAX_VOLUME_VALUE  0x1FU
743  #define SGTL5000_LINE_OUT_MIN_VOLUME_VALUE  0U
744  #define SGTL5000_ADC_MAX_VOLUME_VALUE       0xFU
745  #define SGTL5000_ADC_MIN_VOLUME_VALUE       0U
746  #define SGTL5000_DAC_MAX_VOLUME_VALUE       0xF0U
747  #define SGTL5000_DAC_MIN_VOLUME_VALUE       0x3CU
748  
749  /*! @brief SGTL5000 I2C address. */
750  #define SGTL5000_I2C_ADDR 0x0A
751  
752  /*! @brief sgtl handle size */
753  #ifndef SGTL_I2C_HANDLER_SIZE
754  #define SGTL_I2C_HANDLER_SIZE CODEC_I2C_MASTER_HANDLER_SIZE
755  #endif
756  
757  /*! @brief sgtl i2c baudrate */
758  #define SGTL_I2C_BITRATE 100000U
759  
760  /*! @brief Modules in Sgtl5000 board. */
761  typedef enum _sgtl5000_module
762  {
763      kSGTL_ModuleADC = 0x0, /*!< ADC module in SGTL5000 */
764      kSGTL_ModuleDAC,       /*!< DAC module in SGTL5000 */
765      kSGTL_ModuleDAP,       /*!< DAP module in SGTL5000 */
766      kSGTL_ModuleHP,        /*!< Headphone module in SGTL5000 */
767      kSGTL_ModuleI2SIN,     /*!< I2S-IN module in SGTL5000 */
768      kSGTL_ModuleI2SOUT,    /*!< I2S-OUT module in SGTL5000 */
769      kSGTL_ModuleLineIn,    /*!< Line-in moudle in SGTL5000 */
770      kSGTL_ModuleLineOut,   /*!< Line-out module in SGTL5000 */
771      kSGTL_ModuleMicin      /*!< Micphone module in SGTL5000 */
772  } sgtl_module_t;
773  
774  /*!
775   * @brief Sgtl5000 data route.
776   * @note Only provide some typical data route, not all route listed.
777   * Users cannot combine any routes, once a new route is set, the precios one would be replaced.
778   */
779  typedef enum _sgtl_route
780  {
781      kSGTL_RouteBypass = 0x0,             /*!< LINEIN->Headphone. */
782      kSGTL_RoutePlayback,                 /*!< I2SIN->DAC->Headphone. */
783      kSGTL_RoutePlaybackandRecord,        /*!< I2SIN->DAC->Headphone, LINEIN->ADC->I2SOUT. */
784      kSGTL_RoutePlaybackwithDAP,          /*!< I2SIN->DAP->DAC->Headphone. */
785      kSGTL_RoutePlaybackwithDAPandRecord, /*!< I2SIN->DAP->DAC->HP, LINEIN->ADC->I2SOUT. */
786      kSGTL_RouteRecord                    /*!< LINEIN->ADC->I2SOUT. */
787  } sgtl_route_t;
788  
789  /*!
790   * @brief The audio data transfer protocol choice.
791   * Sgtl5000 only supports I2S format and PCM format.
792   */
793  typedef enum _sgtl_protocol
794  {
795      kSGTL_BusI2S = 0x0,      /*!< I2S Type */
796      kSGTL_BusLeftJustified,  /*!< Left justified */
797      kSGTL_BusRightJustified, /*!< Right Justified */
798      kSGTL_BusPCMA,           /*!< PCMA */
799      kSGTL_BusPCMB            /*!< PCMB */
800  } sgtl_protocol_t;
801  
802  /*! @brief sgtl play channel
803   * @anchor _sgtl_play_channel
804   */
805  enum
806  {
807      kSGTL_HeadphoneLeft  = 0, /*!< headphone left channel */
808      kSGTL_HeadphoneRight = 1, /*!< headphone right channel */
809      kSGTL_LineoutLeft    = 2, /*!< lineout left channel */
810      kSGTL_LineoutRight   = 3, /*!< lineout right channel */
811  };
812  
813  /*! @brief sgtl record source
814   * _sgtl_record_source
815   */
816  enum
817  {
818      kSGTL_RecordSourceLineIn = 0U, /*!< record source line in */
819      kSGTL_RecordSourceMic    = 1U, /*!< record source single end */
820  };
821  
822  /*! @brief sgtl play source
823   * _stgl_play_source
824   */
825  enum
826  {
827      kSGTL_PlaySourceLineIn = 0U, /*!< play source line in */
828      kSGTL_PlaySourceDAC    = 1U, /*!< play source line in */
829  };
830  
831  /*! @brief SGTL SCLK valid edge */
832  typedef enum _sgtl_sclk_edge
833  {
834      kSGTL_SclkValidEdgeRising   = 0U, /*!< SCLK valid edge */
835      kSGTL_SclkValidEdgeFailling = 1U, /*!< SCLK failling edge */
836  } sgtl_sclk_edge_t;
837  
838  /*! @brief Audio format configuration. */
839  typedef struct _sgtl_audio_format
840  {
841      uint32_t mclk_HZ;          /*!< master clock */
842      uint32_t sampleRate;       /*!< Sample rate */
843      uint32_t bitWidth;         /*!< Bit width */
844      sgtl_sclk_edge_t sclkEdge; /*!< sclk valid edge */
845  } sgtl_audio_format_t;
846  
847  /*! @brief Initailize structure of sgtl5000 */
848  typedef struct _sgtl_config
849  {
850      sgtl_route_t route;         /*!< Audio data route.*/
851      sgtl_protocol_t bus;        /*!< Audio transfer protocol */
852      bool master_slave;          /*!< Master or slave. True means master, false means slave. */
853      sgtl_audio_format_t format; /*!< audio format */
854  
855      uint8_t slaveAddress;         /*!< code device slave address */
856      codec_i2c_config_t i2cConfig; /*!< i2c bus configuration */
857  } sgtl_config_t;
858  
859  /*! @brief SGTL codec handler
860   */
861  typedef struct _sgtl_handle
862  {
863      sgtl_config_t *config;                    /*!< sgtl config pointer */
864      uint8_t i2cHandle[SGTL_I2C_HANDLER_SIZE]; /*!< i2c handle */
865  } sgtl_handle_t;
866  
867  /*******************************************************************************
868   * API
869   ******************************************************************************/
870  #if defined(__cplusplus)
871  extern "C" {
872  #endif
873  
874  /*!
875   * @brief sgtl5000 initialize function.
876   *
877   * This function calls SGTL_I2CInit(), and in this function, some configurations
878   * are fixed. The second parameter can be NULL. If users want to change the SGTL5000 settings,
879   * a configure structure should be prepared.
880   * @note If the codec_config is NULL, it would initialize sgtl5000 using default settings.
881   * The default setting:
882   * @code
883   * sgtl_init_t codec_config
884   * codec_config.route = kSGTL_RoutePlaybackandRecord
885   * codec_config.bus = kSGTL_BusI2S
886   * codec_config.master = slave
887   * @endcode
888   *
889   * @param handle Sgtl5000 handle structure.
890   * @param config sgtl5000 configuration structure. If this pointer equals to NULL,
891   * it means using the default configuration.
892   * @return Initialization status
893   */
894  status_t SGTL_Init(sgtl_handle_t *handle, sgtl_config_t *config);
895  
896  /*!
897   * @brief Set audio data route in sgtl5000.
898   *
899   * This function would set the data route according to route. The route cannot be combined,
900   * as all route would enable different modules.
901   *
902   * @note If a new route is set, the previous route would not work.
903   * @param handle Sgtl5000 handle structure.
904   * @param route Audio data route in sgtl5000.
905   */
906  status_t SGTL_SetDataRoute(sgtl_handle_t *handle, sgtl_route_t route);
907  
908  /*!
909   * @brief Set the audio transfer protocol.
910   *
911   * Sgtl5000 only supports I2S, I2S left, I2S right, PCM A, PCM B format.
912   * @param handle Sgtl5000 handle structure.
913   * @param protocol Audio data transfer protocol.
914   */
915  status_t SGTL_SetProtocol(sgtl_handle_t *handle, sgtl_protocol_t protocol);
916  
917  /*!
918   * @brief Set sgtl5000 as master or slave.
919   *
920   * @param handle Sgtl5000 handle structure.
921   * @param master 1 represent master, 0 represent slave.
922   */
923  void SGTL_SetMasterSlave(sgtl_handle_t *handle, bool master);
924  
925  /*!
926   * @brief Set the volume of different modules in sgtl5000.
927   *
928   * This function would set the volume of sgtl5000 modules. This interface set module volume.
929   * The function assume that left channel and right channel has the same volume.
930   *
931   * kSGTL_ModuleADC volume range:      0 - 0xF,     0dB - 22.5dB
932   * kSGTL_ModuleDAC volume range:      0x3C - 0xF0, 0dB - -90dB
933   * kSGTL_ModuleHP volume range:       0 - 0x7F,    12dB - -51.5dB
934   * kSGTL_ModuleLineOut volume range:  0 - 0x1F,    0.5dB steps
935   *
936   * @param handle Sgtl5000 handle structure.
937   * @param module Sgtl5000 module, such as DAC, ADC and etc.
938   * @param volume Volume value need to be set. The value is the exact value in register.
939   */
940  status_t SGTL_SetVolume(sgtl_handle_t *handle, sgtl_module_t module, uint32_t volume);
941  
942  /*!
943   * @brief Get the volume of different modules in sgtl5000.
944   *
945   * This function gets the volume of sgtl5000 modules. This interface get DAC module volume.
946   * The function assume that left channel and right channel has the same volume.
947   * @param handle Sgtl5000 handle structure.
948   * @param module Sgtl5000 module, such as DAC, ADC and etc.
949   * @return Module value, the value is exact value in register.
950   */
951  uint32_t SGTL_GetVolume(sgtl_handle_t *handle, sgtl_module_t module);
952  
953  /*!
954   * @brief Mute/unmute modules in sgtl5000.
955   *
956   * @param handle Sgtl5000 handle structure.
957   * @param module Sgtl5000 module, such as DAC, ADC and etc.
958   * @param mute True means mute, and false means unmute.
959   */
960  status_t SGTL_SetMute(sgtl_handle_t *handle, sgtl_module_t module, bool mute);
961  
962  /*!
963   * @brief Enable expected devices.
964   * @param handle Sgtl5000 handle structure.
965   * @param module Module expected to enable.
966   */
967  status_t SGTL_EnableModule(sgtl_handle_t *handle, sgtl_module_t module);
968  
969  /*!
970   * @brief Disable expected devices.
971   * @param handle Sgtl5000 handle structure.
972   * @param module Module expected to enable.
973   */
974  status_t SGTL_DisableModule(sgtl_handle_t *handle, sgtl_module_t module);
975  
976  /*!
977   * @brief Deinit the sgtl5000 codec. Shut down Sgtl5000 modules.
978   * @param handle Sgtl5000 handle structure pointer.
979   */
980  status_t SGTL_Deinit(sgtl_handle_t *handle);
981  
982  /*!
983   * @brief Configure the data format of audio data.
984   *
985   * This function would configure the registers about the sample rate, bit depths.
986   * @param handle Sgtl5000 handle structure pointer.
987   * @param mclk Master clock frequency of I2S.
988   * @param sample_rate Sample rate of audio file running in sgtl5000. Sgtl5000 now
989   * supports 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k and 96k sample rate.
990   * @param bits Bit depth of audio file (Sgtl5000 only supports 16bit, 20bit, 24bit
991   * and 32 bit in HW).
992   */
993  status_t SGTL_ConfigDataFormat(sgtl_handle_t *handle, uint32_t mclk, uint32_t sample_rate, uint32_t bits);
994  
995  /*!
996   * @brief select SGTL codec play source.
997   *
998   * @param handle Sgtl5000 handle structure pointer.
999   * @param playSource play source value, reference _sgtl_play_source.
1000   *
1001   * @return kStatus_Success, else failed.
1002   */
1003  status_t SGTL_SetPlay(sgtl_handle_t *handle, uint32_t playSource);
1004  
1005  /*!
1006   * @brief select SGTL codec record source.
1007   *
1008   * @param handle Sgtl5000 handle structure pointer.
1009   * @param recordSource record source value, reference _sgtl_record_source.
1010   *
1011   * @return kStatus_Success, else failed.
1012   */
1013  status_t SGTL_SetRecord(sgtl_handle_t *handle, uint32_t recordSource);
1014  
1015  /*!
1016   * @brief Write register to sgtl using I2C.
1017   * @param handle Sgtl5000 handle structure.
1018   * @param reg The register address in sgtl.
1019   * @param val Value needs to write into the register.
1020   */
1021  status_t SGTL_WriteReg(sgtl_handle_t *handle, uint16_t reg, uint16_t val);
1022  
1023  /*!
1024   * @brief Read register from sgtl using I2C.
1025   * @param handle Sgtl5000 handle structure.
1026   * @param reg The register address in sgtl.
1027   * @param val Value written to.
1028   */
1029  status_t SGTL_ReadReg(sgtl_handle_t *handle, uint16_t reg, uint16_t *val);
1030  
1031  /*!
1032   * @brief Modify some bits in the register using I2C.
1033   * @param handle Sgtl5000 handle structure.
1034   * @param reg The register address in sgtl.
1035   * @param clr_mask The mask code for the bits want to write. The bit you want to write should be 0.
1036   * @param val Value needs to write into the register.
1037   */
1038  status_t SGTL_ModifyReg(sgtl_handle_t *handle, uint16_t reg, uint16_t clr_mask, uint16_t val);
1039  
1040  #if defined(__cplusplus)
1041  }
1042  #endif
1043  
1044  /*! @} */
1045  
1046  #endif /* _FSL_SGTL5000_H_ */
1047