1 /* 2 * Copyright (c) 2017-2021 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing software 11 * distributed under the License is distributed on an "AS IS" BASIS 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /** 18 * \file device_definition.c 19 * \brief This file defines exports the structures based on the peripheral 20 * definitions from device_cfg.h. 21 * This file is meant to be used as a helper for baremetal 22 * applications and/or as an example of how to configure the generic 23 * driver structures. 24 */ 25 26 #include "device_cfg.h" 27 #include "device_definition.h" 28 #include "platform_base_address.h" 29 #include "tfm_plat_defs.h" 30 31 /* ======= Peripheral configuration structure definitions ======= */ 32 /* MUSCA B1 SCC driver structures */ 33 #ifdef MUSCA_B1_SCC_S 34 static const struct musca_b1_scc_dev_cfg_t MUSCA_B1_SCC_DEV_CFG_S = { 35 .base = MUSCA_B1_SCC_S_BASE}; 36 struct musca_b1_scc_dev_t MUSCA_B1_SCC_DEV_S = {&(MUSCA_B1_SCC_DEV_CFG_S)}; 37 #endif 38 39 /* Arm PPC SSE 200 driver structures */ 40 #ifdef AHB_PPC0_S 41 static struct ppc_sse200_dev_cfg_t AHB_PPC0_DEV_CFG_S = { 42 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 43 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 44 static struct ppc_sse200_dev_data_t AHB_PPC0_DEV_DATA_S = { 45 .p_ns_ppc = 0, 46 .p_sp_ppc = 0, 47 .p_nsp_ppc = 0, 48 .int_bit_mask = 0, 49 .state = 0 }; 50 struct ppc_sse200_dev_t AHB_PPC0_DEV_S = { 51 &AHB_PPC0_DEV_CFG_S, &AHB_PPC0_DEV_DATA_S }; 52 #endif 53 54 #ifdef AHB_PPCEXP0_S 55 static struct ppc_sse200_dev_cfg_t AHB_PPCEXP0_DEV_CFG_S = { 56 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 57 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 58 static struct ppc_sse200_dev_data_t AHB_PPCEXP0_DEV_DATA_S = { 59 .p_ns_ppc = 0, 60 .p_sp_ppc = 0, 61 .p_nsp_ppc = 0, 62 .int_bit_mask = 0, 63 .state = 0 }; 64 struct ppc_sse200_dev_t AHB_PPCEXP0_DEV_S = { 65 &AHB_PPCEXP0_DEV_CFG_S, &AHB_PPCEXP0_DEV_DATA_S }; 66 #endif 67 68 #ifdef AHB_PPCEXP1_S 69 static struct ppc_sse200_dev_cfg_t AHB_PPCEXP1_DEV_CFG_S = { 70 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 71 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 72 static struct ppc_sse200_dev_data_t AHB_PPCEXP1_DEV_DATA_S = { 73 .p_ns_ppc = 0, 74 .p_sp_ppc = 0, 75 .p_nsp_ppc = 0, 76 .int_bit_mask = 0, 77 .state = 0 }; 78 struct ppc_sse200_dev_t AHB_PPCEXP1_DEV_S = { 79 &AHB_PPCEXP1_DEV_CFG_S, &AHB_PPCEXP1_DEV_DATA_S }; 80 #endif 81 82 #ifdef AHB_PPCEXP2_S 83 static struct ppc_sse200_dev_cfg_t AHB_PPCEXP2_DEV_CFG_S = { 84 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 85 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 86 static struct ppc_sse200_dev_data_t AHB_PPCEXP2_DEV_DATA_S = { 87 .p_ns_ppc = 0, 88 .p_sp_ppc = 0, 89 .p_nsp_ppc = 0, 90 .int_bit_mask = 0, 91 .state = 0 }; 92 struct ppc_sse200_dev_t AHB_PPCEXP2_DEV_S = { 93 &AHB_PPCEXP2_DEV_CFG_S, &AHB_PPCEXP2_DEV_DATA_S }; 94 #endif 95 96 #ifdef AHB_PPCEXP3_S 97 static struct ppc_sse200_dev_cfg_t AHB_PPCEXP3_DEV_CFG_S = { 98 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 99 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 100 static struct ppc_sse200_dev_data_t AHB_PPCEXP3_DEV_DATA_S = { 101 .p_ns_ppc = 0, 102 .p_sp_ppc = 0, 103 .p_nsp_ppc = 0, 104 .int_bit_mask = 0, 105 .state = 0 }; 106 struct ppc_sse200_dev_t AHB_PPCEXP3_DEV_S = { 107 &AHB_PPCEXP3_DEV_CFG_S, &AHB_PPCEXP3_DEV_DATA_S }; 108 #endif 109 110 #ifdef APB_PPC0_S 111 static struct ppc_sse200_dev_cfg_t APB_PPC0_DEV_CFG_S = { 112 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 113 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 114 static struct ppc_sse200_dev_data_t APB_PPC0_DEV_DATA_S = { 115 .p_ns_ppc = 0, 116 .p_sp_ppc = 0, 117 .p_nsp_ppc = 0, 118 .int_bit_mask = 0, 119 .state = 0 }; 120 struct ppc_sse200_dev_t APB_PPC0_DEV_S = { 121 &APB_PPC0_DEV_CFG_S, &APB_PPC0_DEV_DATA_S }; 122 #endif 123 124 #ifdef APB_PPC1_S 125 static struct ppc_sse200_dev_cfg_t APB_PPC1_DEV_CFG_S = { 126 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 127 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 128 static struct ppc_sse200_dev_data_t APB_PPC1_DEV_DATA_S = { 129 .p_ns_ppc = 0, 130 .p_sp_ppc = 0, 131 .p_nsp_ppc = 0, 132 .int_bit_mask = 0, 133 .state = 0 }; 134 struct ppc_sse200_dev_t APB_PPC1_DEV_S = { 135 &APB_PPC1_DEV_CFG_S, &APB_PPC1_DEV_DATA_S}; 136 #endif 137 138 #ifdef APB_PPCEXP0_S 139 static struct ppc_sse200_dev_cfg_t APB_PPCEXP0_DEV_CFG_S = { 140 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 141 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 142 static struct ppc_sse200_dev_data_t APB_PPCEXP0_DEV_DATA_S = { 143 .p_ns_ppc = 0, 144 .p_sp_ppc = 0, 145 .p_nsp_ppc = 0, 146 .int_bit_mask = 0, 147 .state = 0 }; 148 struct ppc_sse200_dev_t APB_PPCEXP0_DEV_S = { 149 &APB_PPCEXP0_DEV_CFG_S, &APB_PPCEXP0_DEV_DATA_S }; 150 #endif 151 152 #ifdef APB_PPCEXP1_S 153 static struct ppc_sse200_dev_cfg_t APB_PPCEXP1_DEV_CFG = { 154 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 155 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 156 static struct ppc_sse200_dev_data_t APB_PPCEXP1_DEV_DATA_S = { 157 .p_ns_ppc = 0, 158 .p_sp_ppc = 0, 159 .p_nsp_ppc = 0, 160 .int_bit_mask = 0, 161 .state = 0 }; 162 struct ppc_sse200_dev_t APB_PPCEXP1_DEV_S = { 163 &APB_PPCEXP1_DEV_CFG, &APB_PPCEXP1_DEV_DATA_S }; 164 #endif 165 166 #ifdef APB_PPCEXP2_S 167 static struct ppc_sse200_dev_cfg_t APB_PPCEXP2_DEV_CFG = { 168 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 169 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 170 static struct ppc_sse200_dev_data_t APB_PPCEXP2_DEV_DATA_S = { 171 .p_ns_ppc = 0, 172 .p_sp_ppc = 0, 173 .p_nsp_ppc = 0, 174 .int_bit_mask = 0, 175 .state = 0 }; 176 struct ppc_sse200_dev_t APB_PPCEXP2_DEV_S = { 177 &APB_PPCEXP2_DEV_CFG, &APB_PPCEXP2_DEV_DATA_S }; 178 #endif 179 180 #ifdef APB_PPCEXP3_S 181 static struct ppc_sse200_dev_cfg_t APB_PPCEXP3_DEV_CFG = { 182 .spctrl_base = MUSCA_B1_SPCTRL_S_BASE, 183 .nspctrl_base = MUSCA_B1_NSPCTRL_NS_BASE }; 184 static struct ppc_sse200_dev_data_t APB_PPCEXP3_DEV_DATA_S = { 185 .p_ns_ppc = 0, 186 .p_sp_ppc = 0, 187 .p_nsp_ppc = 0, 188 .int_bit_mask = 0, 189 .state = 0 }; 190 struct ppc_sse200_dev_t APB_PPCEXP3_DEV_S = { 191 &APB_PPCEXP3_DEV_CFG, &APB_PPCEXP3_DEV_DATA_S }; 192 #endif 193 194 /* Arm MPC SIE 200 driver structures */ 195 #ifdef MPC_ISRAM0_S 196 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM0_DEV_CFG_S = { 197 .base = MUSCA_B1_MPC_SRAM0_S_BASE}; 198 static struct mpc_sie200_dev_data_t MPC_ISRAM0_DEV_DATA_S = { 199 .range_list = 0, 200 .nbr_of_ranges = 0, 201 .state = 0, 202 .reserved = 0}; 203 struct mpc_sie200_dev_t MPC_ISRAM0_DEV_S = { 204 &(MPC_ISRAM0_DEV_CFG_S), 205 &(MPC_ISRAM0_DEV_DATA_S)}; 206 #endif 207 208 #ifdef MPC_ISRAM1_S 209 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM1_DEV_CFG_S = { 210 .base = MUSCA_B1_MPC_SRAM1_S_BASE}; 211 static struct mpc_sie200_dev_data_t MPC_ISRAM1_DEV_DATA_S = { 212 .range_list = 0, 213 .nbr_of_ranges = 0, 214 .state = 0, 215 .reserved = 0}; 216 struct mpc_sie200_dev_t MPC_ISRAM1_DEV_S = { 217 &(MPC_ISRAM1_DEV_CFG_S), 218 &(MPC_ISRAM1_DEV_DATA_S)}; 219 #endif 220 221 #ifdef MPC_ISRAM2_S 222 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM2_DEV_CFG_S = { 223 .base = MUSCA_B1_MPC_SRAM2_S_BASE}; 224 static struct mpc_sie200_dev_data_t MPC_ISRAM2_DEV_DATA_S = { 225 .range_list = 0, 226 .nbr_of_ranges = 0, 227 .state = 0, 228 .reserved = 0}; 229 struct mpc_sie200_dev_t MPC_ISRAM2_DEV_S = { 230 &(MPC_ISRAM2_DEV_CFG_S), 231 &(MPC_ISRAM2_DEV_DATA_S)}; 232 #endif 233 234 #ifdef MPC_ISRAM3_S 235 static const struct mpc_sie200_dev_cfg_t MPC_ISRAM3_DEV_CFG_S = { 236 .base = MUSCA_B1_MPC_SRAM3_S_BASE}; 237 static struct mpc_sie200_dev_data_t MPC_ISRAM3_DEV_DATA_S = { 238 .range_list = 0, 239 .nbr_of_ranges = 0, 240 .state = 0, 241 .reserved = 0}; 242 struct mpc_sie200_dev_t MPC_ISRAM3_DEV_S = { 243 &(MPC_ISRAM3_DEV_CFG_S), 244 &(MPC_ISRAM3_DEV_DATA_S)}; 245 #endif 246 247 #ifdef MPC_CODE_SRAM_S 248 static const struct mpc_sie200_dev_cfg_t MPC_CODE_SRAM_DEV_CFG_S = { 249 .base = MUSCA_B1_CODE_SRAM_MPC_S_BASE}; 250 static struct mpc_sie200_dev_data_t MPC_CODE_SRAM_DEV_DATA_S = { 251 .range_list = 0, 252 .nbr_of_ranges = 0, 253 .state = 0, 254 .reserved = 0}; 255 struct mpc_sie200_dev_t MPC_CODE_SRAM_DEV_S = { 256 &(MPC_CODE_SRAM_DEV_CFG_S), 257 &(MPC_CODE_SRAM_DEV_DATA_S)}; 258 #endif 259 260 #ifdef MPC_QSPI_S 261 static const struct mpc_sie200_dev_cfg_t MPC_QSPI_DEV_CFG_S = { 262 .base = MUSCA_B1_QSPI_MPC_S_BASE}; 263 static struct mpc_sie200_dev_data_t MPC_QSPI_DEV_DATA_S = { 264 .range_list = 0, 265 .nbr_of_ranges = 0, 266 .state = 0, 267 .reserved = 0}; 268 struct mpc_sie200_dev_t MPC_QSPI_DEV_S = { 269 &(MPC_QSPI_DEV_CFG_S), 270 &(MPC_QSPI_DEV_DATA_S)}; 271 #endif 272 273 #ifdef MPC_EFLASH0_S 274 static const struct mpc_sie200_dev_cfg_t MPC_EFLASH0_DEV_CFG_S = { 275 .base = MUSCA_B1_EFLASH0_MPC_S_BASE}; 276 static struct mpc_sie200_dev_data_t MPC_EFLASH0_DEV_DATA_S = { 277 .range_list = 0, 278 .nbr_of_ranges = 0, 279 .state = 0, 280 .reserved = 0}; 281 struct mpc_sie200_dev_t MPC_EFLASH0_DEV_S = { 282 &(MPC_EFLASH0_DEV_CFG_S), 283 &(MPC_EFLASH0_DEV_DATA_S)}; 284 #endif 285 286 #ifdef MPC_EFLASH1_S 287 static const struct mpc_sie200_dev_cfg_t MPC_EFLASH1_DEV_CFG_S = { 288 .base = MUSCA_B1_EFLASH1_MPC_S_BASE}; 289 static struct mpc_sie200_dev_data_t MPC_EFLASH1_DEV_DATA_S = { 290 .range_list = 0, 291 .nbr_of_ranges = 0, 292 .state = 0, 293 .reserved = 0}; 294 struct mpc_sie200_dev_t MPC_EFLASH1_DEV_S = { 295 &(MPC_EFLASH1_DEV_CFG_S), 296 &(MPC_EFLASH1_DEV_DATA_S)}; 297 #endif 298 299 /** CMSDK GPIO driver structures */ 300 #ifdef GPIO0_CMSDK_S 301 static const struct gpio_cmsdk_dev_cfg_t GPIO0_CMSDK_DEV_CFG_S = { 302 .base = MUSCA_B1_GPIO_S_BASE}; 303 struct gpio_cmsdk_dev_t GPIO0_CMSDK_DEV_S = {&(GPIO0_CMSDK_DEV_CFG_S)}; 304 #endif 305 306 /** Arm UART PL011 driver structures */ 307 #ifdef UART0_PL011_S 308 static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_S = { 309 .base = MUSCA_B1_UART0_S_BASE, 310 .def_baudrate = DEFAULT_UART_BAUDRATE, 311 .def_wlen = UART_PL011_WLEN_8, 312 .def_parity = UART_PL011_PARITY_DISABLED, 313 .def_stopbit = UART_PL011_STOPBIT_1}; 314 static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_S = { 315 .state = UART_PL011_UNINITIALIZED, 316 .uart_clk = 0, 317 .baudrate = 0}; 318 struct uart_pl011_dev_t UART0_PL011_DEV_S = {&(UART0_PL011_DEV_CFG_S), 319 &(UART0_PL011_DEV_DATA_S)}; 320 #endif 321 #ifdef UART0_PL011_NS 322 static const struct uart_pl011_dev_cfg_t UART0_PL011_DEV_CFG_NS = { 323 .base = MUSCA_B1_UART0_NS_BASE, 324 .def_baudrate = DEFAULT_UART_BAUDRATE, 325 .def_wlen = UART_PL011_WLEN_8, 326 .def_parity = UART_PL011_PARITY_DISABLED, 327 .def_stopbit = UART_PL011_STOPBIT_1}; 328 static struct uart_pl011_dev_data_t UART0_PL011_DEV_DATA_NS = { 329 .state = UART_PL011_UNINITIALIZED, 330 .uart_clk = 0, 331 .baudrate = 0}; 332 struct uart_pl011_dev_t UART0_PL011_DEV_NS = {&(UART0_PL011_DEV_CFG_NS), 333 &(UART0_PL011_DEV_DATA_NS)}; 334 #endif 335 336 #ifdef UART1_PL011_S 337 static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_S = { 338 .base = MUSCA_B1_UART1_S_BASE, 339 .def_baudrate = DEFAULT_UART_BAUDRATE, 340 .def_wlen = UART_PL011_WLEN_8, 341 .def_parity = UART_PL011_PARITY_DISABLED, 342 .def_stopbit = UART_PL011_STOPBIT_1}; 343 static struct uart_pl011_dev_data_t UART1_PL011_DEV_DATA_S = { 344 .state = UART_PL011_UNINITIALIZED, 345 .uart_clk = 0, 346 .baudrate = 0}; 347 struct uart_pl011_dev_t UART1_PL011_DEV_S = {&(UART1_PL011_DEV_CFG_S), 348 &(UART1_PL011_DEV_DATA_S)}; 349 #endif 350 #ifdef UART1_PL011_NS 351 static const struct uart_pl011_dev_cfg_t UART1_PL011_DEV_CFG_NS = { 352 .base = MUSCA_B1_UART1_NS_BASE, 353 .def_baudrate = DEFAULT_UART_BAUDRATE, 354 .def_wlen = UART_PL011_WLEN_8, 355 .def_parity = UART_PL011_PARITY_DISABLED, 356 .def_stopbit = UART_PL011_STOPBIT_1}; 357 static struct uart_pl011_dev_data_t UART1_PL011_DEV_DATA_NS = { 358 .state = UART_PL011_UNINITIALIZED, 359 .uart_clk = 0, 360 .baudrate = 0}; 361 struct uart_pl011_dev_t UART1_PL011_DEV_NS = {&(UART1_PL011_DEV_CFG_NS), 362 &(UART1_PL011_DEV_DATA_NS)}; 363 #endif 364 365 /** CMSDK Timers driver structures */ 366 #ifdef CMSDK_TIMER0_S 367 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_S 368 #ifdef TEST_NS_SLIH_IRQ 369 TFM_LINK_SET_RO_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 370 #endif 371 = {.base = MUSCA_B1_CMSDK_TIMER0_S_BASE}; 372 static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_S 373 #ifdef TEST_NS_SLIH_IRQ 374 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 375 #endif 376 = {.is_initialized = 0}; 377 struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_S 378 #ifdef TEST_NS_SLIH_IRQ 379 TFM_LINK_SET_RW_IN_PARTITION_SECTION("TFM_SP_SLIH_TEST", "APP-ROT") 380 #endif 381 = {&(CMSDK_TIMER0_DEV_CFG_S), &(CMSDK_TIMER0_DEV_DATA_S)}; 382 #endif 383 #ifdef CMSDK_TIMER0_NS 384 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER0_DEV_CFG_NS = { 385 .base = MUSCA_B1_CMSDK_TIMER0_NS_BASE}; 386 static struct timer_cmsdk_dev_data_t CMSDK_TIMER0_DEV_DATA_NS = { 387 .is_initialized = 0}; 388 struct timer_cmsdk_dev_t CMSDK_TIMER0_DEV_NS = {&(CMSDK_TIMER0_DEV_CFG_NS), 389 &(CMSDK_TIMER0_DEV_DATA_NS)}; 390 #endif 391 392 #ifdef CMSDK_TIMER1_S 393 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_S = { 394 .base = MUSCA_B1_CMSDK_TIMER1_S_BASE}; 395 static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_S = { 396 .is_initialized = 0}; 397 struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_S = {&(CMSDK_TIMER1_DEV_CFG_S), 398 &(CMSDK_TIMER1_DEV_DATA_S)}; 399 #endif 400 #ifdef CMSDK_TIMER1_NS 401 static const struct timer_cmsdk_dev_cfg_t CMSDK_TIMER1_DEV_CFG_NS = { 402 .base = MUSCA_B1_CMSDK_TIMER1_NS_BASE}; 403 static struct timer_cmsdk_dev_data_t CMSDK_TIMER1_DEV_DATA_NS = { 404 .is_initialized = 0}; 405 struct timer_cmsdk_dev_t CMSDK_TIMER1_DEV_NS = {&(CMSDK_TIMER1_DEV_CFG_NS), 406 &(CMSDK_TIMER1_DEV_DATA_NS)}; 407 #endif 408 409 /** GFC-100 eflash driver structures */ 410 #ifdef GFC100_EFLASH0_S 411 static const struct gfc100_eflash_dev_cfg_t GFC100_EFLASH0_CFG_S = { 412 .base = MUSCA_B1_EFLASH0_REG_MAP_S_BASE}; 413 static struct gfc100_eflash_dev_data_t GFC100_EFLASH0_DATA_S = { 414 .is_initialized = false, 415 .flash_size = 0}; 416 struct gfc100_eflash_dev_t GFC100_EFLASH0_DEV_S = {&(GFC100_EFLASH0_CFG_S), 417 &(GFC100_EFLASH0_DATA_S)}; 418 #endif 419 420 #ifdef GFC100_EFLASH1_S 421 static const struct gfc100_eflash_dev_cfg_t GFC100_EFLASH1_CFG_S = { 422 .base = MUSCA_B1_EFLASH1_REG_MAP_S_BASE}; 423 static struct gfc100_eflash_dev_data_t GFC100_EFLASH1_DATA_S = { 424 .is_initialized = false, 425 .flash_size = 0}; 426 struct gfc100_eflash_dev_t GFC100_EFLASH1_DEV_S = {&(GFC100_EFLASH1_CFG_S), 427 &(GFC100_EFLASH1_DATA_S)}; 428 #endif 429 430 /* QSPI IP6514E driver structures */ 431 #ifdef QSPI_IP6514E_S 432 static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_S = { 433 .base = MUSCA_B1_QSPI_REG_S_BASE, 434 .addr_mask = (1U << 23) - 1, /* 8MiB minus 1 byte */ 435 }; 436 struct qspi_ip6514e_dev_t QSPI_DEV_S = { 437 &QSPI_DEV_CFG_S 438 }; 439 #endif 440 441 #ifdef QSPI_IP6514E_NS 442 static const struct qspi_ip6514e_dev_cfg_t QSPI_DEV_CFG_NS = { 443 .base = MUSCA_B1_QSPI_REG_NS_BASE, 444 .addr_mask = (1U << 23) - 1, /* 8MiB minus 1 byte */ 445 }; 446 struct qspi_ip6514e_dev_t QSPI_DEV_NS = { 447 &QSPI_DEV_CFG_NS 448 }; 449 #endif 450 451 /* SE MHU */ 452 #ifdef SE_MHU_SENDER_S 453 struct mhu_v2_x_dev_t SE_MHU_SENDER_DEV_S = { 454 .base = MUSCA_B1_SE_MHU_SND_S_BASE, 455 .frame = MHU_V2_X_SENDER_FRAME 456 }; 457 #endif 458 #ifdef SE_MHU_SENDER_NS 459 struct mhu_v2_x_dev_t SE_MHU_SENDER_DEV_NS = { 460 .base = MUSCA_B1_SE_MHU_SND_NS_BASE, 461 .frame = MHU_V2_X_SENDER_FRAME 462 }; 463 #endif 464 465 #ifdef SE_MHU_RECEIVER_S 466 struct mhu_v2_x_dev_t SE_MHU_RECEIVER_DEV_S = { 467 .base = MUSCA_B1_SE_MHU_RCV_S_BASE, 468 .frame = MHU_V2_X_RECEIVER_FRAME 469 }; 470 #endif 471 #ifdef SE_MHU_RECEIVER_NS 472 struct mhu_v2_x_dev_t SE_MHU_RECEIVER_DEV_NS = { 473 .base = MUSCA_B1_SE_MHU_RCV_NS_BASE, 474 .frame = MHU_V2_X_RECEIVER_FRAME 475 }; 476 #endif 477 478 /* ======= External peripheral configuration structure definitions ======= */ 479 480 /* MT25QL Flash memory library structures */ 481 #if (defined(MT25QL_S) && defined(QSPI_IP6514E_S)) 482 struct mt25ql_dev_t MT25QL_DEV_S = { 483 .controller = &QSPI_DEV_S, 484 .direct_access_start_addr = MUSCA_B1_QSPI_FLASH_S_BASE, 485 .baud_rate_div = 4U, 486 /* 487 * 8 MiB flash memory are advertised in the Arm Musca-B1 Test Chip and Board 488 * Technical Reference Manual. The MT25QL Flash device may however contain 489 * more. 490 */ 491 .size = 0x00800000U, /* 8 MiB */ 492 .config_state = { 0 }, 493 }; 494 #endif 495 496 #if (defined(MT25QL_NS) && defined(QSPI_IP6514E_NS)) 497 struct mt25ql_dev_t MT25QL_DEV_NS = { 498 .controller = &QSPI_DEV_NS, 499 .direct_access_start_addr = MUSCA_B1_QSPI_FLASH_NS_BASE, 500 .baud_rate_div = 4U, 501 /* 502 * 8 MiB flash memory are advertised in the Arm Musca-B1 Test Chip and Board 503 * Technical Reference Manual. The MT25QL Flash device may however contain 504 * more. 505 */ 506 .size = 0x00800000U, /* 8 MiB */ 507 .config_state = { 0 }, 508 }; 509 #endif 510
