1 /* 2 * Copyright (c) 2021, NXP 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 8 #ifndef _SOC_ARM_NXP_IMX_RT_POWER_RT11XX_H_ 9 #define _SOC_ARM_NXP_IMX_RT_POWER_RT11XX_H_ 10 11 /* 12 * Set point configurations. These are kept in a separate file for readability. 13 */ 14 15 #define SP0 0 16 #define SP1 1 17 #define SP2 2 18 #define SP3 3 19 #define SP4 4 20 #define SP5 5 21 #define SP6 6 22 #define SP7 7 23 #define SP8 8 24 #define SP9 9 25 #define SP10 10 26 #define SP11 11 27 #define SP12 12 28 #define SP13 13 29 #define SP14 14 30 #define SP15 15 31 32 33 /* ================= GPC configuration ==================== */ 34 35 #define SET_POINT_COUNT 16 36 37 /* 38 * SOC set point mappings 39 * This matrix defines what set points are allowed for a given core. 40 * For example, when SP2 is requested, SP1 or SP2 are allowed set points 41 */ 42 #define CPU0_COMPATIBLE_SP_TABLE \ 43 /* NA, SP1, SP2, SP3, SP0, SP4, SP5, SP6, SP7, SP8, SP9, SP10, SP11, SP12, SP13, SP14, SP15 */ \ 44 /* SP1*/{{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 45 /* SP2 */{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 46 /* SP3 */{ 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 47 /* SP0 */{ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 48 /* SP4 */{ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 49 /* SP5 */{ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 50 /* SP6 */{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 51 /* SP7 */{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0}, \ 52 /* SP8 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0}, \ 53 /* SP9 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0}, \ 54 /* SP10 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0}, \ 55 /* SP11 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \ 56 /* SP12 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \ 57 /* SP13 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \ 58 /* SP14 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}, \ 59 /* SP15 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}} 60 61 #define CPU1_COMPATIBLE_SP_TABLE \ 62 /* NA, SP1, SP2, SP3, SP0, SP4, SP5, SP6, SP7, SP8, SP9, SP10, SP11, SP12, SP13, SP14, SP15 */ \ 63 /* SP1*/{{ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 64 /* SP2 */{ 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 65 /* SP3 */{ 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \ 66 /* SP0 */{ 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, \ 67 /* SP4 */{ 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \ 68 /* SP5 */{ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \ 69 /* SP6 */{ 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \ 70 /* SP7 */{ 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 0, 0}, \ 71 /* SP8 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0}, \ 72 /* SP9 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, 0, 0}, \ 73 /* SP10 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0}, \ 74 /* SP11 */{ 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0}, \ 75 /* SP12 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 0, 0, 0}, \ 76 /* SP13 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0}, \ 77 /* SP14 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0}, \ 78 /* SP15 */{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}} 79 80 /* Allows GPC to control RC16M on/off */ 81 #define OSC_RC_16M_STBY_VAL 0x0000 82 83 84 /* ================== DCDC configuration ======================= */ 85 #define PD_WKUP_SP_VAL 0xf800 /* Off at SP11 - SP 15 */ 86 87 #define DCDC_ONOFF_SP_VAL (~PD_WKUP_SP_VAL) 88 #define DCDC_DIG_ONOFF_SP_VAL DCDC_ONOFF_SP_VAL 89 #define DCDC_LP_MODE_SP_VAL 0x0000 90 #define DCDC_ONOFF_STBY_VAL DCDC_ONOFF_SP_VAL 91 #define DCDC_LP_MODE_STBY_VAL 0x0000 92 93 94 /* DCDC 1.8V buck mode target voltage in set points 0-15 */ 95 #define DCDC_1P8_BUCK_MODE_CONFIGURATION_TABLE \ 96 { \ 97 kDCDC_1P8BuckTarget1P8V, \ 98 kDCDC_1P8BuckTarget1P8V, \ 99 kDCDC_1P8BuckTarget1P8V, \ 100 kDCDC_1P8BuckTarget1P8V, \ 101 kDCDC_1P8BuckTarget1P8V, \ 102 kDCDC_1P8BuckTarget1P8V, \ 103 kDCDC_1P8BuckTarget1P8V, \ 104 kDCDC_1P8BuckTarget1P8V, \ 105 kDCDC_1P8BuckTarget1P8V, \ 106 kDCDC_1P8BuckTarget1P8V, \ 107 kDCDC_1P8BuckTarget1P8V, \ 108 kDCDC_1P8BuckTarget1P8V, \ 109 kDCDC_1P8BuckTarget1P8V, \ 110 kDCDC_1P8BuckTarget1P8V, \ 111 kDCDC_1P8BuckTarget1P8V, \ 112 kDCDC_1P8BuckTarget1P8V, \ 113 } 114 115 /* DCDC 1.0V buck mode target voltage in set points 0-15 */ 116 #define DCDC_1P0_BUCK_MODE_CONFIGURATION_TABLE \ 117 { \ 118 kDCDC_1P0BuckTarget1P0V, \ 119 kDCDC_1P0BuckTarget1P1V, \ 120 kDCDC_1P0BuckTarget1P1V, \ 121 kDCDC_1P0BuckTarget1P1V, \ 122 kDCDC_1P0BuckTarget1P0V, \ 123 kDCDC_1P0BuckTarget0P9V, \ 124 kDCDC_1P0BuckTarget0P9V, \ 125 kDCDC_1P0BuckTarget0P9V, \ 126 kDCDC_1P0BuckTarget0P9V, \ 127 kDCDC_1P0BuckTarget0P9V, \ 128 kDCDC_1P0BuckTarget0P8V, \ 129 kDCDC_1P0BuckTarget0P9V, \ 130 kDCDC_1P0BuckTarget0P9V, \ 131 kDCDC_1P0BuckTarget0P9V, \ 132 kDCDC_1P0BuckTarget0P9V, \ 133 kDCDC_1P0BuckTarget0P9V, \ 134 } 135 136 137 /* DCDC 1.8V standby mode target voltage in set points 0-15 */ 138 #define DCDC_1P8_STANDBY_MODE_CONFIGURATION_TABLE \ 139 { \ 140 kDCDC_1P8StbyTarget1P8V, \ 141 kDCDC_1P8StbyTarget1P8V, \ 142 kDCDC_1P8StbyTarget1P8V, \ 143 kDCDC_1P8StbyTarget1P8V, \ 144 kDCDC_1P8StbyTarget1P8V, \ 145 kDCDC_1P8StbyTarget1P8V, \ 146 kDCDC_1P8StbyTarget1P8V, \ 147 kDCDC_1P8StbyTarget1P8V, \ 148 kDCDC_1P8StbyTarget1P8V, \ 149 kDCDC_1P8StbyTarget1P8V, \ 150 kDCDC_1P8StbyTarget1P8V, \ 151 kDCDC_1P8StbyTarget1P8V, \ 152 kDCDC_1P8StbyTarget1P8V, \ 153 kDCDC_1P8StbyTarget1P8V, \ 154 kDCDC_1P8StbyTarget1P8V, \ 155 kDCDC_1P8StbyTarget1P8V, \ 156 } 157 158 /* DCDC 1.0V standby mode target voltage in set points 0-15 */ 159 #define DCDC_1P0_STANDBY_MODE_CONFIGURATION_TABLE \ 160 { \ 161 kDCDC_1P0StbyTarget1P0V, \ 162 kDCDC_1P0StbyTarget1P1V, \ 163 kDCDC_1P0StbyTarget1P1V, \ 164 kDCDC_1P0StbyTarget1P1V, \ 165 kDCDC_1P0StbyTarget1P0V, \ 166 kDCDC_1P0StbyTarget0P9V, \ 167 kDCDC_1P0StbyTarget0P9V, \ 168 kDCDC_1P0StbyTarget0P9V, \ 169 kDCDC_1P0StbyTarget0P9V, \ 170 kDCDC_1P0StbyTarget0P9V, \ 171 kDCDC_1P0StbyTarget0P8V, \ 172 kDCDC_1P0StbyTarget0P9V, \ 173 kDCDC_1P0StbyTarget0P9V, \ 174 kDCDC_1P0StbyTarget0P9V, \ 175 kDCDC_1P0StbyTarget0P9V, \ 176 kDCDC_1P0StbyTarget0P9V, \ 177 } 178 179 #endif /* _SOC_ARM_NXP_IMX_RT_POWER_RT11XX_H_ */ 180
