1 /** 2 * \file 3 * 4 * \brief Component description for SERCOM 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_SERCOM_COMPONENT_ 30 #define _SAML21_SERCOM_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR SERCOM */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_SERCOM Serial Communication Interface */ 36 /*@{*/ 37 38 #define SERCOM_U2201 39 #define REV_SERCOM 0x220 40 41 /* -------- SERCOM_I2CM_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CM I2CM Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 48 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 49 uint32_t RUNSTDBY:1; /*!< bit: 7 Run in Standby */ 50 uint32_t :8; /*!< bit: 8..15 Reserved */ 51 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 52 uint32_t :3; /*!< bit: 17..19 Reserved */ 53 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 54 uint32_t MEXTTOEN:1; /*!< bit: 22 Master SCL Low Extend Timeout */ 55 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ 56 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ 57 uint32_t :1; /*!< bit: 26 Reserved */ 58 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ 59 uint32_t INACTOUT:2; /*!< bit: 28..29 Inactive Time-Out */ 60 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ 61 uint32_t :1; /*!< bit: 31 Reserved */ 62 } bit; /*!< Structure used for bit access */ 63 uint32_t reg; /*!< Type used for register access */ 64 } SERCOM_I2CM_CTRLA_Type; 65 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 66 67 #define SERCOM_I2CM_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CM_CTRLA offset) I2CM Control A */ 68 #define SERCOM_I2CM_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_CTRLA reset_value) I2CM Control A */ 69 70 #define SERCOM_I2CM_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_CTRLA) Software Reset */ 71 #define SERCOM_I2CM_CTRLA_SWRST (_U(0x1) << SERCOM_I2CM_CTRLA_SWRST_Pos) 72 #define SERCOM_I2CM_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_CTRLA) Enable */ 73 #define SERCOM_I2CM_CTRLA_ENABLE (_U(0x1) << SERCOM_I2CM_CTRLA_ENABLE_Pos) 74 #define SERCOM_I2CM_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CM_CTRLA) Operating Mode */ 75 #define SERCOM_I2CM_CTRLA_MODE_Msk (_U(0x7) << SERCOM_I2CM_CTRLA_MODE_Pos) 76 #define SERCOM_I2CM_CTRLA_MODE(value) (SERCOM_I2CM_CTRLA_MODE_Msk & ((value) << SERCOM_I2CM_CTRLA_MODE_Pos)) 77 #define SERCOM_I2CM_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CM_CTRLA) Run in Standby */ 78 #define SERCOM_I2CM_CTRLA_RUNSTDBY (_U(0x1) << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) 79 #define SERCOM_I2CM_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CM_CTRLA) Pin Usage */ 80 #define SERCOM_I2CM_CTRLA_PINOUT (_U(0x1) << SERCOM_I2CM_CTRLA_PINOUT_Pos) 81 #define SERCOM_I2CM_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CM_CTRLA) SDA Hold Time */ 82 #define SERCOM_I2CM_CTRLA_SDAHOLD_Msk (_U(0x3) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos) 83 #define SERCOM_I2CM_CTRLA_SDAHOLD(value) (SERCOM_I2CM_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CM_CTRLA_SDAHOLD_Pos)) 84 #define SERCOM_I2CM_CTRLA_MEXTTOEN_Pos 22 /**< \brief (SERCOM_I2CM_CTRLA) Master SCL Low Extend Timeout */ 85 #define SERCOM_I2CM_CTRLA_MEXTTOEN (_U(0x1) << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) 86 #define SERCOM_I2CM_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CM_CTRLA) Slave SCL Low Extend Timeout */ 87 #define SERCOM_I2CM_CTRLA_SEXTTOEN (_U(0x1) << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) 88 #define SERCOM_I2CM_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CM_CTRLA) Transfer Speed */ 89 #define SERCOM_I2CM_CTRLA_SPEED_Msk (_U(0x3) << SERCOM_I2CM_CTRLA_SPEED_Pos) 90 #define SERCOM_I2CM_CTRLA_SPEED(value) (SERCOM_I2CM_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CM_CTRLA_SPEED_Pos)) 91 #define SERCOM_I2CM_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CM_CTRLA) SCL Clock Stretch Mode */ 92 #define SERCOM_I2CM_CTRLA_SCLSM (_U(0x1) << SERCOM_I2CM_CTRLA_SCLSM_Pos) 93 #define SERCOM_I2CM_CTRLA_INACTOUT_Pos 28 /**< \brief (SERCOM_I2CM_CTRLA) Inactive Time-Out */ 94 #define SERCOM_I2CM_CTRLA_INACTOUT_Msk (_U(0x3) << SERCOM_I2CM_CTRLA_INACTOUT_Pos) 95 #define SERCOM_I2CM_CTRLA_INACTOUT(value) (SERCOM_I2CM_CTRLA_INACTOUT_Msk & ((value) << SERCOM_I2CM_CTRLA_INACTOUT_Pos)) 96 #define SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CM_CTRLA) SCL Low Timeout Enable */ 97 #define SERCOM_I2CM_CTRLA_LOWTOUTEN (_U(0x1) << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) 98 #define SERCOM_I2CM_CTRLA_MASK _U(0x7BF1009F) /**< \brief (SERCOM_I2CM_CTRLA) MASK Register */ 99 100 /* -------- SERCOM_I2CS_CTRLA : (SERCOM Offset: 0x00) (R/W 32) I2CS I2CS Control A -------- */ 101 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 102 typedef union { 103 struct { 104 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 105 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 106 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 107 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 108 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 109 uint32_t :8; /*!< bit: 8..15 Reserved */ 110 uint32_t PINOUT:1; /*!< bit: 16 Pin Usage */ 111 uint32_t :3; /*!< bit: 17..19 Reserved */ 112 uint32_t SDAHOLD:2; /*!< bit: 20..21 SDA Hold Time */ 113 uint32_t :1; /*!< bit: 22 Reserved */ 114 uint32_t SEXTTOEN:1; /*!< bit: 23 Slave SCL Low Extend Timeout */ 115 uint32_t SPEED:2; /*!< bit: 24..25 Transfer Speed */ 116 uint32_t :1; /*!< bit: 26 Reserved */ 117 uint32_t SCLSM:1; /*!< bit: 27 SCL Clock Stretch Mode */ 118 uint32_t :2; /*!< bit: 28..29 Reserved */ 119 uint32_t LOWTOUTEN:1; /*!< bit: 30 SCL Low Timeout Enable */ 120 uint32_t :1; /*!< bit: 31 Reserved */ 121 } bit; /*!< Structure used for bit access */ 122 uint32_t reg; /*!< Type used for register access */ 123 } SERCOM_I2CS_CTRLA_Type; 124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 #define SERCOM_I2CS_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_I2CS_CTRLA offset) I2CS Control A */ 127 #define SERCOM_I2CS_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_CTRLA reset_value) I2CS Control A */ 128 129 #define SERCOM_I2CS_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_CTRLA) Software Reset */ 130 #define SERCOM_I2CS_CTRLA_SWRST (_U(0x1) << SERCOM_I2CS_CTRLA_SWRST_Pos) 131 #define SERCOM_I2CS_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_CTRLA) Enable */ 132 #define SERCOM_I2CS_CTRLA_ENABLE (_U(0x1) << SERCOM_I2CS_CTRLA_ENABLE_Pos) 133 #define SERCOM_I2CS_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_I2CS_CTRLA) Operating Mode */ 134 #define SERCOM_I2CS_CTRLA_MODE_Msk (_U(0x7) << SERCOM_I2CS_CTRLA_MODE_Pos) 135 #define SERCOM_I2CS_CTRLA_MODE(value) (SERCOM_I2CS_CTRLA_MODE_Msk & ((value) << SERCOM_I2CS_CTRLA_MODE_Pos)) 136 #define SERCOM_I2CS_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_I2CS_CTRLA) Run during Standby */ 137 #define SERCOM_I2CS_CTRLA_RUNSTDBY (_U(0x1) << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) 138 #define SERCOM_I2CS_CTRLA_PINOUT_Pos 16 /**< \brief (SERCOM_I2CS_CTRLA) Pin Usage */ 139 #define SERCOM_I2CS_CTRLA_PINOUT (_U(0x1) << SERCOM_I2CS_CTRLA_PINOUT_Pos) 140 #define SERCOM_I2CS_CTRLA_SDAHOLD_Pos 20 /**< \brief (SERCOM_I2CS_CTRLA) SDA Hold Time */ 141 #define SERCOM_I2CS_CTRLA_SDAHOLD_Msk (_U(0x3) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos) 142 #define SERCOM_I2CS_CTRLA_SDAHOLD(value) (SERCOM_I2CS_CTRLA_SDAHOLD_Msk & ((value) << SERCOM_I2CS_CTRLA_SDAHOLD_Pos)) 143 #define SERCOM_I2CS_CTRLA_SEXTTOEN_Pos 23 /**< \brief (SERCOM_I2CS_CTRLA) Slave SCL Low Extend Timeout */ 144 #define SERCOM_I2CS_CTRLA_SEXTTOEN (_U(0x1) << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) 145 #define SERCOM_I2CS_CTRLA_SPEED_Pos 24 /**< \brief (SERCOM_I2CS_CTRLA) Transfer Speed */ 146 #define SERCOM_I2CS_CTRLA_SPEED_Msk (_U(0x3) << SERCOM_I2CS_CTRLA_SPEED_Pos) 147 #define SERCOM_I2CS_CTRLA_SPEED(value) (SERCOM_I2CS_CTRLA_SPEED_Msk & ((value) << SERCOM_I2CS_CTRLA_SPEED_Pos)) 148 #define SERCOM_I2CS_CTRLA_SCLSM_Pos 27 /**< \brief (SERCOM_I2CS_CTRLA) SCL Clock Stretch Mode */ 149 #define SERCOM_I2CS_CTRLA_SCLSM (_U(0x1) << SERCOM_I2CS_CTRLA_SCLSM_Pos) 150 #define SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos 30 /**< \brief (SERCOM_I2CS_CTRLA) SCL Low Timeout Enable */ 151 #define SERCOM_I2CS_CTRLA_LOWTOUTEN (_U(0x1) << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos) 152 #define SERCOM_I2CS_CTRLA_MASK _U(0x4BB1009F) /**< \brief (SERCOM_I2CS_CTRLA) MASK Register */ 153 154 /* -------- SERCOM_SPI_CTRLA : (SERCOM Offset: 0x00) (R/W 32) SPI SPI Control A -------- */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef union { 157 struct { 158 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 159 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 160 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 161 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 162 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 163 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 164 uint32_t :7; /*!< bit: 9..15 Reserved */ 165 uint32_t DOPO:2; /*!< bit: 16..17 Data Out Pinout */ 166 uint32_t :2; /*!< bit: 18..19 Reserved */ 167 uint32_t DIPO:2; /*!< bit: 20..21 Data In Pinout */ 168 uint32_t :2; /*!< bit: 22..23 Reserved */ 169 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 170 uint32_t CPHA:1; /*!< bit: 28 Clock Phase */ 171 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 172 uint32_t DORD:1; /*!< bit: 30 Data Order */ 173 uint32_t :1; /*!< bit: 31 Reserved */ 174 } bit; /*!< Structure used for bit access */ 175 uint32_t reg; /*!< Type used for register access */ 176 } SERCOM_SPI_CTRLA_Type; 177 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 178 179 #define SERCOM_SPI_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_SPI_CTRLA offset) SPI Control A */ 180 #define SERCOM_SPI_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_CTRLA reset_value) SPI Control A */ 181 182 #define SERCOM_SPI_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_SPI_CTRLA) Software Reset */ 183 #define SERCOM_SPI_CTRLA_SWRST (_U(0x1) << SERCOM_SPI_CTRLA_SWRST_Pos) 184 #define SERCOM_SPI_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_CTRLA) Enable */ 185 #define SERCOM_SPI_CTRLA_ENABLE (_U(0x1) << SERCOM_SPI_CTRLA_ENABLE_Pos) 186 #define SERCOM_SPI_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_SPI_CTRLA) Operating Mode */ 187 #define SERCOM_SPI_CTRLA_MODE_Msk (_U(0x7) << SERCOM_SPI_CTRLA_MODE_Pos) 188 #define SERCOM_SPI_CTRLA_MODE(value) (SERCOM_SPI_CTRLA_MODE_Msk & ((value) << SERCOM_SPI_CTRLA_MODE_Pos)) 189 #define SERCOM_SPI_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_SPI_CTRLA) Run during Standby */ 190 #define SERCOM_SPI_CTRLA_RUNSTDBY (_U(0x1) << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) 191 #define SERCOM_SPI_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_SPI_CTRLA) Immediate Buffer Overflow Notification */ 192 #define SERCOM_SPI_CTRLA_IBON (_U(0x1) << SERCOM_SPI_CTRLA_IBON_Pos) 193 #define SERCOM_SPI_CTRLA_DOPO_Pos 16 /**< \brief (SERCOM_SPI_CTRLA) Data Out Pinout */ 194 #define SERCOM_SPI_CTRLA_DOPO_Msk (_U(0x3) << SERCOM_SPI_CTRLA_DOPO_Pos) 195 #define SERCOM_SPI_CTRLA_DOPO(value) (SERCOM_SPI_CTRLA_DOPO_Msk & ((value) << SERCOM_SPI_CTRLA_DOPO_Pos)) 196 #define SERCOM_SPI_CTRLA_DIPO_Pos 20 /**< \brief (SERCOM_SPI_CTRLA) Data In Pinout */ 197 #define SERCOM_SPI_CTRLA_DIPO_Msk (_U(0x3) << SERCOM_SPI_CTRLA_DIPO_Pos) 198 #define SERCOM_SPI_CTRLA_DIPO(value) (SERCOM_SPI_CTRLA_DIPO_Msk & ((value) << SERCOM_SPI_CTRLA_DIPO_Pos)) 199 #define SERCOM_SPI_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_SPI_CTRLA) Frame Format */ 200 #define SERCOM_SPI_CTRLA_FORM_Msk (_U(0xF) << SERCOM_SPI_CTRLA_FORM_Pos) 201 #define SERCOM_SPI_CTRLA_FORM(value) (SERCOM_SPI_CTRLA_FORM_Msk & ((value) << SERCOM_SPI_CTRLA_FORM_Pos)) 202 #define SERCOM_SPI_CTRLA_CPHA_Pos 28 /**< \brief (SERCOM_SPI_CTRLA) Clock Phase */ 203 #define SERCOM_SPI_CTRLA_CPHA (_U(0x1) << SERCOM_SPI_CTRLA_CPHA_Pos) 204 #define SERCOM_SPI_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_SPI_CTRLA) Clock Polarity */ 205 #define SERCOM_SPI_CTRLA_CPOL (_U(0x1) << SERCOM_SPI_CTRLA_CPOL_Pos) 206 #define SERCOM_SPI_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_SPI_CTRLA) Data Order */ 207 #define SERCOM_SPI_CTRLA_DORD (_U(0x1) << SERCOM_SPI_CTRLA_DORD_Pos) 208 #define SERCOM_SPI_CTRLA_MASK _U(0x7F33019F) /**< \brief (SERCOM_SPI_CTRLA) MASK Register */ 209 210 /* -------- SERCOM_USART_CTRLA : (SERCOM Offset: 0x00) (R/W 32) USART USART Control A -------- */ 211 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 212 typedef union { 213 struct { 214 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 215 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 216 uint32_t MODE:3; /*!< bit: 2.. 4 Operating Mode */ 217 uint32_t :2; /*!< bit: 5.. 6 Reserved */ 218 uint32_t RUNSTDBY:1; /*!< bit: 7 Run during Standby */ 219 uint32_t IBON:1; /*!< bit: 8 Immediate Buffer Overflow Notification */ 220 uint32_t :4; /*!< bit: 9..12 Reserved */ 221 uint32_t SAMPR:3; /*!< bit: 13..15 Sample */ 222 uint32_t TXPO:2; /*!< bit: 16..17 Transmit Data Pinout */ 223 uint32_t :2; /*!< bit: 18..19 Reserved */ 224 uint32_t RXPO:2; /*!< bit: 20..21 Receive Data Pinout */ 225 uint32_t SAMPA:2; /*!< bit: 22..23 Sample Adjustment */ 226 uint32_t FORM:4; /*!< bit: 24..27 Frame Format */ 227 uint32_t CMODE:1; /*!< bit: 28 Communication Mode */ 228 uint32_t CPOL:1; /*!< bit: 29 Clock Polarity */ 229 uint32_t DORD:1; /*!< bit: 30 Data Order */ 230 uint32_t :1; /*!< bit: 31 Reserved */ 231 } bit; /*!< Structure used for bit access */ 232 uint32_t reg; /*!< Type used for register access */ 233 } SERCOM_USART_CTRLA_Type; 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 235 236 #define SERCOM_USART_CTRLA_OFFSET 0x00 /**< \brief (SERCOM_USART_CTRLA offset) USART Control A */ 237 #define SERCOM_USART_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_USART_CTRLA reset_value) USART Control A */ 238 239 #define SERCOM_USART_CTRLA_SWRST_Pos 0 /**< \brief (SERCOM_USART_CTRLA) Software Reset */ 240 #define SERCOM_USART_CTRLA_SWRST (_U(0x1) << SERCOM_USART_CTRLA_SWRST_Pos) 241 #define SERCOM_USART_CTRLA_ENABLE_Pos 1 /**< \brief (SERCOM_USART_CTRLA) Enable */ 242 #define SERCOM_USART_CTRLA_ENABLE (_U(0x1) << SERCOM_USART_CTRLA_ENABLE_Pos) 243 #define SERCOM_USART_CTRLA_MODE_Pos 2 /**< \brief (SERCOM_USART_CTRLA) Operating Mode */ 244 #define SERCOM_USART_CTRLA_MODE_Msk (_U(0x7) << SERCOM_USART_CTRLA_MODE_Pos) 245 #define SERCOM_USART_CTRLA_MODE(value) (SERCOM_USART_CTRLA_MODE_Msk & ((value) << SERCOM_USART_CTRLA_MODE_Pos)) 246 #define SERCOM_USART_CTRLA_RUNSTDBY_Pos 7 /**< \brief (SERCOM_USART_CTRLA) Run during Standby */ 247 #define SERCOM_USART_CTRLA_RUNSTDBY (_U(0x1) << SERCOM_USART_CTRLA_RUNSTDBY_Pos) 248 #define SERCOM_USART_CTRLA_IBON_Pos 8 /**< \brief (SERCOM_USART_CTRLA) Immediate Buffer Overflow Notification */ 249 #define SERCOM_USART_CTRLA_IBON (_U(0x1) << SERCOM_USART_CTRLA_IBON_Pos) 250 #define SERCOM_USART_CTRLA_SAMPR_Pos 13 /**< \brief (SERCOM_USART_CTRLA) Sample */ 251 #define SERCOM_USART_CTRLA_SAMPR_Msk (_U(0x7) << SERCOM_USART_CTRLA_SAMPR_Pos) 252 #define SERCOM_USART_CTRLA_SAMPR(value) (SERCOM_USART_CTRLA_SAMPR_Msk & ((value) << SERCOM_USART_CTRLA_SAMPR_Pos)) 253 #define SERCOM_USART_CTRLA_TXPO_Pos 16 /**< \brief (SERCOM_USART_CTRLA) Transmit Data Pinout */ 254 #define SERCOM_USART_CTRLA_TXPO_Msk (_U(0x3) << SERCOM_USART_CTRLA_TXPO_Pos) 255 #define SERCOM_USART_CTRLA_TXPO(value) (SERCOM_USART_CTRLA_TXPO_Msk & ((value) << SERCOM_USART_CTRLA_TXPO_Pos)) 256 #define SERCOM_USART_CTRLA_RXPO_Pos 20 /**< \brief (SERCOM_USART_CTRLA) Receive Data Pinout */ 257 #define SERCOM_USART_CTRLA_RXPO_Msk (_U(0x3) << SERCOM_USART_CTRLA_RXPO_Pos) 258 #define SERCOM_USART_CTRLA_RXPO(value) (SERCOM_USART_CTRLA_RXPO_Msk & ((value) << SERCOM_USART_CTRLA_RXPO_Pos)) 259 #define SERCOM_USART_CTRLA_SAMPA_Pos 22 /**< \brief (SERCOM_USART_CTRLA) Sample Adjustment */ 260 #define SERCOM_USART_CTRLA_SAMPA_Msk (_U(0x3) << SERCOM_USART_CTRLA_SAMPA_Pos) 261 #define SERCOM_USART_CTRLA_SAMPA(value) (SERCOM_USART_CTRLA_SAMPA_Msk & ((value) << SERCOM_USART_CTRLA_SAMPA_Pos)) 262 #define SERCOM_USART_CTRLA_FORM_Pos 24 /**< \brief (SERCOM_USART_CTRLA) Frame Format */ 263 #define SERCOM_USART_CTRLA_FORM_Msk (_U(0xF) << SERCOM_USART_CTRLA_FORM_Pos) 264 #define SERCOM_USART_CTRLA_FORM(value) (SERCOM_USART_CTRLA_FORM_Msk & ((value) << SERCOM_USART_CTRLA_FORM_Pos)) 265 #define SERCOM_USART_CTRLA_CMODE_Pos 28 /**< \brief (SERCOM_USART_CTRLA) Communication Mode */ 266 #define SERCOM_USART_CTRLA_CMODE (_U(0x1) << SERCOM_USART_CTRLA_CMODE_Pos) 267 #define SERCOM_USART_CTRLA_CPOL_Pos 29 /**< \brief (SERCOM_USART_CTRLA) Clock Polarity */ 268 #define SERCOM_USART_CTRLA_CPOL (_U(0x1) << SERCOM_USART_CTRLA_CPOL_Pos) 269 #define SERCOM_USART_CTRLA_DORD_Pos 30 /**< \brief (SERCOM_USART_CTRLA) Data Order */ 270 #define SERCOM_USART_CTRLA_DORD (_U(0x1) << SERCOM_USART_CTRLA_DORD_Pos) 271 #define SERCOM_USART_CTRLA_MASK _U(0x7FF3E19F) /**< \brief (SERCOM_USART_CTRLA) MASK Register */ 272 273 /* -------- SERCOM_I2CM_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CM I2CM Control B -------- */ 274 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 275 typedef union { 276 struct { 277 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 278 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 279 uint32_t QCEN:1; /*!< bit: 9 Quick Command Enable */ 280 uint32_t :6; /*!< bit: 10..15 Reserved */ 281 uint32_t CMD:2; /*!< bit: 16..17 Command */ 282 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 283 uint32_t :13; /*!< bit: 19..31 Reserved */ 284 } bit; /*!< Structure used for bit access */ 285 uint32_t reg; /*!< Type used for register access */ 286 } SERCOM_I2CM_CTRLB_Type; 287 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 288 289 #define SERCOM_I2CM_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CM_CTRLB offset) I2CM Control B */ 290 #define SERCOM_I2CM_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_CTRLB reset_value) I2CM Control B */ 291 292 #define SERCOM_I2CM_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CM_CTRLB) Smart Mode Enable */ 293 #define SERCOM_I2CM_CTRLB_SMEN (_U(0x1) << SERCOM_I2CM_CTRLB_SMEN_Pos) 294 #define SERCOM_I2CM_CTRLB_QCEN_Pos 9 /**< \brief (SERCOM_I2CM_CTRLB) Quick Command Enable */ 295 #define SERCOM_I2CM_CTRLB_QCEN (_U(0x1) << SERCOM_I2CM_CTRLB_QCEN_Pos) 296 #define SERCOM_I2CM_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CM_CTRLB) Command */ 297 #define SERCOM_I2CM_CTRLB_CMD_Msk (_U(0x3) << SERCOM_I2CM_CTRLB_CMD_Pos) 298 #define SERCOM_I2CM_CTRLB_CMD(value) (SERCOM_I2CM_CTRLB_CMD_Msk & ((value) << SERCOM_I2CM_CTRLB_CMD_Pos)) 299 #define SERCOM_I2CM_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CM_CTRLB) Acknowledge Action */ 300 #define SERCOM_I2CM_CTRLB_ACKACT (_U(0x1) << SERCOM_I2CM_CTRLB_ACKACT_Pos) 301 #define SERCOM_I2CM_CTRLB_MASK _U(0x00070300) /**< \brief (SERCOM_I2CM_CTRLB) MASK Register */ 302 303 /* -------- SERCOM_I2CS_CTRLB : (SERCOM Offset: 0x04) (R/W 32) I2CS I2CS Control B -------- */ 304 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 305 typedef union { 306 struct { 307 uint32_t :8; /*!< bit: 0.. 7 Reserved */ 308 uint32_t SMEN:1; /*!< bit: 8 Smart Mode Enable */ 309 uint32_t GCMD:1; /*!< bit: 9 PMBus Group Command */ 310 uint32_t AACKEN:1; /*!< bit: 10 Automatic Address Acknowledge */ 311 uint32_t :3; /*!< bit: 11..13 Reserved */ 312 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 313 uint32_t CMD:2; /*!< bit: 16..17 Command */ 314 uint32_t ACKACT:1; /*!< bit: 18 Acknowledge Action */ 315 uint32_t :13; /*!< bit: 19..31 Reserved */ 316 } bit; /*!< Structure used for bit access */ 317 uint32_t reg; /*!< Type used for register access */ 318 } SERCOM_I2CS_CTRLB_Type; 319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 320 321 #define SERCOM_I2CS_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_I2CS_CTRLB offset) I2CS Control B */ 322 #define SERCOM_I2CS_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_CTRLB reset_value) I2CS Control B */ 323 324 #define SERCOM_I2CS_CTRLB_SMEN_Pos 8 /**< \brief (SERCOM_I2CS_CTRLB) Smart Mode Enable */ 325 #define SERCOM_I2CS_CTRLB_SMEN (_U(0x1) << SERCOM_I2CS_CTRLB_SMEN_Pos) 326 #define SERCOM_I2CS_CTRLB_GCMD_Pos 9 /**< \brief (SERCOM_I2CS_CTRLB) PMBus Group Command */ 327 #define SERCOM_I2CS_CTRLB_GCMD (_U(0x1) << SERCOM_I2CS_CTRLB_GCMD_Pos) 328 #define SERCOM_I2CS_CTRLB_AACKEN_Pos 10 /**< \brief (SERCOM_I2CS_CTRLB) Automatic Address Acknowledge */ 329 #define SERCOM_I2CS_CTRLB_AACKEN (_U(0x1) << SERCOM_I2CS_CTRLB_AACKEN_Pos) 330 #define SERCOM_I2CS_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_I2CS_CTRLB) Address Mode */ 331 #define SERCOM_I2CS_CTRLB_AMODE_Msk (_U(0x3) << SERCOM_I2CS_CTRLB_AMODE_Pos) 332 #define SERCOM_I2CS_CTRLB_AMODE(value) (SERCOM_I2CS_CTRLB_AMODE_Msk & ((value) << SERCOM_I2CS_CTRLB_AMODE_Pos)) 333 #define SERCOM_I2CS_CTRLB_CMD_Pos 16 /**< \brief (SERCOM_I2CS_CTRLB) Command */ 334 #define SERCOM_I2CS_CTRLB_CMD_Msk (_U(0x3) << SERCOM_I2CS_CTRLB_CMD_Pos) 335 #define SERCOM_I2CS_CTRLB_CMD(value) (SERCOM_I2CS_CTRLB_CMD_Msk & ((value) << SERCOM_I2CS_CTRLB_CMD_Pos)) 336 #define SERCOM_I2CS_CTRLB_ACKACT_Pos 18 /**< \brief (SERCOM_I2CS_CTRLB) Acknowledge Action */ 337 #define SERCOM_I2CS_CTRLB_ACKACT (_U(0x1) << SERCOM_I2CS_CTRLB_ACKACT_Pos) 338 #define SERCOM_I2CS_CTRLB_MASK _U(0x0007C700) /**< \brief (SERCOM_I2CS_CTRLB) MASK Register */ 339 340 /* -------- SERCOM_SPI_CTRLB : (SERCOM Offset: 0x04) (R/W 32) SPI SPI Control B -------- */ 341 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 342 typedef union { 343 struct { 344 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 345 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 346 uint32_t PLOADEN:1; /*!< bit: 6 Data Preload Enable */ 347 uint32_t :2; /*!< bit: 7.. 8 Reserved */ 348 uint32_t SSDE:1; /*!< bit: 9 Slave Select Low Detect Enable */ 349 uint32_t :3; /*!< bit: 10..12 Reserved */ 350 uint32_t MSSEN:1; /*!< bit: 13 Master Slave Select Enable */ 351 uint32_t AMODE:2; /*!< bit: 14..15 Address Mode */ 352 uint32_t :1; /*!< bit: 16 Reserved */ 353 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 354 uint32_t :14; /*!< bit: 18..31 Reserved */ 355 } bit; /*!< Structure used for bit access */ 356 uint32_t reg; /*!< Type used for register access */ 357 } SERCOM_SPI_CTRLB_Type; 358 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 359 360 #define SERCOM_SPI_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_SPI_CTRLB offset) SPI Control B */ 361 #define SERCOM_SPI_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_CTRLB reset_value) SPI Control B */ 362 363 #define SERCOM_SPI_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_SPI_CTRLB) Character Size */ 364 #define SERCOM_SPI_CTRLB_CHSIZE_Msk (_U(0x7) << SERCOM_SPI_CTRLB_CHSIZE_Pos) 365 #define SERCOM_SPI_CTRLB_CHSIZE(value) (SERCOM_SPI_CTRLB_CHSIZE_Msk & ((value) << SERCOM_SPI_CTRLB_CHSIZE_Pos)) 366 #define SERCOM_SPI_CTRLB_PLOADEN_Pos 6 /**< \brief (SERCOM_SPI_CTRLB) Data Preload Enable */ 367 #define SERCOM_SPI_CTRLB_PLOADEN (_U(0x1) << SERCOM_SPI_CTRLB_PLOADEN_Pos) 368 #define SERCOM_SPI_CTRLB_SSDE_Pos 9 /**< \brief (SERCOM_SPI_CTRLB) Slave Select Low Detect Enable */ 369 #define SERCOM_SPI_CTRLB_SSDE (_U(0x1) << SERCOM_SPI_CTRLB_SSDE_Pos) 370 #define SERCOM_SPI_CTRLB_MSSEN_Pos 13 /**< \brief (SERCOM_SPI_CTRLB) Master Slave Select Enable */ 371 #define SERCOM_SPI_CTRLB_MSSEN (_U(0x1) << SERCOM_SPI_CTRLB_MSSEN_Pos) 372 #define SERCOM_SPI_CTRLB_AMODE_Pos 14 /**< \brief (SERCOM_SPI_CTRLB) Address Mode */ 373 #define SERCOM_SPI_CTRLB_AMODE_Msk (_U(0x3) << SERCOM_SPI_CTRLB_AMODE_Pos) 374 #define SERCOM_SPI_CTRLB_AMODE(value) (SERCOM_SPI_CTRLB_AMODE_Msk & ((value) << SERCOM_SPI_CTRLB_AMODE_Pos)) 375 #define SERCOM_SPI_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_SPI_CTRLB) Receiver Enable */ 376 #define SERCOM_SPI_CTRLB_RXEN (_U(0x1) << SERCOM_SPI_CTRLB_RXEN_Pos) 377 #define SERCOM_SPI_CTRLB_MASK _U(0x0002E247) /**< \brief (SERCOM_SPI_CTRLB) MASK Register */ 378 379 /* -------- SERCOM_USART_CTRLB : (SERCOM Offset: 0x04) (R/W 32) USART USART Control B -------- */ 380 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 381 typedef union { 382 struct { 383 uint32_t CHSIZE:3; /*!< bit: 0.. 2 Character Size */ 384 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 385 uint32_t SBMODE:1; /*!< bit: 6 Stop Bit Mode */ 386 uint32_t :1; /*!< bit: 7 Reserved */ 387 uint32_t COLDEN:1; /*!< bit: 8 Collision Detection Enable */ 388 uint32_t SFDE:1; /*!< bit: 9 Start of Frame Detection Enable */ 389 uint32_t ENC:1; /*!< bit: 10 Encoding Format */ 390 uint32_t :2; /*!< bit: 11..12 Reserved */ 391 uint32_t PMODE:1; /*!< bit: 13 Parity Mode */ 392 uint32_t :2; /*!< bit: 14..15 Reserved */ 393 uint32_t TXEN:1; /*!< bit: 16 Transmitter Enable */ 394 uint32_t RXEN:1; /*!< bit: 17 Receiver Enable */ 395 uint32_t :14; /*!< bit: 18..31 Reserved */ 396 } bit; /*!< Structure used for bit access */ 397 uint32_t reg; /*!< Type used for register access */ 398 } SERCOM_USART_CTRLB_Type; 399 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 400 401 #define SERCOM_USART_CTRLB_OFFSET 0x04 /**< \brief (SERCOM_USART_CTRLB offset) USART Control B */ 402 #define SERCOM_USART_CTRLB_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_USART_CTRLB reset_value) USART Control B */ 403 404 #define SERCOM_USART_CTRLB_CHSIZE_Pos 0 /**< \brief (SERCOM_USART_CTRLB) Character Size */ 405 #define SERCOM_USART_CTRLB_CHSIZE_Msk (_U(0x7) << SERCOM_USART_CTRLB_CHSIZE_Pos) 406 #define SERCOM_USART_CTRLB_CHSIZE(value) (SERCOM_USART_CTRLB_CHSIZE_Msk & ((value) << SERCOM_USART_CTRLB_CHSIZE_Pos)) 407 #define SERCOM_USART_CTRLB_SBMODE_Pos 6 /**< \brief (SERCOM_USART_CTRLB) Stop Bit Mode */ 408 #define SERCOM_USART_CTRLB_SBMODE (_U(0x1) << SERCOM_USART_CTRLB_SBMODE_Pos) 409 #define SERCOM_USART_CTRLB_COLDEN_Pos 8 /**< \brief (SERCOM_USART_CTRLB) Collision Detection Enable */ 410 #define SERCOM_USART_CTRLB_COLDEN (_U(0x1) << SERCOM_USART_CTRLB_COLDEN_Pos) 411 #define SERCOM_USART_CTRLB_SFDE_Pos 9 /**< \brief (SERCOM_USART_CTRLB) Start of Frame Detection Enable */ 412 #define SERCOM_USART_CTRLB_SFDE (_U(0x1) << SERCOM_USART_CTRLB_SFDE_Pos) 413 #define SERCOM_USART_CTRLB_ENC_Pos 10 /**< \brief (SERCOM_USART_CTRLB) Encoding Format */ 414 #define SERCOM_USART_CTRLB_ENC (_U(0x1) << SERCOM_USART_CTRLB_ENC_Pos) 415 #define SERCOM_USART_CTRLB_PMODE_Pos 13 /**< \brief (SERCOM_USART_CTRLB) Parity Mode */ 416 #define SERCOM_USART_CTRLB_PMODE (_U(0x1) << SERCOM_USART_CTRLB_PMODE_Pos) 417 #define SERCOM_USART_CTRLB_TXEN_Pos 16 /**< \brief (SERCOM_USART_CTRLB) Transmitter Enable */ 418 #define SERCOM_USART_CTRLB_TXEN (_U(0x1) << SERCOM_USART_CTRLB_TXEN_Pos) 419 #define SERCOM_USART_CTRLB_RXEN_Pos 17 /**< \brief (SERCOM_USART_CTRLB) Receiver Enable */ 420 #define SERCOM_USART_CTRLB_RXEN (_U(0x1) << SERCOM_USART_CTRLB_RXEN_Pos) 421 #define SERCOM_USART_CTRLB_MASK _U(0x00032747) /**< \brief (SERCOM_USART_CTRLB) MASK Register */ 422 423 /* -------- SERCOM_I2CM_BAUD : (SERCOM Offset: 0x0C) (R/W 32) I2CM I2CM Baud Rate -------- */ 424 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 425 typedef union { 426 struct { 427 uint32_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ 428 uint32_t BAUDLOW:8; /*!< bit: 8..15 Baud Rate Value Low */ 429 uint32_t HSBAUD:8; /*!< bit: 16..23 High Speed Baud Rate Value */ 430 uint32_t HSBAUDLOW:8; /*!< bit: 24..31 High Speed Baud Rate Value Low */ 431 } bit; /*!< Structure used for bit access */ 432 uint32_t reg; /*!< Type used for register access */ 433 } SERCOM_I2CM_BAUD_Type; 434 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 435 436 #define SERCOM_I2CM_BAUD_OFFSET 0x0C /**< \brief (SERCOM_I2CM_BAUD offset) I2CM Baud Rate */ 437 #define SERCOM_I2CM_BAUD_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_BAUD reset_value) I2CM Baud Rate */ 438 439 #define SERCOM_I2CM_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value */ 440 #define SERCOM_I2CM_BAUD_BAUD_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_BAUD_Pos) 441 #define SERCOM_I2CM_BAUD_BAUD(value) (SERCOM_I2CM_BAUD_BAUD_Msk & ((value) << SERCOM_I2CM_BAUD_BAUD_Pos)) 442 #define SERCOM_I2CM_BAUD_BAUDLOW_Pos 8 /**< \brief (SERCOM_I2CM_BAUD) Baud Rate Value Low */ 443 #define SERCOM_I2CM_BAUD_BAUDLOW_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_BAUDLOW_Pos) 444 #define SERCOM_I2CM_BAUD_BAUDLOW(value) (SERCOM_I2CM_BAUD_BAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_BAUDLOW_Pos)) 445 #define SERCOM_I2CM_BAUD_HSBAUD_Pos 16 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value */ 446 #define SERCOM_I2CM_BAUD_HSBAUD_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_HSBAUD_Pos) 447 #define SERCOM_I2CM_BAUD_HSBAUD(value) (SERCOM_I2CM_BAUD_HSBAUD_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUD_Pos)) 448 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Pos 24 /**< \brief (SERCOM_I2CM_BAUD) High Speed Baud Rate Value Low */ 449 #define SERCOM_I2CM_BAUD_HSBAUDLOW_Msk (_U(0xFF) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos) 450 #define SERCOM_I2CM_BAUD_HSBAUDLOW(value) (SERCOM_I2CM_BAUD_HSBAUDLOW_Msk & ((value) << SERCOM_I2CM_BAUD_HSBAUDLOW_Pos)) 451 #define SERCOM_I2CM_BAUD_MASK _U(0xFFFFFFFF) /**< \brief (SERCOM_I2CM_BAUD) MASK Register */ 452 453 /* -------- SERCOM_SPI_BAUD : (SERCOM Offset: 0x0C) (R/W 8) SPI SPI Baud Rate -------- */ 454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 455 typedef union { 456 struct { 457 uint8_t BAUD:8; /*!< bit: 0.. 7 Baud Rate Value */ 458 } bit; /*!< Structure used for bit access */ 459 uint8_t reg; /*!< Type used for register access */ 460 } SERCOM_SPI_BAUD_Type; 461 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 462 463 #define SERCOM_SPI_BAUD_OFFSET 0x0C /**< \brief (SERCOM_SPI_BAUD offset) SPI Baud Rate */ 464 #define SERCOM_SPI_BAUD_RESETVALUE _U(0x00) /**< \brief (SERCOM_SPI_BAUD reset_value) SPI Baud Rate */ 465 466 #define SERCOM_SPI_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_SPI_BAUD) Baud Rate Value */ 467 #define SERCOM_SPI_BAUD_BAUD_Msk (_U(0xFF) << SERCOM_SPI_BAUD_BAUD_Pos) 468 #define SERCOM_SPI_BAUD_BAUD(value) (SERCOM_SPI_BAUD_BAUD_Msk & ((value) << SERCOM_SPI_BAUD_BAUD_Pos)) 469 #define SERCOM_SPI_BAUD_MASK _U(0xFF) /**< \brief (SERCOM_SPI_BAUD) MASK Register */ 470 471 /* -------- SERCOM_USART_BAUD : (SERCOM Offset: 0x0C) (R/W 16) USART USART Baud Rate -------- */ 472 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 473 typedef union { 474 struct { 475 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ 476 } bit; /*!< Structure used for bit access */ 477 struct { // FRAC mode 478 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ 479 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ 480 } FRAC; /*!< Structure used for FRAC */ 481 struct { // FRACFP mode 482 uint16_t BAUD:13; /*!< bit: 0..12 Baud Rate Value */ 483 uint16_t FP:3; /*!< bit: 13..15 Fractional Part */ 484 } FRACFP; /*!< Structure used for FRACFP */ 485 struct { // USARTFP mode 486 uint16_t BAUD:16; /*!< bit: 0..15 Baud Rate Value */ 487 } USARTFP; /*!< Structure used for USARTFP */ 488 uint16_t reg; /*!< Type used for register access */ 489 } SERCOM_USART_BAUD_Type; 490 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 491 492 #define SERCOM_USART_BAUD_OFFSET 0x0C /**< \brief (SERCOM_USART_BAUD offset) USART Baud Rate */ 493 #define SERCOM_USART_BAUD_RESETVALUE _U(0x0000) /**< \brief (SERCOM_USART_BAUD reset_value) USART Baud Rate */ 494 495 #define SERCOM_USART_BAUD_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD) Baud Rate Value */ 496 #define SERCOM_USART_BAUD_BAUD_Msk (_U(0xFFFF) << SERCOM_USART_BAUD_BAUD_Pos) 497 #define SERCOM_USART_BAUD_BAUD(value) (SERCOM_USART_BAUD_BAUD_Msk & ((value) << SERCOM_USART_BAUD_BAUD_Pos)) 498 #define SERCOM_USART_BAUD_MASK _U(0xFFFF) /**< \brief (SERCOM_USART_BAUD) MASK Register */ 499 500 // FRAC mode 501 #define SERCOM_USART_BAUD_FRAC_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRAC) Baud Rate Value */ 502 #define SERCOM_USART_BAUD_FRAC_BAUD_Msk (_U(0x1FFF) << SERCOM_USART_BAUD_FRAC_BAUD_Pos) 503 #define SERCOM_USART_BAUD_FRAC_BAUD(value) (SERCOM_USART_BAUD_FRAC_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRAC_BAUD_Pos)) 504 #define SERCOM_USART_BAUD_FRAC_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRAC) Fractional Part */ 505 #define SERCOM_USART_BAUD_FRAC_FP_Msk (_U(0x7) << SERCOM_USART_BAUD_FRAC_FP_Pos) 506 #define SERCOM_USART_BAUD_FRAC_FP(value) (SERCOM_USART_BAUD_FRAC_FP_Msk & ((value) << SERCOM_USART_BAUD_FRAC_FP_Pos)) 507 #define SERCOM_USART_BAUD_FRAC_MASK _U(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRAC) MASK Register */ 508 509 // FRACFP mode 510 #define SERCOM_USART_BAUD_FRACFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_FRACFP) Baud Rate Value */ 511 #define SERCOM_USART_BAUD_FRACFP_BAUD_Msk (_U(0x1FFF) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos) 512 #define SERCOM_USART_BAUD_FRACFP_BAUD(value) (SERCOM_USART_BAUD_FRACFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_BAUD_Pos)) 513 #define SERCOM_USART_BAUD_FRACFP_FP_Pos 13 /**< \brief (SERCOM_USART_BAUD_FRACFP) Fractional Part */ 514 #define SERCOM_USART_BAUD_FRACFP_FP_Msk (_U(0x7) << SERCOM_USART_BAUD_FRACFP_FP_Pos) 515 #define SERCOM_USART_BAUD_FRACFP_FP(value) (SERCOM_USART_BAUD_FRACFP_FP_Msk & ((value) << SERCOM_USART_BAUD_FRACFP_FP_Pos)) 516 #define SERCOM_USART_BAUD_FRACFP_MASK _U(0xFFFF) /**< \brief (SERCOM_USART_BAUD_FRACFP) MASK Register */ 517 518 // USARTFP mode 519 #define SERCOM_USART_BAUD_USARTFP_BAUD_Pos 0 /**< \brief (SERCOM_USART_BAUD_USARTFP) Baud Rate Value */ 520 #define SERCOM_USART_BAUD_USARTFP_BAUD_Msk (_U(0xFFFF) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos) 521 #define SERCOM_USART_BAUD_USARTFP_BAUD(value) (SERCOM_USART_BAUD_USARTFP_BAUD_Msk & ((value) << SERCOM_USART_BAUD_USARTFP_BAUD_Pos)) 522 #define SERCOM_USART_BAUD_USARTFP_MASK _U(0xFFFF) /**< \brief (SERCOM_USART_BAUD_USARTFP) MASK Register */ 523 524 /* -------- SERCOM_USART_RXPL : (SERCOM Offset: 0x0E) (R/W 8) USART USART Receive Pulse Length -------- */ 525 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 526 typedef union { 527 struct { 528 uint8_t RXPL:8; /*!< bit: 0.. 7 Receive Pulse Length */ 529 } bit; /*!< Structure used for bit access */ 530 uint8_t reg; /*!< Type used for register access */ 531 } SERCOM_USART_RXPL_Type; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 #define SERCOM_USART_RXPL_OFFSET 0x0E /**< \brief (SERCOM_USART_RXPL offset) USART Receive Pulse Length */ 535 #define SERCOM_USART_RXPL_RESETVALUE _U(0x00) /**< \brief (SERCOM_USART_RXPL reset_value) USART Receive Pulse Length */ 536 537 #define SERCOM_USART_RXPL_RXPL_Pos 0 /**< \brief (SERCOM_USART_RXPL) Receive Pulse Length */ 538 #define SERCOM_USART_RXPL_RXPL_Msk (_U(0xFF) << SERCOM_USART_RXPL_RXPL_Pos) 539 #define SERCOM_USART_RXPL_RXPL(value) (SERCOM_USART_RXPL_RXPL_Msk & ((value) << SERCOM_USART_RXPL_RXPL_Pos)) 540 #define SERCOM_USART_RXPL_MASK _U(0xFF) /**< \brief (SERCOM_USART_RXPL) MASK Register */ 541 542 /* -------- SERCOM_I2CM_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CM I2CM Interrupt Enable Clear -------- */ 543 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 544 typedef union { 545 struct { 546 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Disable */ 547 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Disable */ 548 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 549 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 550 } bit; /*!< Structure used for bit access */ 551 uint8_t reg; /*!< Type used for register access */ 552 } SERCOM_I2CM_INTENCLR_Type; 553 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 554 555 #define SERCOM_I2CM_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CM_INTENCLR offset) I2CM Interrupt Enable Clear */ 556 #define SERCOM_I2CM_INTENCLR_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CM_INTENCLR reset_value) I2CM Interrupt Enable Clear */ 557 558 #define SERCOM_I2CM_INTENCLR_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENCLR) Master On Bus Interrupt Disable */ 559 #define SERCOM_I2CM_INTENCLR_MB (_U(0x1) << SERCOM_I2CM_INTENCLR_MB_Pos) 560 #define SERCOM_I2CM_INTENCLR_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENCLR) Slave On Bus Interrupt Disable */ 561 #define SERCOM_I2CM_INTENCLR_SB (_U(0x1) << SERCOM_I2CM_INTENCLR_SB_Pos) 562 #define SERCOM_I2CM_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENCLR) Combined Error Interrupt Disable */ 563 #define SERCOM_I2CM_INTENCLR_ERROR (_U(0x1) << SERCOM_I2CM_INTENCLR_ERROR_Pos) 564 #define SERCOM_I2CM_INTENCLR_MASK _U(0x83) /**< \brief (SERCOM_I2CM_INTENCLR) MASK Register */ 565 566 /* -------- SERCOM_I2CS_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) I2CS I2CS Interrupt Enable Clear -------- */ 567 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 568 typedef union { 569 struct { 570 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Disable */ 571 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Disable */ 572 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Disable */ 573 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 574 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 575 } bit; /*!< Structure used for bit access */ 576 uint8_t reg; /*!< Type used for register access */ 577 } SERCOM_I2CS_INTENCLR_Type; 578 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 579 580 #define SERCOM_I2CS_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_I2CS_INTENCLR offset) I2CS Interrupt Enable Clear */ 581 #define SERCOM_I2CS_INTENCLR_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CS_INTENCLR reset_value) I2CS Interrupt Enable Clear */ 582 583 #define SERCOM_I2CS_INTENCLR_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENCLR) Stop Received Interrupt Disable */ 584 #define SERCOM_I2CS_INTENCLR_PREC (_U(0x1) << SERCOM_I2CS_INTENCLR_PREC_Pos) 585 #define SERCOM_I2CS_INTENCLR_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENCLR) Address Match Interrupt Disable */ 586 #define SERCOM_I2CS_INTENCLR_AMATCH (_U(0x1) << SERCOM_I2CS_INTENCLR_AMATCH_Pos) 587 #define SERCOM_I2CS_INTENCLR_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENCLR) Data Interrupt Disable */ 588 #define SERCOM_I2CS_INTENCLR_DRDY (_U(0x1) << SERCOM_I2CS_INTENCLR_DRDY_Pos) 589 #define SERCOM_I2CS_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENCLR) Combined Error Interrupt Disable */ 590 #define SERCOM_I2CS_INTENCLR_ERROR (_U(0x1) << SERCOM_I2CS_INTENCLR_ERROR_Pos) 591 #define SERCOM_I2CS_INTENCLR_MASK _U(0x87) /**< \brief (SERCOM_I2CS_INTENCLR) MASK Register */ 592 593 /* -------- SERCOM_SPI_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) SPI SPI Interrupt Enable Clear -------- */ 594 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 595 typedef union { 596 struct { 597 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ 598 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ 599 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ 600 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Disable */ 601 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 602 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 603 } bit; /*!< Structure used for bit access */ 604 uint8_t reg; /*!< Type used for register access */ 605 } SERCOM_SPI_INTENCLR_Type; 606 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 607 608 #define SERCOM_SPI_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_SPI_INTENCLR offset) SPI Interrupt Enable Clear */ 609 #define SERCOM_SPI_INTENCLR_RESETVALUE _U(0x00) /**< \brief (SERCOM_SPI_INTENCLR reset_value) SPI Interrupt Enable Clear */ 610 611 #define SERCOM_SPI_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENCLR) Data Register Empty Interrupt Disable */ 612 #define SERCOM_SPI_INTENCLR_DRE (_U(0x1) << SERCOM_SPI_INTENCLR_DRE_Pos) 613 #define SERCOM_SPI_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENCLR) Transmit Complete Interrupt Disable */ 614 #define SERCOM_SPI_INTENCLR_TXC (_U(0x1) << SERCOM_SPI_INTENCLR_TXC_Pos) 615 #define SERCOM_SPI_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENCLR) Receive Complete Interrupt Disable */ 616 #define SERCOM_SPI_INTENCLR_RXC (_U(0x1) << SERCOM_SPI_INTENCLR_RXC_Pos) 617 #define SERCOM_SPI_INTENCLR_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENCLR) Slave Select Low Interrupt Disable */ 618 #define SERCOM_SPI_INTENCLR_SSL (_U(0x1) << SERCOM_SPI_INTENCLR_SSL_Pos) 619 #define SERCOM_SPI_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENCLR) Combined Error Interrupt Disable */ 620 #define SERCOM_SPI_INTENCLR_ERROR (_U(0x1) << SERCOM_SPI_INTENCLR_ERROR_Pos) 621 #define SERCOM_SPI_INTENCLR_MASK _U(0x8F) /**< \brief (SERCOM_SPI_INTENCLR) MASK Register */ 622 623 /* -------- SERCOM_USART_INTENCLR : (SERCOM Offset: 0x14) (R/W 8) USART USART Interrupt Enable Clear -------- */ 624 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 625 typedef union { 626 struct { 627 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Disable */ 628 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Disable */ 629 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Disable */ 630 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Disable */ 631 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Disable */ 632 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Disable */ 633 uint8_t :1; /*!< bit: 6 Reserved */ 634 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Disable */ 635 } bit; /*!< Structure used for bit access */ 636 uint8_t reg; /*!< Type used for register access */ 637 } SERCOM_USART_INTENCLR_Type; 638 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 639 640 #define SERCOM_USART_INTENCLR_OFFSET 0x14 /**< \brief (SERCOM_USART_INTENCLR offset) USART Interrupt Enable Clear */ 641 #define SERCOM_USART_INTENCLR_RESETVALUE _U(0x00) /**< \brief (SERCOM_USART_INTENCLR reset_value) USART Interrupt Enable Clear */ 642 643 #define SERCOM_USART_INTENCLR_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENCLR) Data Register Empty Interrupt Disable */ 644 #define SERCOM_USART_INTENCLR_DRE (_U(0x1) << SERCOM_USART_INTENCLR_DRE_Pos) 645 #define SERCOM_USART_INTENCLR_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENCLR) Transmit Complete Interrupt Disable */ 646 #define SERCOM_USART_INTENCLR_TXC (_U(0x1) << SERCOM_USART_INTENCLR_TXC_Pos) 647 #define SERCOM_USART_INTENCLR_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENCLR) Receive Complete Interrupt Disable */ 648 #define SERCOM_USART_INTENCLR_RXC (_U(0x1) << SERCOM_USART_INTENCLR_RXC_Pos) 649 #define SERCOM_USART_INTENCLR_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENCLR) Receive Start Interrupt Disable */ 650 #define SERCOM_USART_INTENCLR_RXS (_U(0x1) << SERCOM_USART_INTENCLR_RXS_Pos) 651 #define SERCOM_USART_INTENCLR_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENCLR) Clear To Send Input Change Interrupt Disable */ 652 #define SERCOM_USART_INTENCLR_CTSIC (_U(0x1) << SERCOM_USART_INTENCLR_CTSIC_Pos) 653 #define SERCOM_USART_INTENCLR_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENCLR) Break Received Interrupt Disable */ 654 #define SERCOM_USART_INTENCLR_RXBRK (_U(0x1) << SERCOM_USART_INTENCLR_RXBRK_Pos) 655 #define SERCOM_USART_INTENCLR_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENCLR) Combined Error Interrupt Disable */ 656 #define SERCOM_USART_INTENCLR_ERROR (_U(0x1) << SERCOM_USART_INTENCLR_ERROR_Pos) 657 #define SERCOM_USART_INTENCLR_MASK _U(0xBF) /**< \brief (SERCOM_USART_INTENCLR) MASK Register */ 658 659 /* -------- SERCOM_I2CM_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CM I2CM Interrupt Enable Set -------- */ 660 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 661 typedef union { 662 struct { 663 uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt Enable */ 664 uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt Enable */ 665 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 666 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 667 } bit; /*!< Structure used for bit access */ 668 uint8_t reg; /*!< Type used for register access */ 669 } SERCOM_I2CM_INTENSET_Type; 670 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 671 672 #define SERCOM_I2CM_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CM_INTENSET offset) I2CM Interrupt Enable Set */ 673 #define SERCOM_I2CM_INTENSET_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CM_INTENSET reset_value) I2CM Interrupt Enable Set */ 674 675 #define SERCOM_I2CM_INTENSET_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTENSET) Master On Bus Interrupt Enable */ 676 #define SERCOM_I2CM_INTENSET_MB (_U(0x1) << SERCOM_I2CM_INTENSET_MB_Pos) 677 #define SERCOM_I2CM_INTENSET_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTENSET) Slave On Bus Interrupt Enable */ 678 #define SERCOM_I2CM_INTENSET_SB (_U(0x1) << SERCOM_I2CM_INTENSET_SB_Pos) 679 #define SERCOM_I2CM_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTENSET) Combined Error Interrupt Enable */ 680 #define SERCOM_I2CM_INTENSET_ERROR (_U(0x1) << SERCOM_I2CM_INTENSET_ERROR_Pos) 681 #define SERCOM_I2CM_INTENSET_MASK _U(0x83) /**< \brief (SERCOM_I2CM_INTENSET) MASK Register */ 682 683 /* -------- SERCOM_I2CS_INTENSET : (SERCOM Offset: 0x16) (R/W 8) I2CS I2CS Interrupt Enable Set -------- */ 684 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 685 typedef union { 686 struct { 687 uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt Enable */ 688 uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt Enable */ 689 uint8_t DRDY:1; /*!< bit: 2 Data Interrupt Enable */ 690 uint8_t :4; /*!< bit: 3.. 6 Reserved */ 691 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 692 } bit; /*!< Structure used for bit access */ 693 uint8_t reg; /*!< Type used for register access */ 694 } SERCOM_I2CS_INTENSET_Type; 695 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 696 697 #define SERCOM_I2CS_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_I2CS_INTENSET offset) I2CS Interrupt Enable Set */ 698 #define SERCOM_I2CS_INTENSET_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CS_INTENSET reset_value) I2CS Interrupt Enable Set */ 699 700 #define SERCOM_I2CS_INTENSET_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTENSET) Stop Received Interrupt Enable */ 701 #define SERCOM_I2CS_INTENSET_PREC (_U(0x1) << SERCOM_I2CS_INTENSET_PREC_Pos) 702 #define SERCOM_I2CS_INTENSET_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTENSET) Address Match Interrupt Enable */ 703 #define SERCOM_I2CS_INTENSET_AMATCH (_U(0x1) << SERCOM_I2CS_INTENSET_AMATCH_Pos) 704 #define SERCOM_I2CS_INTENSET_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTENSET) Data Interrupt Enable */ 705 #define SERCOM_I2CS_INTENSET_DRDY (_U(0x1) << SERCOM_I2CS_INTENSET_DRDY_Pos) 706 #define SERCOM_I2CS_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTENSET) Combined Error Interrupt Enable */ 707 #define SERCOM_I2CS_INTENSET_ERROR (_U(0x1) << SERCOM_I2CS_INTENSET_ERROR_Pos) 708 #define SERCOM_I2CS_INTENSET_MASK _U(0x87) /**< \brief (SERCOM_I2CS_INTENSET) MASK Register */ 709 710 /* -------- SERCOM_SPI_INTENSET : (SERCOM Offset: 0x16) (R/W 8) SPI SPI Interrupt Enable Set -------- */ 711 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 712 typedef union { 713 struct { 714 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 715 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 716 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 717 uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Enable */ 718 uint8_t :3; /*!< bit: 4.. 6 Reserved */ 719 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 720 } bit; /*!< Structure used for bit access */ 721 uint8_t reg; /*!< Type used for register access */ 722 } SERCOM_SPI_INTENSET_Type; 723 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 724 725 #define SERCOM_SPI_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_SPI_INTENSET offset) SPI Interrupt Enable Set */ 726 #define SERCOM_SPI_INTENSET_RESETVALUE _U(0x00) /**< \brief (SERCOM_SPI_INTENSET reset_value) SPI Interrupt Enable Set */ 727 728 #define SERCOM_SPI_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTENSET) Data Register Empty Interrupt Enable */ 729 #define SERCOM_SPI_INTENSET_DRE (_U(0x1) << SERCOM_SPI_INTENSET_DRE_Pos) 730 #define SERCOM_SPI_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTENSET) Transmit Complete Interrupt Enable */ 731 #define SERCOM_SPI_INTENSET_TXC (_U(0x1) << SERCOM_SPI_INTENSET_TXC_Pos) 732 #define SERCOM_SPI_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTENSET) Receive Complete Interrupt Enable */ 733 #define SERCOM_SPI_INTENSET_RXC (_U(0x1) << SERCOM_SPI_INTENSET_RXC_Pos) 734 #define SERCOM_SPI_INTENSET_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTENSET) Slave Select Low Interrupt Enable */ 735 #define SERCOM_SPI_INTENSET_SSL (_U(0x1) << SERCOM_SPI_INTENSET_SSL_Pos) 736 #define SERCOM_SPI_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTENSET) Combined Error Interrupt Enable */ 737 #define SERCOM_SPI_INTENSET_ERROR (_U(0x1) << SERCOM_SPI_INTENSET_ERROR_Pos) 738 #define SERCOM_SPI_INTENSET_MASK _U(0x8F) /**< \brief (SERCOM_SPI_INTENSET) MASK Register */ 739 740 /* -------- SERCOM_USART_INTENSET : (SERCOM Offset: 0x16) (R/W 8) USART USART Interrupt Enable Set -------- */ 741 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 742 typedef union { 743 struct { 744 uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt Enable */ 745 uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt Enable */ 746 uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt Enable */ 747 uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt Enable */ 748 uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt Enable */ 749 uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt Enable */ 750 uint8_t :1; /*!< bit: 6 Reserved */ 751 uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt Enable */ 752 } bit; /*!< Structure used for bit access */ 753 uint8_t reg; /*!< Type used for register access */ 754 } SERCOM_USART_INTENSET_Type; 755 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 756 757 #define SERCOM_USART_INTENSET_OFFSET 0x16 /**< \brief (SERCOM_USART_INTENSET offset) USART Interrupt Enable Set */ 758 #define SERCOM_USART_INTENSET_RESETVALUE _U(0x00) /**< \brief (SERCOM_USART_INTENSET reset_value) USART Interrupt Enable Set */ 759 760 #define SERCOM_USART_INTENSET_DRE_Pos 0 /**< \brief (SERCOM_USART_INTENSET) Data Register Empty Interrupt Enable */ 761 #define SERCOM_USART_INTENSET_DRE (_U(0x1) << SERCOM_USART_INTENSET_DRE_Pos) 762 #define SERCOM_USART_INTENSET_TXC_Pos 1 /**< \brief (SERCOM_USART_INTENSET) Transmit Complete Interrupt Enable */ 763 #define SERCOM_USART_INTENSET_TXC (_U(0x1) << SERCOM_USART_INTENSET_TXC_Pos) 764 #define SERCOM_USART_INTENSET_RXC_Pos 2 /**< \brief (SERCOM_USART_INTENSET) Receive Complete Interrupt Enable */ 765 #define SERCOM_USART_INTENSET_RXC (_U(0x1) << SERCOM_USART_INTENSET_RXC_Pos) 766 #define SERCOM_USART_INTENSET_RXS_Pos 3 /**< \brief (SERCOM_USART_INTENSET) Receive Start Interrupt Enable */ 767 #define SERCOM_USART_INTENSET_RXS (_U(0x1) << SERCOM_USART_INTENSET_RXS_Pos) 768 #define SERCOM_USART_INTENSET_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTENSET) Clear To Send Input Change Interrupt Enable */ 769 #define SERCOM_USART_INTENSET_CTSIC (_U(0x1) << SERCOM_USART_INTENSET_CTSIC_Pos) 770 #define SERCOM_USART_INTENSET_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTENSET) Break Received Interrupt Enable */ 771 #define SERCOM_USART_INTENSET_RXBRK (_U(0x1) << SERCOM_USART_INTENSET_RXBRK_Pos) 772 #define SERCOM_USART_INTENSET_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTENSET) Combined Error Interrupt Enable */ 773 #define SERCOM_USART_INTENSET_ERROR (_U(0x1) << SERCOM_USART_INTENSET_ERROR_Pos) 774 #define SERCOM_USART_INTENSET_MASK _U(0xBF) /**< \brief (SERCOM_USART_INTENSET) MASK Register */ 775 776 /* -------- SERCOM_I2CM_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CM I2CM Interrupt Flag Status and Clear -------- */ 777 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 778 typedef union { // __I to avoid read-modify-write on write-to-clear register 779 struct { 780 __I uint8_t MB:1; /*!< bit: 0 Master On Bus Interrupt */ 781 __I uint8_t SB:1; /*!< bit: 1 Slave On Bus Interrupt */ 782 __I uint8_t :5; /*!< bit: 2.. 6 Reserved */ 783 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 784 } bit; /*!< Structure used for bit access */ 785 uint8_t reg; /*!< Type used for register access */ 786 } SERCOM_I2CM_INTFLAG_Type; 787 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 788 789 #define SERCOM_I2CM_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CM_INTFLAG offset) I2CM Interrupt Flag Status and Clear */ 790 #define SERCOM_I2CM_INTFLAG_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CM_INTFLAG reset_value) I2CM Interrupt Flag Status and Clear */ 791 792 #define SERCOM_I2CM_INTFLAG_MB_Pos 0 /**< \brief (SERCOM_I2CM_INTFLAG) Master On Bus Interrupt */ 793 #define SERCOM_I2CM_INTFLAG_MB (_U(0x1) << SERCOM_I2CM_INTFLAG_MB_Pos) 794 #define SERCOM_I2CM_INTFLAG_SB_Pos 1 /**< \brief (SERCOM_I2CM_INTFLAG) Slave On Bus Interrupt */ 795 #define SERCOM_I2CM_INTFLAG_SB (_U(0x1) << SERCOM_I2CM_INTFLAG_SB_Pos) 796 #define SERCOM_I2CM_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CM_INTFLAG) Combined Error Interrupt */ 797 #define SERCOM_I2CM_INTFLAG_ERROR (_U(0x1) << SERCOM_I2CM_INTFLAG_ERROR_Pos) 798 #define SERCOM_I2CM_INTFLAG_MASK _U(0x83) /**< \brief (SERCOM_I2CM_INTFLAG) MASK Register */ 799 800 /* -------- SERCOM_I2CS_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) I2CS I2CS Interrupt Flag Status and Clear -------- */ 801 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 802 typedef union { // __I to avoid read-modify-write on write-to-clear register 803 struct { 804 __I uint8_t PREC:1; /*!< bit: 0 Stop Received Interrupt */ 805 __I uint8_t AMATCH:1; /*!< bit: 1 Address Match Interrupt */ 806 __I uint8_t DRDY:1; /*!< bit: 2 Data Interrupt */ 807 __I uint8_t :4; /*!< bit: 3.. 6 Reserved */ 808 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 809 } bit; /*!< Structure used for bit access */ 810 uint8_t reg; /*!< Type used for register access */ 811 } SERCOM_I2CS_INTFLAG_Type; 812 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 813 814 #define SERCOM_I2CS_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_I2CS_INTFLAG offset) I2CS Interrupt Flag Status and Clear */ 815 #define SERCOM_I2CS_INTFLAG_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CS_INTFLAG reset_value) I2CS Interrupt Flag Status and Clear */ 816 817 #define SERCOM_I2CS_INTFLAG_PREC_Pos 0 /**< \brief (SERCOM_I2CS_INTFLAG) Stop Received Interrupt */ 818 #define SERCOM_I2CS_INTFLAG_PREC (_U(0x1) << SERCOM_I2CS_INTFLAG_PREC_Pos) 819 #define SERCOM_I2CS_INTFLAG_AMATCH_Pos 1 /**< \brief (SERCOM_I2CS_INTFLAG) Address Match Interrupt */ 820 #define SERCOM_I2CS_INTFLAG_AMATCH (_U(0x1) << SERCOM_I2CS_INTFLAG_AMATCH_Pos) 821 #define SERCOM_I2CS_INTFLAG_DRDY_Pos 2 /**< \brief (SERCOM_I2CS_INTFLAG) Data Interrupt */ 822 #define SERCOM_I2CS_INTFLAG_DRDY (_U(0x1) << SERCOM_I2CS_INTFLAG_DRDY_Pos) 823 #define SERCOM_I2CS_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_I2CS_INTFLAG) Combined Error Interrupt */ 824 #define SERCOM_I2CS_INTFLAG_ERROR (_U(0x1) << SERCOM_I2CS_INTFLAG_ERROR_Pos) 825 #define SERCOM_I2CS_INTFLAG_MASK _U(0x87) /**< \brief (SERCOM_I2CS_INTFLAG) MASK Register */ 826 827 /* -------- SERCOM_SPI_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) SPI SPI Interrupt Flag Status and Clear -------- */ 828 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 829 typedef union { // __I to avoid read-modify-write on write-to-clear register 830 struct { 831 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ 832 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ 833 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ 834 __I uint8_t SSL:1; /*!< bit: 3 Slave Select Low Interrupt Flag */ 835 __I uint8_t :3; /*!< bit: 4.. 6 Reserved */ 836 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 837 } bit; /*!< Structure used for bit access */ 838 uint8_t reg; /*!< Type used for register access */ 839 } SERCOM_SPI_INTFLAG_Type; 840 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 841 842 #define SERCOM_SPI_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_SPI_INTFLAG offset) SPI Interrupt Flag Status and Clear */ 843 #define SERCOM_SPI_INTFLAG_RESETVALUE _U(0x00) /**< \brief (SERCOM_SPI_INTFLAG reset_value) SPI Interrupt Flag Status and Clear */ 844 845 #define SERCOM_SPI_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_SPI_INTFLAG) Data Register Empty Interrupt */ 846 #define SERCOM_SPI_INTFLAG_DRE (_U(0x1) << SERCOM_SPI_INTFLAG_DRE_Pos) 847 #define SERCOM_SPI_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_SPI_INTFLAG) Transmit Complete Interrupt */ 848 #define SERCOM_SPI_INTFLAG_TXC (_U(0x1) << SERCOM_SPI_INTFLAG_TXC_Pos) 849 #define SERCOM_SPI_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_SPI_INTFLAG) Receive Complete Interrupt */ 850 #define SERCOM_SPI_INTFLAG_RXC (_U(0x1) << SERCOM_SPI_INTFLAG_RXC_Pos) 851 #define SERCOM_SPI_INTFLAG_SSL_Pos 3 /**< \brief (SERCOM_SPI_INTFLAG) Slave Select Low Interrupt Flag */ 852 #define SERCOM_SPI_INTFLAG_SSL (_U(0x1) << SERCOM_SPI_INTFLAG_SSL_Pos) 853 #define SERCOM_SPI_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_SPI_INTFLAG) Combined Error Interrupt */ 854 #define SERCOM_SPI_INTFLAG_ERROR (_U(0x1) << SERCOM_SPI_INTFLAG_ERROR_Pos) 855 #define SERCOM_SPI_INTFLAG_MASK _U(0x8F) /**< \brief (SERCOM_SPI_INTFLAG) MASK Register */ 856 857 /* -------- SERCOM_USART_INTFLAG : (SERCOM Offset: 0x18) (R/W 8) USART USART Interrupt Flag Status and Clear -------- */ 858 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 859 typedef union { // __I to avoid read-modify-write on write-to-clear register 860 struct { 861 __I uint8_t DRE:1; /*!< bit: 0 Data Register Empty Interrupt */ 862 __I uint8_t TXC:1; /*!< bit: 1 Transmit Complete Interrupt */ 863 __I uint8_t RXC:1; /*!< bit: 2 Receive Complete Interrupt */ 864 __I uint8_t RXS:1; /*!< bit: 3 Receive Start Interrupt */ 865 __I uint8_t CTSIC:1; /*!< bit: 4 Clear To Send Input Change Interrupt */ 866 __I uint8_t RXBRK:1; /*!< bit: 5 Break Received Interrupt */ 867 __I uint8_t :1; /*!< bit: 6 Reserved */ 868 __I uint8_t ERROR:1; /*!< bit: 7 Combined Error Interrupt */ 869 } bit; /*!< Structure used for bit access */ 870 uint8_t reg; /*!< Type used for register access */ 871 } SERCOM_USART_INTFLAG_Type; 872 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 873 874 #define SERCOM_USART_INTFLAG_OFFSET 0x18 /**< \brief (SERCOM_USART_INTFLAG offset) USART Interrupt Flag Status and Clear */ 875 #define SERCOM_USART_INTFLAG_RESETVALUE _U(0x00) /**< \brief (SERCOM_USART_INTFLAG reset_value) USART Interrupt Flag Status and Clear */ 876 877 #define SERCOM_USART_INTFLAG_DRE_Pos 0 /**< \brief (SERCOM_USART_INTFLAG) Data Register Empty Interrupt */ 878 #define SERCOM_USART_INTFLAG_DRE (_U(0x1) << SERCOM_USART_INTFLAG_DRE_Pos) 879 #define SERCOM_USART_INTFLAG_TXC_Pos 1 /**< \brief (SERCOM_USART_INTFLAG) Transmit Complete Interrupt */ 880 #define SERCOM_USART_INTFLAG_TXC (_U(0x1) << SERCOM_USART_INTFLAG_TXC_Pos) 881 #define SERCOM_USART_INTFLAG_RXC_Pos 2 /**< \brief (SERCOM_USART_INTFLAG) Receive Complete Interrupt */ 882 #define SERCOM_USART_INTFLAG_RXC (_U(0x1) << SERCOM_USART_INTFLAG_RXC_Pos) 883 #define SERCOM_USART_INTFLAG_RXS_Pos 3 /**< \brief (SERCOM_USART_INTFLAG) Receive Start Interrupt */ 884 #define SERCOM_USART_INTFLAG_RXS (_U(0x1) << SERCOM_USART_INTFLAG_RXS_Pos) 885 #define SERCOM_USART_INTFLAG_CTSIC_Pos 4 /**< \brief (SERCOM_USART_INTFLAG) Clear To Send Input Change Interrupt */ 886 #define SERCOM_USART_INTFLAG_CTSIC (_U(0x1) << SERCOM_USART_INTFLAG_CTSIC_Pos) 887 #define SERCOM_USART_INTFLAG_RXBRK_Pos 5 /**< \brief (SERCOM_USART_INTFLAG) Break Received Interrupt */ 888 #define SERCOM_USART_INTFLAG_RXBRK (_U(0x1) << SERCOM_USART_INTFLAG_RXBRK_Pos) 889 #define SERCOM_USART_INTFLAG_ERROR_Pos 7 /**< \brief (SERCOM_USART_INTFLAG) Combined Error Interrupt */ 890 #define SERCOM_USART_INTFLAG_ERROR (_U(0x1) << SERCOM_USART_INTFLAG_ERROR_Pos) 891 #define SERCOM_USART_INTFLAG_MASK _U(0xBF) /**< \brief (SERCOM_USART_INTFLAG) MASK Register */ 892 893 /* -------- SERCOM_I2CM_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CM I2CM Status -------- */ 894 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 895 typedef union { 896 struct { 897 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 898 uint16_t ARBLOST:1; /*!< bit: 1 Arbitration Lost */ 899 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 900 uint16_t :1; /*!< bit: 3 Reserved */ 901 uint16_t BUSSTATE:2; /*!< bit: 4.. 5 Bus State */ 902 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ 903 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 904 uint16_t MEXTTOUT:1; /*!< bit: 8 Master SCL Low Extend Timeout */ 905 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ 906 uint16_t LENERR:1; /*!< bit: 10 Length Error */ 907 uint16_t :5; /*!< bit: 11..15 Reserved */ 908 } bit; /*!< Structure used for bit access */ 909 uint16_t reg; /*!< Type used for register access */ 910 } SERCOM_I2CM_STATUS_Type; 911 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 912 913 #define SERCOM_I2CM_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CM_STATUS offset) I2CM Status */ 914 #define SERCOM_I2CM_STATUS_RESETVALUE _U(0x0000) /**< \brief (SERCOM_I2CM_STATUS reset_value) I2CM Status */ 915 916 #define SERCOM_I2CM_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CM_STATUS) Bus Error */ 917 #define SERCOM_I2CM_STATUS_BUSERR (_U(0x1) << SERCOM_I2CM_STATUS_BUSERR_Pos) 918 #define SERCOM_I2CM_STATUS_ARBLOST_Pos 1 /**< \brief (SERCOM_I2CM_STATUS) Arbitration Lost */ 919 #define SERCOM_I2CM_STATUS_ARBLOST (_U(0x1) << SERCOM_I2CM_STATUS_ARBLOST_Pos) 920 #define SERCOM_I2CM_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CM_STATUS) Received Not Acknowledge */ 921 #define SERCOM_I2CM_STATUS_RXNACK (_U(0x1) << SERCOM_I2CM_STATUS_RXNACK_Pos) 922 #define SERCOM_I2CM_STATUS_BUSSTATE_Pos 4 /**< \brief (SERCOM_I2CM_STATUS) Bus State */ 923 #define SERCOM_I2CM_STATUS_BUSSTATE_Msk (_U(0x3) << SERCOM_I2CM_STATUS_BUSSTATE_Pos) 924 #define SERCOM_I2CM_STATUS_BUSSTATE(value) (SERCOM_I2CM_STATUS_BUSSTATE_Msk & ((value) << SERCOM_I2CM_STATUS_BUSSTATE_Pos)) 925 #define SERCOM_I2CM_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CM_STATUS) SCL Low Timeout */ 926 #define SERCOM_I2CM_STATUS_LOWTOUT (_U(0x1) << SERCOM_I2CM_STATUS_LOWTOUT_Pos) 927 #define SERCOM_I2CM_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CM_STATUS) Clock Hold */ 928 #define SERCOM_I2CM_STATUS_CLKHOLD (_U(0x1) << SERCOM_I2CM_STATUS_CLKHOLD_Pos) 929 #define SERCOM_I2CM_STATUS_MEXTTOUT_Pos 8 /**< \brief (SERCOM_I2CM_STATUS) Master SCL Low Extend Timeout */ 930 #define SERCOM_I2CM_STATUS_MEXTTOUT (_U(0x1) << SERCOM_I2CM_STATUS_MEXTTOUT_Pos) 931 #define SERCOM_I2CM_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CM_STATUS) Slave SCL Low Extend Timeout */ 932 #define SERCOM_I2CM_STATUS_SEXTTOUT (_U(0x1) << SERCOM_I2CM_STATUS_SEXTTOUT_Pos) 933 #define SERCOM_I2CM_STATUS_LENERR_Pos 10 /**< \brief (SERCOM_I2CM_STATUS) Length Error */ 934 #define SERCOM_I2CM_STATUS_LENERR (_U(0x1) << SERCOM_I2CM_STATUS_LENERR_Pos) 935 #define SERCOM_I2CM_STATUS_MASK _U(0x07F7) /**< \brief (SERCOM_I2CM_STATUS) MASK Register */ 936 937 /* -------- SERCOM_I2CS_STATUS : (SERCOM Offset: 0x1A) (R/W 16) I2CS I2CS Status -------- */ 938 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 939 typedef union { 940 struct { 941 uint16_t BUSERR:1; /*!< bit: 0 Bus Error */ 942 uint16_t COLL:1; /*!< bit: 1 Transmit Collision */ 943 uint16_t RXNACK:1; /*!< bit: 2 Received Not Acknowledge */ 944 uint16_t DIR:1; /*!< bit: 3 Read/Write Direction */ 945 uint16_t SR:1; /*!< bit: 4 Repeated Start */ 946 uint16_t :1; /*!< bit: 5 Reserved */ 947 uint16_t LOWTOUT:1; /*!< bit: 6 SCL Low Timeout */ 948 uint16_t CLKHOLD:1; /*!< bit: 7 Clock Hold */ 949 uint16_t :1; /*!< bit: 8 Reserved */ 950 uint16_t SEXTTOUT:1; /*!< bit: 9 Slave SCL Low Extend Timeout */ 951 uint16_t HS:1; /*!< bit: 10 High Speed */ 952 uint16_t :5; /*!< bit: 11..15 Reserved */ 953 } bit; /*!< Structure used for bit access */ 954 uint16_t reg; /*!< Type used for register access */ 955 } SERCOM_I2CS_STATUS_Type; 956 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 957 958 #define SERCOM_I2CS_STATUS_OFFSET 0x1A /**< \brief (SERCOM_I2CS_STATUS offset) I2CS Status */ 959 #define SERCOM_I2CS_STATUS_RESETVALUE _U(0x0000) /**< \brief (SERCOM_I2CS_STATUS reset_value) I2CS Status */ 960 961 #define SERCOM_I2CS_STATUS_BUSERR_Pos 0 /**< \brief (SERCOM_I2CS_STATUS) Bus Error */ 962 #define SERCOM_I2CS_STATUS_BUSERR (_U(0x1) << SERCOM_I2CS_STATUS_BUSERR_Pos) 963 #define SERCOM_I2CS_STATUS_COLL_Pos 1 /**< \brief (SERCOM_I2CS_STATUS) Transmit Collision */ 964 #define SERCOM_I2CS_STATUS_COLL (_U(0x1) << SERCOM_I2CS_STATUS_COLL_Pos) 965 #define SERCOM_I2CS_STATUS_RXNACK_Pos 2 /**< \brief (SERCOM_I2CS_STATUS) Received Not Acknowledge */ 966 #define SERCOM_I2CS_STATUS_RXNACK (_U(0x1) << SERCOM_I2CS_STATUS_RXNACK_Pos) 967 #define SERCOM_I2CS_STATUS_DIR_Pos 3 /**< \brief (SERCOM_I2CS_STATUS) Read/Write Direction */ 968 #define SERCOM_I2CS_STATUS_DIR (_U(0x1) << SERCOM_I2CS_STATUS_DIR_Pos) 969 #define SERCOM_I2CS_STATUS_SR_Pos 4 /**< \brief (SERCOM_I2CS_STATUS) Repeated Start */ 970 #define SERCOM_I2CS_STATUS_SR (_U(0x1) << SERCOM_I2CS_STATUS_SR_Pos) 971 #define SERCOM_I2CS_STATUS_LOWTOUT_Pos 6 /**< \brief (SERCOM_I2CS_STATUS) SCL Low Timeout */ 972 #define SERCOM_I2CS_STATUS_LOWTOUT (_U(0x1) << SERCOM_I2CS_STATUS_LOWTOUT_Pos) 973 #define SERCOM_I2CS_STATUS_CLKHOLD_Pos 7 /**< \brief (SERCOM_I2CS_STATUS) Clock Hold */ 974 #define SERCOM_I2CS_STATUS_CLKHOLD (_U(0x1) << SERCOM_I2CS_STATUS_CLKHOLD_Pos) 975 #define SERCOM_I2CS_STATUS_SEXTTOUT_Pos 9 /**< \brief (SERCOM_I2CS_STATUS) Slave SCL Low Extend Timeout */ 976 #define SERCOM_I2CS_STATUS_SEXTTOUT (_U(0x1) << SERCOM_I2CS_STATUS_SEXTTOUT_Pos) 977 #define SERCOM_I2CS_STATUS_HS_Pos 10 /**< \brief (SERCOM_I2CS_STATUS) High Speed */ 978 #define SERCOM_I2CS_STATUS_HS (_U(0x1) << SERCOM_I2CS_STATUS_HS_Pos) 979 #define SERCOM_I2CS_STATUS_MASK _U(0x06DF) /**< \brief (SERCOM_I2CS_STATUS) MASK Register */ 980 981 /* -------- SERCOM_SPI_STATUS : (SERCOM Offset: 0x1A) (R/W 16) SPI SPI Status -------- */ 982 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 983 typedef union { 984 struct { 985 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 986 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 987 uint16_t :13; /*!< bit: 3..15 Reserved */ 988 } bit; /*!< Structure used for bit access */ 989 uint16_t reg; /*!< Type used for register access */ 990 } SERCOM_SPI_STATUS_Type; 991 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 992 993 #define SERCOM_SPI_STATUS_OFFSET 0x1A /**< \brief (SERCOM_SPI_STATUS offset) SPI Status */ 994 #define SERCOM_SPI_STATUS_RESETVALUE _U(0x0000) /**< \brief (SERCOM_SPI_STATUS reset_value) SPI Status */ 995 996 #define SERCOM_SPI_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_SPI_STATUS) Buffer Overflow */ 997 #define SERCOM_SPI_STATUS_BUFOVF (_U(0x1) << SERCOM_SPI_STATUS_BUFOVF_Pos) 998 #define SERCOM_SPI_STATUS_MASK _U(0x0004) /**< \brief (SERCOM_SPI_STATUS) MASK Register */ 999 1000 /* -------- SERCOM_USART_STATUS : (SERCOM Offset: 0x1A) (R/W 16) USART USART Status -------- */ 1001 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1002 typedef union { 1003 struct { 1004 uint16_t PERR:1; /*!< bit: 0 Parity Error */ 1005 uint16_t FERR:1; /*!< bit: 1 Frame Error */ 1006 uint16_t BUFOVF:1; /*!< bit: 2 Buffer Overflow */ 1007 uint16_t CTS:1; /*!< bit: 3 Clear To Send */ 1008 uint16_t ISF:1; /*!< bit: 4 Inconsistent Sync Field */ 1009 uint16_t COLL:1; /*!< bit: 5 Collision Detected */ 1010 uint16_t :10; /*!< bit: 6..15 Reserved */ 1011 } bit; /*!< Structure used for bit access */ 1012 uint16_t reg; /*!< Type used for register access */ 1013 } SERCOM_USART_STATUS_Type; 1014 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1015 1016 #define SERCOM_USART_STATUS_OFFSET 0x1A /**< \brief (SERCOM_USART_STATUS offset) USART Status */ 1017 #define SERCOM_USART_STATUS_RESETVALUE _U(0x0000) /**< \brief (SERCOM_USART_STATUS reset_value) USART Status */ 1018 1019 #define SERCOM_USART_STATUS_PERR_Pos 0 /**< \brief (SERCOM_USART_STATUS) Parity Error */ 1020 #define SERCOM_USART_STATUS_PERR (_U(0x1) << SERCOM_USART_STATUS_PERR_Pos) 1021 #define SERCOM_USART_STATUS_FERR_Pos 1 /**< \brief (SERCOM_USART_STATUS) Frame Error */ 1022 #define SERCOM_USART_STATUS_FERR (_U(0x1) << SERCOM_USART_STATUS_FERR_Pos) 1023 #define SERCOM_USART_STATUS_BUFOVF_Pos 2 /**< \brief (SERCOM_USART_STATUS) Buffer Overflow */ 1024 #define SERCOM_USART_STATUS_BUFOVF (_U(0x1) << SERCOM_USART_STATUS_BUFOVF_Pos) 1025 #define SERCOM_USART_STATUS_CTS_Pos 3 /**< \brief (SERCOM_USART_STATUS) Clear To Send */ 1026 #define SERCOM_USART_STATUS_CTS (_U(0x1) << SERCOM_USART_STATUS_CTS_Pos) 1027 #define SERCOM_USART_STATUS_ISF_Pos 4 /**< \brief (SERCOM_USART_STATUS) Inconsistent Sync Field */ 1028 #define SERCOM_USART_STATUS_ISF (_U(0x1) << SERCOM_USART_STATUS_ISF_Pos) 1029 #define SERCOM_USART_STATUS_COLL_Pos 5 /**< \brief (SERCOM_USART_STATUS) Collision Detected */ 1030 #define SERCOM_USART_STATUS_COLL (_U(0x1) << SERCOM_USART_STATUS_COLL_Pos) 1031 #define SERCOM_USART_STATUS_MASK _U(0x003F) /**< \brief (SERCOM_USART_STATUS) MASK Register */ 1032 1033 /* -------- SERCOM_I2CM_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CM I2CM Synchronization Busy -------- */ 1034 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1035 typedef union { 1036 struct { 1037 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1038 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1039 uint32_t SYSOP:1; /*!< bit: 2 System Operation Synchronization Busy */ 1040 uint32_t :29; /*!< bit: 3..31 Reserved */ 1041 } bit; /*!< Structure used for bit access */ 1042 uint32_t reg; /*!< Type used for register access */ 1043 } SERCOM_I2CM_SYNCBUSY_Type; 1044 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1045 1046 #define SERCOM_I2CM_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CM_SYNCBUSY offset) I2CM Synchronization Busy */ 1047 #define SERCOM_I2CM_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_SYNCBUSY reset_value) I2CM Synchronization Busy */ 1048 1049 #define SERCOM_I2CM_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CM_SYNCBUSY) Software Reset Synchronization Busy */ 1050 #define SERCOM_I2CM_SYNCBUSY_SWRST (_U(0x1) << SERCOM_I2CM_SYNCBUSY_SWRST_Pos) 1051 #define SERCOM_I2CM_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CM_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1052 #define SERCOM_I2CM_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_I2CM_SYNCBUSY_ENABLE_Pos) 1053 #define SERCOM_I2CM_SYNCBUSY_SYSOP_Pos 2 /**< \brief (SERCOM_I2CM_SYNCBUSY) System Operation Synchronization Busy */ 1054 #define SERCOM_I2CM_SYNCBUSY_SYSOP (_U(0x1) << SERCOM_I2CM_SYNCBUSY_SYSOP_Pos) 1055 #define SERCOM_I2CM_SYNCBUSY_MASK _U(0x00000007) /**< \brief (SERCOM_I2CM_SYNCBUSY) MASK Register */ 1056 1057 /* -------- SERCOM_I2CS_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) I2CS I2CS Synchronization Busy -------- */ 1058 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1059 typedef union { 1060 struct { 1061 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1062 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1063 uint32_t :30; /*!< bit: 2..31 Reserved */ 1064 } bit; /*!< Structure used for bit access */ 1065 uint32_t reg; /*!< Type used for register access */ 1066 } SERCOM_I2CS_SYNCBUSY_Type; 1067 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1068 1069 #define SERCOM_I2CS_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_I2CS_SYNCBUSY offset) I2CS Synchronization Busy */ 1070 #define SERCOM_I2CS_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_SYNCBUSY reset_value) I2CS Synchronization Busy */ 1071 1072 #define SERCOM_I2CS_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_I2CS_SYNCBUSY) Software Reset Synchronization Busy */ 1073 #define SERCOM_I2CS_SYNCBUSY_SWRST (_U(0x1) << SERCOM_I2CS_SYNCBUSY_SWRST_Pos) 1074 #define SERCOM_I2CS_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_I2CS_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1075 #define SERCOM_I2CS_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_I2CS_SYNCBUSY_ENABLE_Pos) 1076 #define SERCOM_I2CS_SYNCBUSY_MASK _U(0x00000003) /**< \brief (SERCOM_I2CS_SYNCBUSY) MASK Register */ 1077 1078 /* -------- SERCOM_SPI_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) SPI SPI Synchronization Busy -------- */ 1079 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1080 typedef union { 1081 struct { 1082 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1083 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1084 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ 1085 uint32_t :29; /*!< bit: 3..31 Reserved */ 1086 } bit; /*!< Structure used for bit access */ 1087 uint32_t reg; /*!< Type used for register access */ 1088 } SERCOM_SPI_SYNCBUSY_Type; 1089 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1090 1091 #define SERCOM_SPI_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_SPI_SYNCBUSY offset) SPI Synchronization Busy */ 1092 #define SERCOM_SPI_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_SYNCBUSY reset_value) SPI Synchronization Busy */ 1093 1094 #define SERCOM_SPI_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_SPI_SYNCBUSY) Software Reset Synchronization Busy */ 1095 #define SERCOM_SPI_SYNCBUSY_SWRST (_U(0x1) << SERCOM_SPI_SYNCBUSY_SWRST_Pos) 1096 #define SERCOM_SPI_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_SPI_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1097 #define SERCOM_SPI_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_SPI_SYNCBUSY_ENABLE_Pos) 1098 #define SERCOM_SPI_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_SPI_SYNCBUSY) CTRLB Synchronization Busy */ 1099 #define SERCOM_SPI_SYNCBUSY_CTRLB (_U(0x1) << SERCOM_SPI_SYNCBUSY_CTRLB_Pos) 1100 #define SERCOM_SPI_SYNCBUSY_MASK _U(0x00000007) /**< \brief (SERCOM_SPI_SYNCBUSY) MASK Register */ 1101 1102 /* -------- SERCOM_USART_SYNCBUSY : (SERCOM Offset: 0x1C) (R/ 32) USART USART Synchronization Busy -------- */ 1103 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1104 typedef union { 1105 struct { 1106 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 1107 uint32_t ENABLE:1; /*!< bit: 1 SERCOM Enable Synchronization Busy */ 1108 uint32_t CTRLB:1; /*!< bit: 2 CTRLB Synchronization Busy */ 1109 uint32_t :29; /*!< bit: 3..31 Reserved */ 1110 } bit; /*!< Structure used for bit access */ 1111 uint32_t reg; /*!< Type used for register access */ 1112 } SERCOM_USART_SYNCBUSY_Type; 1113 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1114 1115 #define SERCOM_USART_SYNCBUSY_OFFSET 0x1C /**< \brief (SERCOM_USART_SYNCBUSY offset) USART Synchronization Busy */ 1116 #define SERCOM_USART_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_USART_SYNCBUSY reset_value) USART Synchronization Busy */ 1117 1118 #define SERCOM_USART_SYNCBUSY_SWRST_Pos 0 /**< \brief (SERCOM_USART_SYNCBUSY) Software Reset Synchronization Busy */ 1119 #define SERCOM_USART_SYNCBUSY_SWRST (_U(0x1) << SERCOM_USART_SYNCBUSY_SWRST_Pos) 1120 #define SERCOM_USART_SYNCBUSY_ENABLE_Pos 1 /**< \brief (SERCOM_USART_SYNCBUSY) SERCOM Enable Synchronization Busy */ 1121 #define SERCOM_USART_SYNCBUSY_ENABLE (_U(0x1) << SERCOM_USART_SYNCBUSY_ENABLE_Pos) 1122 #define SERCOM_USART_SYNCBUSY_CTRLB_Pos 2 /**< \brief (SERCOM_USART_SYNCBUSY) CTRLB Synchronization Busy */ 1123 #define SERCOM_USART_SYNCBUSY_CTRLB (_U(0x1) << SERCOM_USART_SYNCBUSY_CTRLB_Pos) 1124 #define SERCOM_USART_SYNCBUSY_MASK _U(0x00000007) /**< \brief (SERCOM_USART_SYNCBUSY) MASK Register */ 1125 1126 /* -------- SERCOM_I2CM_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CM I2CM Address -------- */ 1127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1128 typedef union { 1129 struct { 1130 uint32_t ADDR:11; /*!< bit: 0..10 Address Value */ 1131 uint32_t :2; /*!< bit: 11..12 Reserved */ 1132 uint32_t LENEN:1; /*!< bit: 13 Length Enable */ 1133 uint32_t HS:1; /*!< bit: 14 High Speed Mode */ 1134 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ 1135 uint32_t LEN:8; /*!< bit: 16..23 Length */ 1136 uint32_t :8; /*!< bit: 24..31 Reserved */ 1137 } bit; /*!< Structure used for bit access */ 1138 uint32_t reg; /*!< Type used for register access */ 1139 } SERCOM_I2CM_ADDR_Type; 1140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1141 1142 #define SERCOM_I2CM_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CM_ADDR offset) I2CM Address */ 1143 #define SERCOM_I2CM_ADDR_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CM_ADDR reset_value) I2CM Address */ 1144 1145 #define SERCOM_I2CM_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_I2CM_ADDR) Address Value */ 1146 #define SERCOM_I2CM_ADDR_ADDR_Msk (_U(0x7FF) << SERCOM_I2CM_ADDR_ADDR_Pos) 1147 #define SERCOM_I2CM_ADDR_ADDR(value) (SERCOM_I2CM_ADDR_ADDR_Msk & ((value) << SERCOM_I2CM_ADDR_ADDR_Pos)) 1148 #define SERCOM_I2CM_ADDR_LENEN_Pos 13 /**< \brief (SERCOM_I2CM_ADDR) Length Enable */ 1149 #define SERCOM_I2CM_ADDR_LENEN (_U(0x1) << SERCOM_I2CM_ADDR_LENEN_Pos) 1150 #define SERCOM_I2CM_ADDR_HS_Pos 14 /**< \brief (SERCOM_I2CM_ADDR) High Speed Mode */ 1151 #define SERCOM_I2CM_ADDR_HS (_U(0x1) << SERCOM_I2CM_ADDR_HS_Pos) 1152 #define SERCOM_I2CM_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CM_ADDR) Ten Bit Addressing Enable */ 1153 #define SERCOM_I2CM_ADDR_TENBITEN (_U(0x1) << SERCOM_I2CM_ADDR_TENBITEN_Pos) 1154 #define SERCOM_I2CM_ADDR_LEN_Pos 16 /**< \brief (SERCOM_I2CM_ADDR) Length */ 1155 #define SERCOM_I2CM_ADDR_LEN_Msk (_U(0xFF) << SERCOM_I2CM_ADDR_LEN_Pos) 1156 #define SERCOM_I2CM_ADDR_LEN(value) (SERCOM_I2CM_ADDR_LEN_Msk & ((value) << SERCOM_I2CM_ADDR_LEN_Pos)) 1157 #define SERCOM_I2CM_ADDR_MASK _U(0x00FFE7FF) /**< \brief (SERCOM_I2CM_ADDR) MASK Register */ 1158 1159 /* -------- SERCOM_I2CS_ADDR : (SERCOM Offset: 0x24) (R/W 32) I2CS I2CS Address -------- */ 1160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1161 typedef union { 1162 struct { 1163 uint32_t GENCEN:1; /*!< bit: 0 General Call Address Enable */ 1164 uint32_t ADDR:10; /*!< bit: 1..10 Address Value */ 1165 uint32_t :4; /*!< bit: 11..14 Reserved */ 1166 uint32_t TENBITEN:1; /*!< bit: 15 Ten Bit Addressing Enable */ 1167 uint32_t :1; /*!< bit: 16 Reserved */ 1168 uint32_t ADDRMASK:10; /*!< bit: 17..26 Address Mask */ 1169 uint32_t :5; /*!< bit: 27..31 Reserved */ 1170 } bit; /*!< Structure used for bit access */ 1171 uint32_t reg; /*!< Type used for register access */ 1172 } SERCOM_I2CS_ADDR_Type; 1173 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1174 1175 #define SERCOM_I2CS_ADDR_OFFSET 0x24 /**< \brief (SERCOM_I2CS_ADDR offset) I2CS Address */ 1176 #define SERCOM_I2CS_ADDR_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_I2CS_ADDR reset_value) I2CS Address */ 1177 1178 #define SERCOM_I2CS_ADDR_GENCEN_Pos 0 /**< \brief (SERCOM_I2CS_ADDR) General Call Address Enable */ 1179 #define SERCOM_I2CS_ADDR_GENCEN (_U(0x1) << SERCOM_I2CS_ADDR_GENCEN_Pos) 1180 #define SERCOM_I2CS_ADDR_ADDR_Pos 1 /**< \brief (SERCOM_I2CS_ADDR) Address Value */ 1181 #define SERCOM_I2CS_ADDR_ADDR_Msk (_U(0x3FF) << SERCOM_I2CS_ADDR_ADDR_Pos) 1182 #define SERCOM_I2CS_ADDR_ADDR(value) (SERCOM_I2CS_ADDR_ADDR_Msk & ((value) << SERCOM_I2CS_ADDR_ADDR_Pos)) 1183 #define SERCOM_I2CS_ADDR_TENBITEN_Pos 15 /**< \brief (SERCOM_I2CS_ADDR) Ten Bit Addressing Enable */ 1184 #define SERCOM_I2CS_ADDR_TENBITEN (_U(0x1) << SERCOM_I2CS_ADDR_TENBITEN_Pos) 1185 #define SERCOM_I2CS_ADDR_ADDRMASK_Pos 17 /**< \brief (SERCOM_I2CS_ADDR) Address Mask */ 1186 #define SERCOM_I2CS_ADDR_ADDRMASK_Msk (_U(0x3FF) << SERCOM_I2CS_ADDR_ADDRMASK_Pos) 1187 #define SERCOM_I2CS_ADDR_ADDRMASK(value) (SERCOM_I2CS_ADDR_ADDRMASK_Msk & ((value) << SERCOM_I2CS_ADDR_ADDRMASK_Pos)) 1188 #define SERCOM_I2CS_ADDR_MASK _U(0x07FE87FF) /**< \brief (SERCOM_I2CS_ADDR) MASK Register */ 1189 1190 /* -------- SERCOM_SPI_ADDR : (SERCOM Offset: 0x24) (R/W 32) SPI SPI Address -------- */ 1191 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1192 typedef union { 1193 struct { 1194 uint32_t ADDR:8; /*!< bit: 0.. 7 Address Value */ 1195 uint32_t :8; /*!< bit: 8..15 Reserved */ 1196 uint32_t ADDRMASK:8; /*!< bit: 16..23 Address Mask */ 1197 uint32_t :8; /*!< bit: 24..31 Reserved */ 1198 } bit; /*!< Structure used for bit access */ 1199 uint32_t reg; /*!< Type used for register access */ 1200 } SERCOM_SPI_ADDR_Type; 1201 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1202 1203 #define SERCOM_SPI_ADDR_OFFSET 0x24 /**< \brief (SERCOM_SPI_ADDR offset) SPI Address */ 1204 #define SERCOM_SPI_ADDR_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_ADDR reset_value) SPI Address */ 1205 1206 #define SERCOM_SPI_ADDR_ADDR_Pos 0 /**< \brief (SERCOM_SPI_ADDR) Address Value */ 1207 #define SERCOM_SPI_ADDR_ADDR_Msk (_U(0xFF) << SERCOM_SPI_ADDR_ADDR_Pos) 1208 #define SERCOM_SPI_ADDR_ADDR(value) (SERCOM_SPI_ADDR_ADDR_Msk & ((value) << SERCOM_SPI_ADDR_ADDR_Pos)) 1209 #define SERCOM_SPI_ADDR_ADDRMASK_Pos 16 /**< \brief (SERCOM_SPI_ADDR) Address Mask */ 1210 #define SERCOM_SPI_ADDR_ADDRMASK_Msk (_U(0xFF) << SERCOM_SPI_ADDR_ADDRMASK_Pos) 1211 #define SERCOM_SPI_ADDR_ADDRMASK(value) (SERCOM_SPI_ADDR_ADDRMASK_Msk & ((value) << SERCOM_SPI_ADDR_ADDRMASK_Pos)) 1212 #define SERCOM_SPI_ADDR_MASK _U(0x00FF00FF) /**< \brief (SERCOM_SPI_ADDR) MASK Register */ 1213 1214 /* -------- SERCOM_I2CM_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CM I2CM Data -------- */ 1215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1216 typedef union { 1217 struct { 1218 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ 1219 } bit; /*!< Structure used for bit access */ 1220 uint8_t reg; /*!< Type used for register access */ 1221 } SERCOM_I2CM_DATA_Type; 1222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1223 1224 #define SERCOM_I2CM_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CM_DATA offset) I2CM Data */ 1225 #define SERCOM_I2CM_DATA_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CM_DATA reset_value) I2CM Data */ 1226 1227 #define SERCOM_I2CM_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CM_DATA) Data Value */ 1228 #define SERCOM_I2CM_DATA_DATA_Msk (_U(0xFF) << SERCOM_I2CM_DATA_DATA_Pos) 1229 #define SERCOM_I2CM_DATA_DATA(value) (SERCOM_I2CM_DATA_DATA_Msk & ((value) << SERCOM_I2CM_DATA_DATA_Pos)) 1230 #define SERCOM_I2CM_DATA_MASK _U(0xFF) /**< \brief (SERCOM_I2CM_DATA) MASK Register */ 1231 1232 /* -------- SERCOM_I2CS_DATA : (SERCOM Offset: 0x28) (R/W 8) I2CS I2CS Data -------- */ 1233 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1234 typedef union { 1235 struct { 1236 uint8_t DATA:8; /*!< bit: 0.. 7 Data Value */ 1237 } bit; /*!< Structure used for bit access */ 1238 uint8_t reg; /*!< Type used for register access */ 1239 } SERCOM_I2CS_DATA_Type; 1240 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1241 1242 #define SERCOM_I2CS_DATA_OFFSET 0x28 /**< \brief (SERCOM_I2CS_DATA offset) I2CS Data */ 1243 #define SERCOM_I2CS_DATA_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CS_DATA reset_value) I2CS Data */ 1244 1245 #define SERCOM_I2CS_DATA_DATA_Pos 0 /**< \brief (SERCOM_I2CS_DATA) Data Value */ 1246 #define SERCOM_I2CS_DATA_DATA_Msk (_U(0xFF) << SERCOM_I2CS_DATA_DATA_Pos) 1247 #define SERCOM_I2CS_DATA_DATA(value) (SERCOM_I2CS_DATA_DATA_Msk & ((value) << SERCOM_I2CS_DATA_DATA_Pos)) 1248 #define SERCOM_I2CS_DATA_MASK _U(0xFF) /**< \brief (SERCOM_I2CS_DATA) MASK Register */ 1249 1250 /* -------- SERCOM_SPI_DATA : (SERCOM Offset: 0x28) (R/W 32) SPI SPI Data -------- */ 1251 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1252 typedef union { 1253 struct { 1254 uint32_t DATA:9; /*!< bit: 0.. 8 Data Value */ 1255 uint32_t :23; /*!< bit: 9..31 Reserved */ 1256 } bit; /*!< Structure used for bit access */ 1257 uint32_t reg; /*!< Type used for register access */ 1258 } SERCOM_SPI_DATA_Type; 1259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1260 1261 #define SERCOM_SPI_DATA_OFFSET 0x28 /**< \brief (SERCOM_SPI_DATA offset) SPI Data */ 1262 #define SERCOM_SPI_DATA_RESETVALUE _U(0x00000000) /**< \brief (SERCOM_SPI_DATA reset_value) SPI Data */ 1263 1264 #define SERCOM_SPI_DATA_DATA_Pos 0 /**< \brief (SERCOM_SPI_DATA) Data Value */ 1265 #define SERCOM_SPI_DATA_DATA_Msk (_U(0x1FF) << SERCOM_SPI_DATA_DATA_Pos) 1266 #define SERCOM_SPI_DATA_DATA(value) (SERCOM_SPI_DATA_DATA_Msk & ((value) << SERCOM_SPI_DATA_DATA_Pos)) 1267 #define SERCOM_SPI_DATA_MASK _U(0x000001FF) /**< \brief (SERCOM_SPI_DATA) MASK Register */ 1268 1269 /* -------- SERCOM_USART_DATA : (SERCOM Offset: 0x28) (R/W 16) USART USART Data -------- */ 1270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1271 typedef union { 1272 struct { 1273 uint16_t DATA:9; /*!< bit: 0.. 8 Data Value */ 1274 uint16_t :7; /*!< bit: 9..15 Reserved */ 1275 } bit; /*!< Structure used for bit access */ 1276 uint16_t reg; /*!< Type used for register access */ 1277 } SERCOM_USART_DATA_Type; 1278 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1279 1280 #define SERCOM_USART_DATA_OFFSET 0x28 /**< \brief (SERCOM_USART_DATA offset) USART Data */ 1281 #define SERCOM_USART_DATA_RESETVALUE _U(0x0000) /**< \brief (SERCOM_USART_DATA reset_value) USART Data */ 1282 1283 #define SERCOM_USART_DATA_DATA_Pos 0 /**< \brief (SERCOM_USART_DATA) Data Value */ 1284 #define SERCOM_USART_DATA_DATA_Msk (_U(0x1FF) << SERCOM_USART_DATA_DATA_Pos) 1285 #define SERCOM_USART_DATA_DATA(value) (SERCOM_USART_DATA_DATA_Msk & ((value) << SERCOM_USART_DATA_DATA_Pos)) 1286 #define SERCOM_USART_DATA_MASK _U(0x01FF) /**< \brief (SERCOM_USART_DATA) MASK Register */ 1287 1288 /* -------- SERCOM_I2CM_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) I2CM I2CM Debug Control -------- */ 1289 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1290 typedef union { 1291 struct { 1292 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1293 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1294 } bit; /*!< Structure used for bit access */ 1295 uint8_t reg; /*!< Type used for register access */ 1296 } SERCOM_I2CM_DBGCTRL_Type; 1297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1298 1299 #define SERCOM_I2CM_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_I2CM_DBGCTRL offset) I2CM Debug Control */ 1300 #define SERCOM_I2CM_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (SERCOM_I2CM_DBGCTRL reset_value) I2CM Debug Control */ 1301 1302 #define SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_I2CM_DBGCTRL) Debug Mode */ 1303 #define SERCOM_I2CM_DBGCTRL_DBGSTOP (_U(0x1) << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos) 1304 #define SERCOM_I2CM_DBGCTRL_MASK _U(0x01) /**< \brief (SERCOM_I2CM_DBGCTRL) MASK Register */ 1305 1306 /* -------- SERCOM_SPI_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) SPI SPI Debug Control -------- */ 1307 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1308 typedef union { 1309 struct { 1310 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1311 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1312 } bit; /*!< Structure used for bit access */ 1313 uint8_t reg; /*!< Type used for register access */ 1314 } SERCOM_SPI_DBGCTRL_Type; 1315 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1316 1317 #define SERCOM_SPI_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_SPI_DBGCTRL offset) SPI Debug Control */ 1318 #define SERCOM_SPI_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (SERCOM_SPI_DBGCTRL reset_value) SPI Debug Control */ 1319 1320 #define SERCOM_SPI_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_SPI_DBGCTRL) Debug Mode */ 1321 #define SERCOM_SPI_DBGCTRL_DBGSTOP (_U(0x1) << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos) 1322 #define SERCOM_SPI_DBGCTRL_MASK _U(0x01) /**< \brief (SERCOM_SPI_DBGCTRL) MASK Register */ 1323 1324 /* -------- SERCOM_USART_DBGCTRL : (SERCOM Offset: 0x30) (R/W 8) USART USART Debug Control -------- */ 1325 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1326 typedef union { 1327 struct { 1328 uint8_t DBGSTOP:1; /*!< bit: 0 Debug Mode */ 1329 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 1330 } bit; /*!< Structure used for bit access */ 1331 uint8_t reg; /*!< Type used for register access */ 1332 } SERCOM_USART_DBGCTRL_Type; 1333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1334 1335 #define SERCOM_USART_DBGCTRL_OFFSET 0x30 /**< \brief (SERCOM_USART_DBGCTRL offset) USART Debug Control */ 1336 #define SERCOM_USART_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (SERCOM_USART_DBGCTRL reset_value) USART Debug Control */ 1337 1338 #define SERCOM_USART_DBGCTRL_DBGSTOP_Pos 0 /**< \brief (SERCOM_USART_DBGCTRL) Debug Mode */ 1339 #define SERCOM_USART_DBGCTRL_DBGSTOP (_U(0x1) << SERCOM_USART_DBGCTRL_DBGSTOP_Pos) 1340 #define SERCOM_USART_DBGCTRL_MASK _U(0x01) /**< \brief (SERCOM_USART_DBGCTRL) MASK Register */ 1341 1342 /** \brief SERCOM_I2CM hardware registers */ 1343 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1344 typedef struct { /* I2C Master Mode */ 1345 __IO SERCOM_I2CM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CM Control A */ 1346 __IO SERCOM_I2CM_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CM Control B */ 1347 RoReg8 Reserved1[0x4]; 1348 __IO SERCOM_I2CM_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 32) I2CM Baud Rate */ 1349 RoReg8 Reserved2[0x4]; 1350 __IO SERCOM_I2CM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear */ 1351 RoReg8 Reserved3[0x1]; 1352 __IO SERCOM_I2CM_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set */ 1353 RoReg8 Reserved4[0x1]; 1354 __IO SERCOM_I2CM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear */ 1355 RoReg8 Reserved5[0x1]; 1356 __IO SERCOM_I2CM_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CM Status */ 1357 __I SERCOM_I2CM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CM Synchronization Busy */ 1358 RoReg8 Reserved6[0x4]; 1359 __IO SERCOM_I2CM_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CM Address */ 1360 __IO SERCOM_I2CM_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CM Data */ 1361 RoReg8 Reserved7[0x7]; 1362 __IO SERCOM_I2CM_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) I2CM Debug Control */ 1363 } SercomI2cm; 1364 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1365 1366 /** \brief SERCOM_I2CS hardware registers */ 1367 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1368 typedef struct { /* I2C Slave Mode */ 1369 __IO SERCOM_I2CS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) I2CS Control A */ 1370 __IO SERCOM_I2CS_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) I2CS Control B */ 1371 RoReg8 Reserved1[0xC]; 1372 __IO SERCOM_I2CS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) I2CS Interrupt Enable Clear */ 1373 RoReg8 Reserved2[0x1]; 1374 __IO SERCOM_I2CS_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) I2CS Interrupt Enable Set */ 1375 RoReg8 Reserved3[0x1]; 1376 __IO SERCOM_I2CS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) I2CS Interrupt Flag Status and Clear */ 1377 RoReg8 Reserved4[0x1]; 1378 __IO SERCOM_I2CS_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) I2CS Status */ 1379 __I SERCOM_I2CS_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) I2CS Synchronization Busy */ 1380 RoReg8 Reserved5[0x4]; 1381 __IO SERCOM_I2CS_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) I2CS Address */ 1382 __IO SERCOM_I2CS_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 8) I2CS Data */ 1383 } SercomI2cs; 1384 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1385 1386 /** \brief SERCOM_SPI hardware registers */ 1387 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1388 typedef struct { /* SPI Mode */ 1389 __IO SERCOM_SPI_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) SPI Control A */ 1390 __IO SERCOM_SPI_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) SPI Control B */ 1391 RoReg8 Reserved1[0x4]; 1392 __IO SERCOM_SPI_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 8) SPI Baud Rate */ 1393 RoReg8 Reserved2[0x7]; 1394 __IO SERCOM_SPI_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) SPI Interrupt Enable Clear */ 1395 RoReg8 Reserved3[0x1]; 1396 __IO SERCOM_SPI_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) SPI Interrupt Enable Set */ 1397 RoReg8 Reserved4[0x1]; 1398 __IO SERCOM_SPI_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) SPI Interrupt Flag Status and Clear */ 1399 RoReg8 Reserved5[0x1]; 1400 __IO SERCOM_SPI_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) SPI Status */ 1401 __I SERCOM_SPI_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) SPI Synchronization Busy */ 1402 RoReg8 Reserved6[0x4]; 1403 __IO SERCOM_SPI_ADDR_Type ADDR; /**< \brief Offset: 0x24 (R/W 32) SPI Address */ 1404 __IO SERCOM_SPI_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 32) SPI Data */ 1405 RoReg8 Reserved7[0x4]; 1406 __IO SERCOM_SPI_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) SPI Debug Control */ 1407 } SercomSpi; 1408 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1409 1410 /** \brief SERCOM_USART hardware registers */ 1411 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1412 typedef struct { /* USART Mode */ 1413 __IO SERCOM_USART_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) USART Control A */ 1414 __IO SERCOM_USART_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) USART Control B */ 1415 RoReg8 Reserved1[0x4]; 1416 __IO SERCOM_USART_BAUD_Type BAUD; /**< \brief Offset: 0x0C (R/W 16) USART Baud Rate */ 1417 __IO SERCOM_USART_RXPL_Type RXPL; /**< \brief Offset: 0x0E (R/W 8) USART Receive Pulse Length */ 1418 RoReg8 Reserved2[0x5]; 1419 __IO SERCOM_USART_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x14 (R/W 8) USART Interrupt Enable Clear */ 1420 RoReg8 Reserved3[0x1]; 1421 __IO SERCOM_USART_INTENSET_Type INTENSET; /**< \brief Offset: 0x16 (R/W 8) USART Interrupt Enable Set */ 1422 RoReg8 Reserved4[0x1]; 1423 __IO SERCOM_USART_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) USART Interrupt Flag Status and Clear */ 1424 RoReg8 Reserved5[0x1]; 1425 __IO SERCOM_USART_STATUS_Type STATUS; /**< \brief Offset: 0x1A (R/W 16) USART Status */ 1426 __I SERCOM_USART_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x1C (R/ 32) USART Synchronization Busy */ 1427 RoReg8 Reserved6[0x8]; 1428 __IO SERCOM_USART_DATA_Type DATA; /**< \brief Offset: 0x28 (R/W 16) USART Data */ 1429 RoReg8 Reserved7[0x6]; 1430 __IO SERCOM_USART_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x30 (R/W 8) USART Debug Control */ 1431 } SercomUsart; 1432 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1433 1434 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 1435 typedef union { 1436 SercomI2cm I2CM; /**< \brief Offset: 0x00 I2C Master Mode */ 1437 SercomI2cs I2CS; /**< \brief Offset: 0x00 I2C Slave Mode */ 1438 SercomSpi SPI; /**< \brief Offset: 0x00 SPI Mode */ 1439 SercomUsart USART; /**< \brief Offset: 0x00 USART Mode */ 1440 } Sercom; 1441 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 1442 1443 /*@}*/ 1444 1445 #endif /* _SAML21_SERCOM_COMPONENT_ */ 1446
