1 // Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 //     http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14 #ifndef _SOC_SENSITIVE_REG_H_
15 #define _SOC_SENSITIVE_REG_H_
16 
17 
18 #include "soc.h"
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22 
23 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG          (DR_REG_SENSITIVE_BASE + 0x0)
24 /* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
25 /*description: .*/
26 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK    (BIT(0))
27 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M  (BIT(0))
28 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V  0x1
29 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S  0
30 
31 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG          (DR_REG_SENSITIVE_BASE + 0x4)
32 /* SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN : R/W ;bitpos:[7:0] ;default: ~8'b0 ; */
33 /*description: .*/
34 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN    0x000000FF
35 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M  ((SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V)<<(SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S))
36 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V  0xFF
37 #define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S  0
38 
39 #define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x8)
40 /* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
41 /*description: .*/
42 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK    (BIT(0))
43 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M  (BIT(0))
44 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V  0x1
45 #define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S  0
46 
47 #define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0xC)
48 /* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
49 /*description: .*/
50 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST    (BIT(0))
51 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M  (BIT(0))
52 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V  0x1
53 #define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S  0
54 
55 #define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG          (DR_REG_SENSITIVE_BASE + 0x10)
56 /* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
57 /*description: .*/
58 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK    (BIT(0))
59 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M  (BIT(0))
60 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V  0x1
61 #define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S  0
62 
63 #define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG          (DR_REG_SENSITIVE_BASE + 0x14)
64 /* SENSITIVE_INTERNAL_SRAM_CPU_USAGE : R/W ;bitpos:[10:4] ;default: ~7'h0 ; */
65 /*description: .*/
66 #define SENSITIVE_INTERNAL_SRAM_CPU_USAGE    0x0000007F
67 #define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S))
68 #define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_V  0x7F
69 #define SENSITIVE_INTERNAL_SRAM_CPU_USAGE_S  4
70 /* SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE : R/W ;bitpos:[3:2] ;default: ~2'h0 ; */
71 /*description: .*/
72 #define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE    0x00000003
73 #define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S))
74 #define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_V  0x3
75 #define SENSITIVE_INTERNAL_SRAM_DCACHE_USAGE_S  2
76 /* SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE : R/W ;bitpos:[1:0] ;default: ~2'h0 ; */
77 /*description: .*/
78 #define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE    0x00000003
79 #define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S))
80 #define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_V  0x3
81 #define SENSITIVE_INTERNAL_SRAM_ICACHE_USAGE_S  0
82 
83 #define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG          (DR_REG_SENSITIVE_BASE + 0x18)
84 /* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
85 /*description: .*/
86 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC    0x00000003
87 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_M  ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S))
88 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_V  0x3
89 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_ALLOC_S  16
90 /* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
91 /*description: .*/
92 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC    0x00000003
93 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_M  ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S))
94 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_V  0x3
95 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_ALLOC_S  14
96 /* SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE : R/W ;bitpos:[13:7] ;default: 7'b0 ; */
97 /*description: .*/
98 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE    0x0000007F
99 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S))
100 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_V  0x7F
101 #define SENSITIVE_INTERNAL_SRAM_CORE1_TRACE_USAGE_S  7
102 /* SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
103 /*description: .*/
104 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE    0x0000007F
105 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S))
106 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_V  0x7F
107 #define SENSITIVE_INTERNAL_SRAM_CORE0_TRACE_USAGE_S  0
108 
109 #define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG          (DR_REG_SENSITIVE_BASE + 0x1C)
110 /* SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
111 /*description: .*/
112 #define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE    0x0000000F
113 #define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S))
114 #define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_V  0xF
115 #define SENSITIVE_INTERNAL_SRAM_MAC_DUMP_USAGE_S  0
116 
117 #define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG          (DR_REG_SENSITIVE_BASE + 0x20)
118 /* SENSITIVE_INTERNAL_SRAM_LOG_USAGE : R/W ;bitpos:[6:0] ;default: 7'b0 ; */
119 /*description: .*/
120 #define SENSITIVE_INTERNAL_SRAM_LOG_USAGE    0x0000007F
121 #define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_M  ((SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V)<<(SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S))
122 #define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_V  0x7F
123 #define SENSITIVE_INTERNAL_SRAM_LOG_USAGE_S  0
124 
125 #define SENSITIVE_RETENTION_DISABLE_REG          (DR_REG_SENSITIVE_BASE + 0x24)
126 /* SENSITIVE_RETENTION_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
127 /*description: .*/
128 #define SENSITIVE_RETENTION_DISABLE    (BIT(0))
129 #define SENSITIVE_RETENTION_DISABLE_M  (BIT(0))
130 #define SENSITIVE_RETENTION_DISABLE_V  0x1
131 #define SENSITIVE_RETENTION_DISABLE_S  0
132 
133 #define SENSITIVE_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x28)
134 /* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
135 /*description: .*/
136 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK    (BIT(0))
137 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
138 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V  0x1
139 #define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S  0
140 
141 #define SENSITIVE_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x2C)
142 /* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */
143 /*description: .*/
144 #define SENSITIVE_PRO_D_TAG_WR_ACS    (BIT(3))
145 #define SENSITIVE_PRO_D_TAG_WR_ACS_M  (BIT(3))
146 #define SENSITIVE_PRO_D_TAG_WR_ACS_V  0x1
147 #define SENSITIVE_PRO_D_TAG_WR_ACS_S  3
148 /* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */
149 /*description: .*/
150 #define SENSITIVE_PRO_D_TAG_RD_ACS    (BIT(2))
151 #define SENSITIVE_PRO_D_TAG_RD_ACS_M  (BIT(2))
152 #define SENSITIVE_PRO_D_TAG_RD_ACS_V  0x1
153 #define SENSITIVE_PRO_D_TAG_RD_ACS_S  2
154 /* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */
155 /*description: .*/
156 #define SENSITIVE_PRO_I_TAG_WR_ACS    (BIT(1))
157 #define SENSITIVE_PRO_I_TAG_WR_ACS_M  (BIT(1))
158 #define SENSITIVE_PRO_I_TAG_WR_ACS_V  0x1
159 #define SENSITIVE_PRO_I_TAG_WR_ACS_S  1
160 /* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */
161 /*description: .*/
162 #define SENSITIVE_PRO_I_TAG_RD_ACS    (BIT(0))
163 #define SENSITIVE_PRO_I_TAG_RD_ACS_M  (BIT(0))
164 #define SENSITIVE_PRO_I_TAG_RD_ACS_V  0x1
165 #define SENSITIVE_PRO_I_TAG_RD_ACS_S  0
166 
167 #define SENSITIVE_CACHE_MMU_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x30)
168 /* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
169 /*description: .*/
170 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK    (BIT(0))
171 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M  (BIT(0))
172 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V  0x1
173 #define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S  0
174 
175 #define SENSITIVE_CACHE_MMU_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x34)
176 /* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */
177 /*description: .*/
178 #define SENSITIVE_PRO_MMU_WR_ACS    (BIT(1))
179 #define SENSITIVE_PRO_MMU_WR_ACS_M  (BIT(1))
180 #define SENSITIVE_PRO_MMU_WR_ACS_V  0x1
181 #define SENSITIVE_PRO_MMU_WR_ACS_S  1
182 /* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */
183 /*description: .*/
184 #define SENSITIVE_PRO_MMU_RD_ACS    (BIT(0))
185 #define SENSITIVE_PRO_MMU_RD_ACS_M  (BIT(0))
186 #define SENSITIVE_PRO_MMU_RD_ACS_V  0x1
187 #define SENSITIVE_PRO_MMU_RD_ACS_S  0
188 
189 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x38)
190 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
191 /*description: .*/
192 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK    (BIT(0))
193 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M  (BIT(0))
194 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V  0x1
195 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S  0
196 
197 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x3C)
198 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
199 /*description: .*/
200 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
201 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
202 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
203 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
204 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
205 /*description: .*/
206 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
207 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
208 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
209 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
210 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
211 /*description: .*/
212 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
213 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S))
214 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
215 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_3_S  6
216 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
217 /*description: .*/
218 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
219 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S))
220 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
221 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_2_S  4
222 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
223 /*description: .*/
224 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
225 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S))
226 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
227 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_1_S  2
228 /* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
229 /*description: .*/
230 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
231 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S))
232 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
233 #define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_PMS_0_S  0
234 
235 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x40)
236 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
237 /*description: .*/
238 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK    (BIT(0))
239 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M  (BIT(0))
240 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V  0x1
241 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S  0
242 
243 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x44)
244 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
245 /*description: .*/
246 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
247 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
248 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
249 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
250 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
251 /*description: .*/
252 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
253 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
254 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
255 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
256 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
257 /*description: .*/
258 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
259 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S))
260 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
261 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_3_S  6
262 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
263 /*description: .*/
264 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
265 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S))
266 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
267 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_2_S  4
268 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
269 /*description: .*/
270 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
271 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S))
272 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
273 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_1_S  2
274 /* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
275 /*description: .*/
276 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
277 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S))
278 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
279 #define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_PMS_0_S  0
280 
281 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x48)
282 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
283 /*description: .*/
284 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK    (BIT(0))
285 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
286 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_V  0x1
287 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_LOCK_S  0
288 
289 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x4C)
290 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
291 /*description: .*/
292 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
293 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
294 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
295 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
296 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
297 /*description: .*/
298 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
299 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
300 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
301 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
302 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
303 /*description: .*/
304 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
305 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S))
306 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
307 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_3_S  6
308 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
309 /*description: .*/
310 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
311 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S))
312 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
313 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_2_S  4
314 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
315 /*description: .*/
316 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
317 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S))
318 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
319 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_1_S  2
320 /* SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
321 /*description: .*/
322 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
323 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S))
324 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
325 #define SENSITIVE_DMA_APBPERI_UHCI0_PMS_CONSTRAIN_SRAM_PMS_0_S  0
326 
327 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x50)
328 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
329 /*description: .*/
330 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK    (BIT(0))
331 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
332 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V  0x1
333 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S  0
334 
335 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x54)
336 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
337 /*description: .*/
338 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
339 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
340 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
341 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
342 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
343 /*description: .*/
344 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
345 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
346 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
347 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
348 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
349 /*description: .*/
350 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
351 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S))
352 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
353 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_3_S  6
354 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
355 /*description: .*/
356 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
357 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S))
358 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
359 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_2_S  4
360 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
361 /*description: .*/
362 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
363 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S))
364 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
365 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_1_S  2
366 /* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
367 /*description: .*/
368 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
369 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S))
370 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
371 #define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_PMS_0_S  0
372 
373 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x58)
374 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
375 /*description: .*/
376 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK    (BIT(0))
377 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M  (BIT(0))
378 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V  0x1
379 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S  0
380 
381 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x5C)
382 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
383 /*description: .*/
384 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
385 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
386 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
387 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
388 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
389 /*description: .*/
390 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
391 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
392 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
393 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
394 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
395 /*description: .*/
396 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
397 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S))
398 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
399 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_3_S  6
400 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
401 /*description: .*/
402 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
403 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S))
404 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
405 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_2_S  4
406 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
407 /*description: .*/
408 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
409 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S))
410 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
411 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_1_S  2
412 /* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
413 /*description: .*/
414 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
415 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S))
416 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
417 #define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_PMS_0_S  0
418 
419 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x60)
420 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
421 /*description: .*/
422 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK    (BIT(0))
423 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
424 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V  0x1
425 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S  0
426 
427 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x64)
428 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
429 /*description: .*/
430 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
431 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
432 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
433 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
434 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
435 /*description: .*/
436 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
437 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
438 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
439 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
440 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
441 /*description: .*/
442 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
443 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
444 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
445 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
446 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
447 /*description: .*/
448 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
449 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
450 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
451 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
452 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
453 /*description: .*/
454 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
455 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
456 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
457 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
458 /* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
459 /*description: .*/
460 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
461 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S))
462 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
463 #define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
464 
465 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x68)
466 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
467 /*description: .*/
468 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK    (BIT(0))
469 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_M  (BIT(0))
470 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_V  0x1
471 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK_S  0
472 
473 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x6C)
474 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
475 /*description: .*/
476 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
477 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
478 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
479 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
480 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
481 /*description: .*/
482 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
483 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
484 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
485 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
486 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
487 /*description: .*/
488 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
489 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S))
490 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
491 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_3_S  6
492 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
493 /*description: .*/
494 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
495 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S))
496 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
497 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_2_S  4
498 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
499 /*description: .*/
500 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
501 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S))
502 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
503 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_1_S  2
504 /* SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
505 /*description: .*/
506 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
507 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S))
508 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
509 #define SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_PMS_0_S  0
510 
511 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x70)
512 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
513 /*description: .*/
514 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK    (BIT(0))
515 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M  (BIT(0))
516 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V  0x1
517 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S  0
518 
519 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x74)
520 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
521 /*description: .*/
522 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
523 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
524 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
525 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
526 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
527 /*description: .*/
528 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
529 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
530 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
531 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
532 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
533 /*description: .*/
534 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
535 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S))
536 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
537 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_3_S  6
538 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
539 /*description: .*/
540 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
541 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S))
542 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
543 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_2_S  4
544 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
545 /*description: .*/
546 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
547 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S))
548 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
549 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_1_S  2
550 /* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
551 /*description: .*/
552 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
553 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S))
554 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
555 #define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_PMS_0_S  0
556 
557 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x78)
558 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
559 /*description: .*/
560 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK    (BIT(0))
561 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M  (BIT(0))
562 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V  0x1
563 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S  0
564 
565 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x7C)
566 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
567 /*description: .*/
568 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
569 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
570 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
571 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
572 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
573 /*description: .*/
574 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
575 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
576 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
577 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
578 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
579 /*description: .*/
580 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
581 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S))
582 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
583 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_3_S  6
584 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
585 /*description: .*/
586 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
587 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S))
588 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
589 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_2_S  4
590 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
591 /*description: .*/
592 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
593 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S))
594 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
595 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_1_S  2
596 /* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
597 /*description: .*/
598 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
599 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S))
600 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
601 #define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_PMS_0_S  0
602 
603 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x80)
604 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
605 /*description: .*/
606 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK    (BIT(0))
607 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
608 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V  0x1
609 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S  0
610 
611 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x84)
612 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
613 /*description: .*/
614 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
615 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
616 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
617 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
618 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
619 /*description: .*/
620 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
621 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
622 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
623 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
624 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
625 /*description: .*/
626 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
627 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S))
628 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
629 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
630 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
631 /*description: .*/
632 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
633 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S))
634 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
635 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
636 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
637 /*description: .*/
638 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
639 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S))
640 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
641 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
642 /* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
643 /*description: .*/
644 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
645 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S))
646 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
647 #define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
648 
649 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x88)
650 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
651 /*description: .*/
652 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK    (BIT(0))
653 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_M  (BIT(0))
654 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_V  0x1
655 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_LOCK_S  0
656 
657 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x8C)
658 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
659 /*description: .*/
660 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
661 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
662 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
663 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
664 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
665 /*description: .*/
666 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
667 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
668 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
669 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
670 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
671 /*description: .*/
672 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
673 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S))
674 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
675 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_3_S  6
676 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
677 /*description: .*/
678 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
679 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S))
680 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
681 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_2_S  4
682 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
683 /*description: .*/
684 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
685 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S))
686 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
687 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_1_S  2
688 /* SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
689 /*description: .*/
690 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
691 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S))
692 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
693 #define SENSITIVE_DMA_APBPERI_RMT_PMS_CONSTRAIN_SRAM_PMS_0_S  0
694 
695 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x90)
696 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
697 /*description: .*/
698 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK    (BIT(0))
699 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M  (BIT(0))
700 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V  0x1
701 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S  0
702 
703 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x94)
704 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
705 /*description: .*/
706 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
707 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
708 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
709 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
710 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
711 /*description: .*/
712 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
713 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
714 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
715 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
716 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
717 /*description: .*/
718 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
719 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S))
720 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
721 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_3_S  6
722 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
723 /*description: .*/
724 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
725 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S))
726 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
727 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_2_S  4
728 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
729 /*description: .*/
730 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
731 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S))
732 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
733 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_1_S  2
734 /* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
735 /*description: .*/
736 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
737 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S))
738 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
739 #define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_PMS_0_S  0
740 
741 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x98)
742 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
743 /*description: .*/
744 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK    (BIT(0))
745 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M  (BIT(0))
746 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V  0x1
747 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S  0
748 
749 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x9C)
750 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
751 /*description: .*/
752 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
753 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
754 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
755 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
756 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
757 /*description: .*/
758 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
759 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
760 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
761 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
762 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
763 /*description: .*/
764 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
765 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S))
766 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
767 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_3_S  6
768 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
769 /*description: .*/
770 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
771 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S))
772 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
773 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_2_S  4
774 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
775 /*description: .*/
776 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
777 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S))
778 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
779 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_1_S  2
780 /* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
781 /*description: .*/
782 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
783 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S))
784 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
785 #define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_PMS_0_S  0
786 
787 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA0)
788 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
789 /*description: .*/
790 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK    (BIT(0))
791 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M  (BIT(0))
792 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V  0x1
793 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S  0
794 
795 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xA4)
796 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
797 /*description: .*/
798 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
799 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
800 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
801 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
802 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
803 /*description: .*/
804 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
805 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
806 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
807 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
808 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
809 /*description: .*/
810 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
811 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S))
812 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
813 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_3_S  6
814 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
815 /*description: .*/
816 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
817 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S))
818 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
819 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_2_S  4
820 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
821 /*description: .*/
822 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
823 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S))
824 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
825 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_1_S  2
826 /* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
827 /*description: .*/
828 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
829 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S))
830 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
831 #define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_PMS_0_S  0
832 
833 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xA8)
834 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
835 /*description: .*/
836 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK    (BIT(0))
837 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_M  (BIT(0))
838 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_V  0x1
839 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_LOCK_S  0
840 
841 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xAC)
842 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
843 /*description: .*/
844 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1    0x00000003
845 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S))
846 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_V  0x3
847 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_1_S  10
848 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
849 /*description: .*/
850 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0    0x00000003
851 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S))
852 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_V  0x3
853 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_CACHEDATAARRAY_PMS_0_S  8
854 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
855 /*description: .*/
856 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3    0x00000003
857 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S))
858 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_V  0x3
859 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_3_S  6
860 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
861 /*description: .*/
862 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2    0x00000003
863 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S))
864 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_V  0x3
865 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_2_S  4
866 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
867 /*description: .*/
868 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1    0x00000003
869 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S))
870 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_V  0x3
871 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_1_S  2
872 /* SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
873 /*description: .*/
874 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0    0x00000003
875 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_M  ((SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V)<<(SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S))
876 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_V  0x3
877 #define SENSITIVE_DMA_APBPERI_SDIO_PMS_CONSTRAIN_SRAM_PMS_0_S  0
878 
879 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xB0)
880 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
881 /*description: .*/
882 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK    (BIT(0))
883 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M  (BIT(0))
884 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V  0x1
885 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S  0
886 
887 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xB4)
888 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
889 /*description: .*/
890 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN    (BIT(1))
891 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
892 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V  0x1
893 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S  1
894 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
895 /*description: .*/
896 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
897 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
898 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V  0x1
899 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S  0
900 
901 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xB8)
902 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[24:3] ;default: 22'b0 ; */
903 /*description: .*/
904 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
905 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
906 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
907 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  3
908 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */
909 /*description: .*/
910 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
911 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
912 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
913 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  1
914 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
915 /*description: .*/
916 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
917 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
918 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V  0x1
919 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S  0
920 
921 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0xBC)
922 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
923 /*description: .*/
924 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
925 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
926 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
927 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
928 /* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
929 /*description: .*/
930 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
931 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
932 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
933 #define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
934 
935 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xC0)
936 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
937 /*description: .*/
938 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK    (BIT(0))
939 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M  (BIT(0))
940 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V  0x1
941 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S  0
942 
943 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xC4)
944 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
945 /*description: .*/
946 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR    0x000000FF
947 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S))
948 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V  0xFF
949 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S  14
950 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
951 /*description: .*/
952 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6    0x00000003
953 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S))
954 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V  0x3
955 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S  12
956 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
957 /*description: .*/
958 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5    0x00000003
959 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S))
960 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V  0x3
961 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S  10
962 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
963 /*description: .*/
964 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4    0x00000003
965 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S))
966 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V  0x3
967 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S  8
968 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
969 /*description: .*/
970 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3    0x00000003
971 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S))
972 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V  0x3
973 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S  6
974 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
975 /*description: .*/
976 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2    0x00000003
977 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S))
978 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V  0x3
979 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S  4
980 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
981 /*description: .*/
982 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1    0x00000003
983 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S))
984 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V  0x3
985 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S  2
986 /* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
987 /*description: .*/
988 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0    0x00000003
989 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S))
990 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V  0x3
991 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S  0
992 
993 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xC8)
994 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
995 /*description: .*/
996 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR    0x000000FF
997 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S))
998 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V  0xFF
999 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S  14
1000 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
1001 /*description: .*/
1002 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6    0x00000003
1003 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S))
1004 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V  0x3
1005 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S  12
1006 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
1007 /*description: .*/
1008 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5    0x00000003
1009 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S))
1010 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V  0x3
1011 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S  10
1012 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
1013 /*description: .*/
1014 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4    0x00000003
1015 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S))
1016 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V  0x3
1017 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S  8
1018 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
1019 /*description: .*/
1020 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3    0x00000003
1021 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S))
1022 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V  0x3
1023 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S  6
1024 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
1025 /*description: .*/
1026 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2    0x00000003
1027 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S))
1028 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V  0x3
1029 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S  4
1030 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
1031 /*description: .*/
1032 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1    0x00000003
1033 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S))
1034 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V  0x3
1035 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S  2
1036 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
1037 /*description: .*/
1038 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0    0x00000003
1039 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S))
1040 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V  0x3
1041 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S  0
1042 
1043 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0xCC)
1044 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
1045 /*description: .*/
1046 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR    0x000000FF
1047 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S))
1048 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V  0xFF
1049 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S  14
1050 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
1051 /*description: .*/
1052 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6    0x00000003
1053 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S))
1054 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V  0x3
1055 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S  12
1056 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
1057 /*description: .*/
1058 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5    0x00000003
1059 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S))
1060 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V  0x3
1061 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S  10
1062 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
1063 /*description: .*/
1064 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4    0x00000003
1065 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S))
1066 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V  0x3
1067 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S  8
1068 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
1069 /*description: .*/
1070 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3    0x00000003
1071 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S))
1072 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V  0x3
1073 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S  6
1074 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
1075 /*description: .*/
1076 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2    0x00000003
1077 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S))
1078 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V  0x3
1079 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S  4
1080 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
1081 /*description: .*/
1082 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1    0x00000003
1083 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S))
1084 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V  0x3
1085 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S  2
1086 /* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
1087 /*description: .*/
1088 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0    0x00000003
1089 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S))
1090 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V  0x3
1091 #define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S  0
1092 
1093 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0xD0)
1094 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
1095 /*description: .*/
1096 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR    0x000000FF
1097 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S))
1098 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V  0xFF
1099 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S  14
1100 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
1101 /*description: .*/
1102 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6    0x00000003
1103 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S))
1104 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V  0x3
1105 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S  12
1106 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
1107 /*description: .*/
1108 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5    0x00000003
1109 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S))
1110 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V  0x3
1111 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S  10
1112 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
1113 /*description: .*/
1114 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4    0x00000003
1115 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S))
1116 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V  0x3
1117 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S  8
1118 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
1119 /*description: .*/
1120 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3    0x00000003
1121 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S))
1122 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V  0x3
1123 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S  6
1124 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
1125 /*description: .*/
1126 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2    0x00000003
1127 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S))
1128 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V  0x3
1129 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S  4
1130 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
1131 /*description: .*/
1132 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1    0x00000003
1133 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S))
1134 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V  0x3
1135 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S  2
1136 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
1137 /*description: .*/
1138 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0    0x00000003
1139 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S))
1140 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V  0x3
1141 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S  0
1142 
1143 #define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0xD4)
1144 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[21:14] ;default: 8'b0 ; */
1145 /*description: .*/
1146 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR    0x000000FF
1147 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S))
1148 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V  0xFF
1149 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S  14
1150 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
1151 /*description: .*/
1152 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6    0x00000003
1153 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S))
1154 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V  0x3
1155 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S  12
1156 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
1157 /*description: .*/
1158 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5    0x00000003
1159 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S))
1160 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V  0x3
1161 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S  10
1162 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
1163 /*description: .*/
1164 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4    0x00000003
1165 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S))
1166 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V  0x3
1167 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S  8
1168 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
1169 /*description: .*/
1170 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3    0x00000003
1171 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S))
1172 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V  0x3
1173 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S  6
1174 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
1175 /*description: .*/
1176 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2    0x00000003
1177 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S))
1178 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V  0x3
1179 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S  4
1180 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
1181 /*description: .*/
1182 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1    0x00000003
1183 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S))
1184 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V  0x3
1185 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S  2
1186 /* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
1187 /*description: .*/
1188 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0    0x00000003
1189 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M  ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V)<<(SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S))
1190 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V  0x3
1191 #define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S  0
1192 
1193 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xD8)
1194 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1195 /*description: .*/
1196 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
1197 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
1198 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V  0x1
1199 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S  0
1200 
1201 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0xDC)
1202 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
1203 /*description: .*/
1204 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000007
1205 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
1206 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x7
1207 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  18
1208 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */
1209 /*description: .*/
1210 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1    0x00000007
1211 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S))
1212 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V  0x7
1213 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S  15
1214 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
1215 /*description: .*/
1216 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000007
1217 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
1218 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x7
1219 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  12
1220 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
1221 /*description: .*/
1222 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000007
1223 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
1224 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x7
1225 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  9
1226 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
1227 /*description: .*/
1228 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000007
1229 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
1230 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x7
1231 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  6
1232 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
1233 /*description: .*/
1234 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000007
1235 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
1236 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x7
1237 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  3
1238 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
1239 /*description: .*/
1240 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000007
1241 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
1242 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x7
1243 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  0
1244 
1245 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0xE0)
1246 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */
1247 /*description: .*/
1248 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000007
1249 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
1250 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x7
1251 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  18
1252 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */
1253 /*description: .*/
1254 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1    0x00000007
1255 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S))
1256 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V  0x7
1257 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S  15
1258 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */
1259 /*description: .*/
1260 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000007
1261 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
1262 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x7
1263 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  12
1264 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
1265 /*description: .*/
1266 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000007
1267 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
1268 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x7
1269 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  9
1270 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
1271 /*description: .*/
1272 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000007
1273 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
1274 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x7
1275 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  6
1276 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
1277 /*description: .*/
1278 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000007
1279 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
1280 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x7
1281 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  3
1282 /* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
1283 /*description: .*/
1284 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000007
1285 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
1286 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x7
1287 #define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
1288 
1289 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xE4)
1290 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1291 /*description: .*/
1292 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
1293 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
1294 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V  0x1
1295 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S  0
1296 
1297 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xE8)
1298 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
1299 /*description: .*/
1300 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
1301 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
1302 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
1303 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
1304 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
1305 /*description: .*/
1306 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
1307 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
1308 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
1309 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
1310 
1311 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xEC)
1312 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
1313 /*description: .*/
1314 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
1315 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
1316 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
1317 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
1318 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
1319 /*description: .*/
1320 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
1321 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
1322 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
1323 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
1324 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
1325 /*description: .*/
1326 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
1327 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
1328 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
1329 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
1330 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
1331 /*description: .*/
1332 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
1333 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
1334 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
1335 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
1336 /* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
1337 /*description: .*/
1338 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
1339 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
1340 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
1341 #define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
1342 
1343 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0xF0)
1344 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1345 /*description: .*/
1346 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK    (BIT(0))
1347 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
1348 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V  0x1
1349 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S  0
1350 
1351 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0xF4)
1352 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
1353 /*description: .*/
1354 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
1355 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
1356 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
1357 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S  1
1358 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
1359 /*description: .*/
1360 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
1361 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
1362 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
1363 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
1364 
1365 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0xF8)
1366 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */
1367 /*description: .*/
1368 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x00FFFFFF
1369 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
1370 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0xFFFFFF
1371 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  5
1372 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
1373 /*description: .*/
1374 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
1375 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
1376 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
1377 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  3
1378 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */
1379 /*description: .*/
1380 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE    (BIT(2))
1381 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M  (BIT(2))
1382 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V  0x1
1383 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S  2
1384 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */
1385 /*description: .*/
1386 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(1))
1387 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(1))
1388 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
1389 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  1
1390 /* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
1391 /*description: .*/
1392 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
1393 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
1394 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
1395 #define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
1396 
1397 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0xFC)
1398 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1399 /*description: .*/
1400 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK    (BIT(0))
1401 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M  (BIT(0))
1402 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V  0x1
1403 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S  0
1404 
1405 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x100)
1406 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
1407 /*description: .*/
1408 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS    0x00000003
1409 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S))
1410 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V  0x3
1411 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S  26
1412 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
1413 /*description: .*/
1414 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS    0x00000003
1415 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S))
1416 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V  0x3
1417 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S  24
1418 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
1419 /*description: .*/
1420 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1    0x00000003
1421 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S))
1422 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V  0x3
1423 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S  22
1424 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
1425 /*description: .*/
1426 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0    0x00000003
1427 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S))
1428 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V  0x3
1429 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S  20
1430 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
1431 /*description: .*/
1432 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3    0x00000003
1433 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S))
1434 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V  0x3
1435 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S  18
1436 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
1437 /*description: .*/
1438 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2    0x00000003
1439 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S))
1440 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V  0x3
1441 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S  16
1442 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
1443 /*description: .*/
1444 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1    0x00000003
1445 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S))
1446 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V  0x3
1447 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S  14
1448 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
1449 /*description: .*/
1450 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0    0x00000003
1451 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S))
1452 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V  0x3
1453 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S  12
1454 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
1455 /*description: .*/
1456 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1    0x00000003
1457 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S))
1458 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V  0x3
1459 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S  10
1460 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
1461 /*description: .*/
1462 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0    0x00000003
1463 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S))
1464 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V  0x3
1465 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S  8
1466 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
1467 /*description: .*/
1468 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3    0x00000003
1469 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S))
1470 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V  0x3
1471 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S  6
1472 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
1473 /*description: .*/
1474 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2    0x00000003
1475 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S))
1476 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V  0x3
1477 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S  4
1478 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
1479 /*description: .*/
1480 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1    0x00000003
1481 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S))
1482 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V  0x3
1483 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S  2
1484 /* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
1485 /*description: .*/
1486 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0    0x00000003
1487 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M  ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V)<<(SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S))
1488 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V  0x3
1489 #define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S  0
1490 
1491 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x104)
1492 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1493 /*description: .*/
1494 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
1495 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
1496 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V  0x1
1497 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S  0
1498 
1499 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x108)
1500 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
1501 /*description: .*/
1502 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
1503 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
1504 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
1505 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
1506 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
1507 /*description: .*/
1508 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
1509 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
1510 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
1511 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
1512 
1513 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x10C)
1514 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */
1515 /*description: .*/
1516 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
1517 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
1518 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
1519 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
1520 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
1521 /*description: .*/
1522 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
1523 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
1524 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
1525 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
1526 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
1527 /*description: .*/
1528 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
1529 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
1530 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
1531 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
1532 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
1533 /*description: .*/
1534 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
1535 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
1536 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
1537 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
1538 
1539 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x110)
1540 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
1541 /*description: .*/
1542 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
1543 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
1544 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
1545 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
1546 /* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
1547 /*description: .*/
1548 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
1549 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
1550 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
1551 #define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
1552 
1553 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x114)
1554 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1555 /*description: .*/
1556 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK    (BIT(0))
1557 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M  (BIT(0))
1558 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V  0x1
1559 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S  0
1560 
1561 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x118)
1562 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
1563 /*description: .*/
1564 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN    (BIT(1))
1565 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
1566 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V  0x1
1567 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S  1
1568 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
1569 /*description: .*/
1570 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
1571 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
1572 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V  0x1
1573 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S  0
1574 
1575 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x11C)
1576 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */
1577 /*description: .*/
1578 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR    0x003FFFFF
1579 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S))
1580 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V  0x3FFFFF
1581 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S  4
1582 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */
1583 /*description: .*/
1584 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD    0x00000003
1585 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S))
1586 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V  0x3
1587 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S  2
1588 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */
1589 /*description: .*/
1590 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK    (BIT(1))
1591 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M  (BIT(1))
1592 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V  0x1
1593 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S  1
1594 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
1595 /*description: .*/
1596 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
1597 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
1598 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V  0x1
1599 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S  0
1600 
1601 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x120)
1602 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */
1603 /*description: .*/
1604 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN    0x0000FFFF
1605 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M  ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V)<<(SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S))
1606 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V  0xFFFF
1607 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S  1
1608 /* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */
1609 /*description: .*/
1610 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR    (BIT(0))
1611 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M  (BIT(0))
1612 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V  0x1
1613 #define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S  0
1614 
1615 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x124)
1616 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
1617 /*description: .*/
1618 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
1619 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
1620 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V  0x1
1621 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S  0
1622 
1623 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x128)
1624 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
1625 /*description: .*/
1626 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
1627 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
1628 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
1629 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
1630 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
1631 /*description: .*/
1632 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0    0x00000003
1633 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
1634 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
1635 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  28
1636 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
1637 /*description: .*/
1638 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
1639 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
1640 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
1641 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
1642 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
1643 /*description: .*/
1644 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
1645 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
1646 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
1647 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
1648 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
1649 /*description: .*/
1650 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF    0x00000003
1651 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
1652 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V  0x3
1653 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S  20
1654 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
1655 /*description: .*/
1656 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
1657 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
1658 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
1659 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
1660 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
1661 /*description: .*/
1662 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
1663 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
1664 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
1665 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
1666 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
1667 /*description: .*/
1668 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
1669 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
1670 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
1671 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
1672 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
1673 /*description: .*/
1674 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2    0x00000003
1675 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
1676 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
1677 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
1678 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
1679 /*description: .*/
1680 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
1681 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
1682 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
1683 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
1684 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
1685 /*description: .*/
1686 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
1687 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
1688 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
1689 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
1690 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
1691 /*description: .*/
1692 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
1693 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
1694 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
1695 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
1696 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
1697 /*description: .*/
1698 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
1699 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
1700 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
1701 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
1702 
1703 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x12C)
1704 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
1705 /*description: .*/
1706 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
1707 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
1708 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
1709 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
1710 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
1711 /*description: .*/
1712 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
1713 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
1714 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
1715 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
1716 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
1717 /*description: .*/
1718 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
1719 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
1720 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
1721 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
1722 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
1723 /*description: .*/
1724 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0    0x00000003
1725 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S))
1726 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V  0x3
1727 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S  24
1728 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
1729 /*description: .*/
1730 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB    0x00000003
1731 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
1732 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
1733 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
1734 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
1735 /*description: .*/
1736 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP    0x00000003
1737 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
1738 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V  0x3
1739 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S  18
1740 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
1741 /*description: .*/
1742 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
1743 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
1744 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
1745 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
1746 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
1747 /*description: .*/
1748 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC    0x00000003
1749 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S))
1750 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V  0x3
1751 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S  14
1752 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
1753 /*description: .*/
1754 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT    0x00000003
1755 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
1756 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V  0x3
1757 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S  12
1758 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
1759 /*description: .*/
1760 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
1761 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
1762 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
1763 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
1764 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
1765 /*description: .*/
1766 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST    0x00000003
1767 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S))
1768 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V  0x3
1769 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S  8
1770 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
1771 /*description: .*/
1772 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
1773 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
1774 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
1775 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
1776 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
1777 /*description: .*/
1778 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
1779 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
1780 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
1781 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
1782 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
1783 /*description: .*/
1784 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
1785 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
1786 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
1787 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
1788 
1789 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x130)
1790 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
1791 /*description: .*/
1792 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR    0x00000003
1793 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
1794 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
1795 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
1796 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
1797 /*description: .*/
1798 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC    0x00000003
1799 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
1800 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
1801 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
1802 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
1803 /*description: .*/
1804 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
1805 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
1806 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
1807 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
1808 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
1809 /*description: .*/
1810 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2    0x00000003
1811 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
1812 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V  0x3
1813 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S  16
1814 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
1815 /*description: .*/
1816 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
1817 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
1818 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
1819 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
1820 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
1821 /*description: .*/
1822 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1    0x00000003
1823 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S))
1824 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V  0x3
1825 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S  12
1826 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
1827 /*description: .*/
1828 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
1829 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
1830 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
1831 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
1832 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
1833 /*description: .*/
1834 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST    0x00000003
1835 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S))
1836 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V  0x3
1837 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S  8
1838 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
1839 /*description: .*/
1840 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1    0x00000003
1841 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S))
1842 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V  0x3
1843 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S  6
1844 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
1845 /*description: .*/
1846 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
1847 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
1848 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
1849 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
1850 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
1851 /*description: .*/
1852 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3    0x00000003
1853 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S))
1854 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V  0x3
1855 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S  2
1856 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
1857 /*description: .*/
1858 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
1859 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
1860 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
1861 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
1862 
1863 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x134)
1864 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
1865 /*description: .*/
1866 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
1867 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
1868 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
1869 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
1870 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
1871 /*description: .*/
1872 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
1873 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
1874 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
1875 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
1876 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
1877 /*description: .*/
1878 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
1879 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
1880 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
1881 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
1882 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
1883 /*description: .*/
1884 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
1885 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
1886 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
1887 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
1888 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
1889 /*description: .*/
1890 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
1891 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
1892 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
1893 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
1894 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
1895 /*description: .*/
1896 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
1897 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
1898 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
1899 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
1900 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
1901 /*description: .*/
1902 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
1903 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
1904 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
1905 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
1906 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
1907 /*description: .*/
1908 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
1909 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
1910 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
1911 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
1912 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
1913 /*description: .*/
1914 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB    0x00000003
1915 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S))
1916 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V  0x3
1917 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S  14
1918 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
1919 /*description: .*/
1920 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR    0x00000003
1921 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
1922 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
1923 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
1924 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
1925 /*description: .*/
1926 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM    0x00000003
1927 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S))
1928 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V  0x3
1929 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S  10
1930 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
1931 /*description: .*/
1932 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
1933 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
1934 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
1935 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
1936 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
1937 /*description: .*/
1938 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
1939 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
1940 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
1941 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
1942 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
1943 /*description: .*/
1944 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
1945 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
1946 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
1947 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
1948 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
1949 /*description: .*/
1950 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP    0x00000003
1951 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
1952 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
1953 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
1954 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
1955 /*description: .*/
1956 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
1957 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
1958 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
1959 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  0
1960 
1961 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x138)
1962 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
1963 /*description: .*/
1964 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
1965 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
1966 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
1967 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
1968 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
1969 /*description: .*/
1970 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0    0x00000003
1971 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
1972 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
1973 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  28
1974 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
1975 /*description: .*/
1976 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
1977 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
1978 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
1979 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
1980 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
1981 /*description: .*/
1982 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
1983 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
1984 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
1985 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
1986 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
1987 /*description: .*/
1988 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF    0x00000003
1989 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S))
1990 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V  0x3
1991 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S  20
1992 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
1993 /*description: .*/
1994 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
1995 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
1996 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
1997 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
1998 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
1999 /*description: .*/
2000 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
2001 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
2002 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
2003 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
2004 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2005 /*description: .*/
2006 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
2007 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
2008 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
2009 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
2010 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2011 /*description: .*/
2012 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2    0x00000003
2013 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
2014 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
2015 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
2016 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2017 /*description: .*/
2018 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
2019 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
2020 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
2021 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
2022 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2023 /*description: .*/
2024 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
2025 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
2026 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
2027 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
2028 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
2029 /*description: .*/
2030 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
2031 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
2032 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
2033 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
2034 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2035 /*description: .*/
2036 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
2037 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
2038 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
2039 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
2040 
2041 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x13C)
2042 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
2043 /*description: .*/
2044 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
2045 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
2046 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
2047 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
2048 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
2049 /*description: .*/
2050 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
2051 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
2052 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
2053 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
2054 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
2055 /*description: .*/
2056 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
2057 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
2058 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
2059 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
2060 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
2061 /*description: .*/
2062 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0    0x00000003
2063 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S))
2064 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V  0x3
2065 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S  24
2066 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
2067 /*description: .*/
2068 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB    0x00000003
2069 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
2070 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
2071 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
2072 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
2073 /*description: .*/
2074 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP    0x00000003
2075 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S))
2076 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V  0x3
2077 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S  18
2078 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2079 /*description: .*/
2080 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
2081 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
2082 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
2083 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
2084 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2085 /*description: .*/
2086 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC    0x00000003
2087 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S))
2088 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V  0x3
2089 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S  14
2090 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
2091 /*description: .*/
2092 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT    0x00000003
2093 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S))
2094 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V  0x3
2095 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S  12
2096 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2097 /*description: .*/
2098 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
2099 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
2100 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
2101 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
2102 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2103 /*description: .*/
2104 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST    0x00000003
2105 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S))
2106 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V  0x3
2107 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S  8
2108 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2109 /*description: .*/
2110 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
2111 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
2112 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
2113 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
2114 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2115 /*description: .*/
2116 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
2117 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
2118 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
2119 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
2120 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2121 /*description: .*/
2122 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
2123 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
2124 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
2125 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
2126 
2127 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x140)
2128 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
2129 /*description: .*/
2130 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR    0x00000003
2131 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
2132 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
2133 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
2134 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
2135 /*description: .*/
2136 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC    0x00000003
2137 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
2138 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
2139 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
2140 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
2141 /*description: .*/
2142 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
2143 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
2144 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
2145 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
2146 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2147 /*description: .*/
2148 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2    0x00000003
2149 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S))
2150 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V  0x3
2151 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S  16
2152 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2153 /*description: .*/
2154 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
2155 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
2156 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
2157 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
2158 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
2159 /*description: .*/
2160 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1    0x00000003
2161 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S))
2162 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V  0x3
2163 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S  12
2164 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2165 /*description: .*/
2166 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
2167 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
2168 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
2169 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
2170 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2171 /*description: .*/
2172 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST    0x00000003
2173 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S))
2174 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V  0x3
2175 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S  8
2176 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2177 /*description: .*/
2178 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1    0x00000003
2179 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S))
2180 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V  0x3
2181 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S  6
2182 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2183 /*description: .*/
2184 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
2185 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
2186 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
2187 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
2188 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
2189 /*description: .*/
2190 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3    0x00000003
2191 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S))
2192 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V  0x3
2193 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S  2
2194 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2195 /*description: .*/
2196 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
2197 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
2198 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
2199 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
2200 
2201 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x144)
2202 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
2203 /*description: .*/
2204 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
2205 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
2206 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
2207 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
2208 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
2209 /*description: .*/
2210 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
2211 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
2212 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
2213 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
2214 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
2215 /*description: .*/
2216 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
2217 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
2218 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
2219 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
2220 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
2221 /*description: .*/
2222 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
2223 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
2224 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
2225 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
2226 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
2227 /*description: .*/
2228 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
2229 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
2230 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
2231 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
2232 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
2233 /*description: .*/
2234 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
2235 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
2236 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
2237 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
2238 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
2239 /*description: .*/
2240 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
2241 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
2242 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
2243 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
2244 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2245 /*description: .*/
2246 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
2247 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
2248 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
2249 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
2250 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2251 /*description: .*/
2252 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB    0x00000003
2253 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S))
2254 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V  0x3
2255 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S  14
2256 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
2257 /*description: .*/
2258 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR    0x00000003
2259 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
2260 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
2261 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
2262 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2263 /*description: .*/
2264 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM    0x00000003
2265 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S))
2266 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V  0x3
2267 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S  10
2268 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2269 /*description: .*/
2270 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
2271 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
2272 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
2273 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
2274 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2275 /*description: .*/
2276 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
2277 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
2278 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
2279 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
2280 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2281 /*description: .*/
2282 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
2283 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
2284 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
2285 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
2286 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
2287 /*description: .*/
2288 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP    0x00000003
2289 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
2290 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
2291 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
2292 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2293 /*description: .*/
2294 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
2295 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
2296 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
2297 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  0
2298 
2299 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x148)
2300 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
2301 /*description: .*/
2302 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
2303 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
2304 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
2305 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
2306 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
2307 /*description: .*/
2308 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
2309 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
2310 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
2311 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
2312 
2313 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x14C)
2314 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
2315 /*description: .*/
2316 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
2317 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
2318 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
2319 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
2320 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
2321 /*description: .*/
2322 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
2323 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
2324 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
2325 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
2326 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
2327 /*description: .*/
2328 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
2329 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
2330 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
2331 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
2332 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
2333 /*description: .*/
2334 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
2335 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
2336 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
2337 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
2338 
2339 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x150)
2340 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
2341 /*description: .*/
2342 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1    0x000007FF
2343 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S))
2344 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V  0x7FF
2345 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S  11
2346 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
2347 /*description: .*/
2348 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0    0x000007FF
2349 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
2350 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V  0x7FF
2351 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S  0
2352 
2353 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x154)
2354 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
2355 /*description: .*/
2356 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H    0x00000007
2357 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S))
2358 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V  0x7
2359 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S  9
2360 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
2361 /*description: .*/
2362 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L    0x00000007
2363 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
2364 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V  0x7
2365 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S  6
2366 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
2367 /*description: .*/
2368 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H    0x00000007
2369 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S))
2370 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V  0x7
2371 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S  3
2372 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
2373 /*description: .*/
2374 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L    0x00000007
2375 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
2376 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V  0x7
2377 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S  0
2378 
2379 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x158)
2380 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
2381 /*description: .*/
2382 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1    0x000007FF
2383 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S))
2384 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V  0x7FF
2385 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S  11
2386 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
2387 /*description: .*/
2388 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0    0x000007FF
2389 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
2390 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V  0x7FF
2391 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S  0
2392 
2393 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x15C)
2394 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
2395 /*description: .*/
2396 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H    0x00000007
2397 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S))
2398 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V  0x7
2399 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S  9
2400 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
2401 /*description: .*/
2402 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L    0x00000007
2403 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
2404 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V  0x7
2405 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S  6
2406 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
2407 /*description: .*/
2408 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H    0x00000007
2409 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S))
2410 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V  0x7
2411 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S  3
2412 /* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
2413 /*description: .*/
2414 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L    0x00000007
2415 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M  ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
2416 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V  0x7
2417 #define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S  0
2418 
2419 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x160)
2420 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
2421 /*description: .*/
2422 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
2423 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
2424 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_V  0x1
2425 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_LOCK_S  0
2426 
2427 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x164)
2428 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
2429 /*description: .*/
2430 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10    0x00000003
2431 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
2432 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V  0x3
2433 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S  20
2434 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
2435 /*description: .*/
2436 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9    0x00000003
2437 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S))
2438 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V  0x3
2439 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S  18
2440 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2441 /*description: .*/
2442 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8    0x00000003
2443 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
2444 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V  0x3
2445 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S  16
2446 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2447 /*description: .*/
2448 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7    0x00000003
2449 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S))
2450 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V  0x3
2451 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S  14
2452 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
2453 /*description: .*/
2454 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
2455 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
2456 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
2457 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
2458 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2459 /*description: .*/
2460 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
2461 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
2462 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
2463 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
2464 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2465 /*description: .*/
2466 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
2467 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
2468 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
2469 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
2470 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2471 /*description: .*/
2472 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
2473 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
2474 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
2475 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
2476 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2477 /*description: .*/
2478 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
2479 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
2480 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
2481 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
2482 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
2483 /*description: .*/
2484 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
2485 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
2486 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
2487 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
2488 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2489 /*description: .*/
2490 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
2491 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
2492 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
2493 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
2494 
2495 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x168)
2496 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
2497 /*description: .*/
2498 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10    0x00000003
2499 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S))
2500 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V  0x3
2501 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S  20
2502 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
2503 /*description: .*/
2504 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9    0x00000003
2505 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
2506 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V  0x3
2507 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S  18
2508 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2509 /*description: .*/
2510 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8    0x00000003
2511 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S))
2512 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V  0x3
2513 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S  16
2514 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2515 /*description: .*/
2516 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7    0x00000003
2517 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
2518 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V  0x3
2519 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S  14
2520 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
2521 /*description: .*/
2522 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
2523 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
2524 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
2525 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
2526 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2527 /*description: .*/
2528 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
2529 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
2530 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
2531 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
2532 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2533 /*description: .*/
2534 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
2535 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
2536 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
2537 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
2538 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2539 /*description: .*/
2540 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
2541 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
2542 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
2543 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
2544 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2545 /*description: .*/
2546 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
2547 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
2548 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
2549 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
2550 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
2551 /*description: .*/
2552 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
2553 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
2554 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
2555 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
2556 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2557 /*description: .*/
2558 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
2559 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
2560 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
2561 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
2562 
2563 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x16C)
2564 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2565 /*description: .*/
2566 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
2567 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S))
2568 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
2569 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_0_S  0
2570 
2571 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x170)
2572 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2573 /*description: .*/
2574 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
2575 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S))
2576 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
2577 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_1_S  0
2578 
2579 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x174)
2580 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2581 /*description: .*/
2582 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
2583 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S))
2584 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
2585 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_2_S  0
2586 
2587 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x178)
2588 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2589 /*description: .*/
2590 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
2591 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S))
2592 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
2593 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_3_S  0
2594 
2595 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x17C)
2596 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2597 /*description: .*/
2598 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
2599 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S))
2600 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
2601 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_4_S  0
2602 
2603 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x180)
2604 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2605 /*description: .*/
2606 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
2607 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S))
2608 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
2609 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_5_S  0
2610 
2611 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x184)
2612 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2613 /*description: .*/
2614 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
2615 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S))
2616 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
2617 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_6_S  0
2618 
2619 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x188)
2620 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2621 /*description: .*/
2622 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
2623 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S))
2624 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
2625 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_7_S  0
2626 
2627 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x18C)
2628 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2629 /*description: .*/
2630 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8    0x3FFFFFFF
2631 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S))
2632 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_V  0x3FFFFFFF
2633 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_8_S  0
2634 
2635 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x190)
2636 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2637 /*description: .*/
2638 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9    0x3FFFFFFF
2639 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S))
2640 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_V  0x3FFFFFFF
2641 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_9_S  0
2642 
2643 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x194)
2644 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2645 /*description: .*/
2646 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10    0x3FFFFFFF
2647 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S))
2648 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_V  0x3FFFFFFF
2649 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_10_S  0
2650 
2651 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x198)
2652 /* SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
2653 /*description: .*/
2654 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11    0x3FFFFFFF
2655 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_M  ((SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S))
2656 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_V  0x3FFFFFFF
2657 #define SENSITIVE_CORE_0_REGION_PMS_CONSTRAIN_ADDR_11_S  0
2658 
2659 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x19C)
2660 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
2661 /*description: .*/
2662 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK    (BIT(0))
2663 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
2664 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V  0x1
2665 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S  0
2666 
2667 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x1A0)
2668 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
2669 /*description: .*/
2670 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
2671 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
2672 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
2673 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S  1
2674 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
2675 /*description: .*/
2676 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
2677 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
2678 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
2679 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
2680 
2681 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x1A4)
2682 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
2683 /*description: .*/
2684 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
2685 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
2686 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
2687 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
2688 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
2689 /*description: .*/
2690 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
2691 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
2692 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
2693 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
2694 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
2695 /*description: .*/
2696 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
2697 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
2698 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
2699 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
2700 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
2701 /*description: .*/
2702 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
2703 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
2704 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
2705 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
2706 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
2707 /*description: .*/
2708 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
2709 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
2710 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
2711 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
2712 
2713 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x1A8)
2714 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2715 /*description: .*/
2716 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
2717 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
2718 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
2719 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
2720 
2721 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x1AC)
2722 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
2723 /*description: .*/
2724 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
2725 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
2726 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
2727 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
2728 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
2729 /*description: .*/
2730 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
2731 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
2732 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
2733 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
2734 
2735 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x1B0)
2736 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
2737 /*description: .*/
2738 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
2739 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
2740 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
2741 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
2742 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
2743 /*description: .*/
2744 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
2745 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
2746 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
2747 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
2748 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
2749 /*description: .*/
2750 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
2751 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
2752 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
2753 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
2754 
2755 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x1B4)
2756 /* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
2757 /*description: .*/
2758 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
2759 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
2760 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
2761 #define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
2762 
2763 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x1B8)
2764 /* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
2765 /*description: .*/
2766 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK    (BIT(0))
2767 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M  (BIT(0))
2768 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V  0x1
2769 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S  0
2770 
2771 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x1BC)
2772 /* SENSITIVE_CORE_0_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
2773 /*description: .*/
2774 #define SENSITIVE_CORE_0_VECBASE_WORLD_MASK    (BIT(0))
2775 #define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_M  (BIT(0))
2776 #define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_V  0x1
2777 #define SENSITIVE_CORE_0_VECBASE_WORLD_MASK_S  0
2778 
2779 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1C0)
2780 /* SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
2781 /*description: .*/
2782 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL    0x00000003
2783 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S))
2784 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V  0x3
2785 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S  22
2786 /* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
2787 /*description: .*/
2788 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE    0x003FFFFF
2789 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S))
2790 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_V  0x3FFFFF
2791 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD0_VALUE_S  0
2792 
2793 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_2_REG          (DR_REG_SENSITIVE_BASE + 0x1C4)
2794 /* SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
2795 /*description: .*/
2796 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE    0x003FFFFF
2797 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_M  ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S))
2798 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_V  0x3FFFFF
2799 #define SENSITIVE_CORE_0_VECBASE_OVERRIDE_WORLD1_VALUE_S  0
2800 
2801 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x1C8)
2802 /* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
2803 /*description: .*/
2804 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK    (BIT(0))
2805 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M  (BIT(0))
2806 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V  0x1
2807 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S  0
2808 
2809 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x1CC)
2810 /* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */
2811 /*description: .*/
2812 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE    (BIT(0))
2813 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M  (BIT(0))
2814 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V  0x1
2815 #define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S  0
2816 
2817 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x1D0)
2818 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
2819 /*description: .*/
2820 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK    (BIT(0))
2821 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M  (BIT(0))
2822 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V  0x1
2823 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S  0
2824 
2825 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x1D4)
2826 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
2827 /*description: .*/
2828 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1    0x00000003
2829 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S))
2830 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V  0x3
2831 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S  30
2832 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
2833 /*description: .*/
2834 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0    0x00000003
2835 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S))
2836 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V  0x3
2837 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S  28
2838 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
2839 /*description: .*/
2840 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C    0x00000003
2841 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S))
2842 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V  0x3
2843 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S  26
2844 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
2845 /*description: .*/
2846 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC    0x00000003
2847 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S))
2848 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V  0x3
2849 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S  24
2850 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
2851 /*description: .*/
2852 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF    0x00000003
2853 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S))
2854 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V  0x3
2855 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S  20
2856 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2857 /*description: .*/
2858 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX    0x00000003
2859 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S))
2860 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V  0x3
2861 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S  16
2862 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2863 /*description: .*/
2864 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC    0x00000003
2865 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S))
2866 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_V  0x3
2867 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_S  14
2868 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2869 /*description: .*/
2870 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE    0x00000003
2871 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S))
2872 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V  0x3
2873 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S  10
2874 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2875 /*description: .*/
2876 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2    0x00000003
2877 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S))
2878 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V  0x3
2879 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S  8
2880 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2881 /*description: .*/
2882 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO    0x00000003
2883 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S))
2884 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V  0x3
2885 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S  6
2886 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2887 /*description: .*/
2888 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0    0x00000003
2889 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S))
2890 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V  0x3
2891 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S  4
2892 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
2893 /*description: .*/
2894 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1    0x00000003
2895 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S))
2896 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V  0x3
2897 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S  2
2898 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2899 /*description: .*/
2900 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART    0x00000003
2901 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S))
2902 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V  0x3
2903 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S  0
2904 
2905 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x1D8)
2906 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
2907 /*description: .*/
2908 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER    0x00000003
2909 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S))
2910 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V  0x3
2911 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S  30
2912 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
2913 /*description: .*/
2914 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1    0x00000003
2915 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S))
2916 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V  0x3
2917 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S  28
2918 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
2919 /*description: .*/
2920 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP    0x00000003
2921 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S))
2922 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V  0x3
2923 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S  26
2924 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
2925 /*description: .*/
2926 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0    0x00000003
2927 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S))
2928 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V  0x3
2929 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S  24
2930 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
2931 /*description: .*/
2932 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB    0x00000003
2933 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S))
2934 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V  0x3
2935 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S  22
2936 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
2937 /*description: .*/
2938 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP    0x00000003
2939 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S))
2940 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_V  0x3
2941 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BACKUP_S  18
2942 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
2943 /*description: .*/
2944 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC    0x00000003
2945 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S))
2946 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V  0x3
2947 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S  16
2948 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
2949 /*description: .*/
2950 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC    0x00000003
2951 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S))
2952 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V  0x3
2953 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S  14
2954 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
2955 /*description: .*/
2956 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT    0x00000003
2957 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S))
2958 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V  0x3
2959 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S  12
2960 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
2961 /*description: .*/
2962 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT    0x00000003
2963 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S))
2964 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V  0x3
2965 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S  10
2966 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
2967 /*description: .*/
2968 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST    0x00000003
2969 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S))
2970 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V  0x3
2971 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S  8
2972 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
2973 /*description: .*/
2974 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0    0x00000003
2975 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S))
2976 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V  0x3
2977 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S  6
2978 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
2979 /*description: .*/
2980 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0    0x00000003
2981 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S))
2982 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V  0x3
2983 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S  4
2984 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
2985 /*description: .*/
2986 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT    0x00000003
2987 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S))
2988 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V  0x3
2989 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S  0
2990 
2991 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x1DC)
2992 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
2993 /*description: .*/
2994 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR    0x00000003
2995 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S))
2996 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V  0x3
2997 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S  28
2998 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
2999 /*description: .*/
3000 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC    0x00000003
3001 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S))
3002 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V  0x3
3003 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S  26
3004 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
3005 /*description: .*/
3006 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT    0x00000003
3007 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S))
3008 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V  0x3
3009 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S  22
3010 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3011 /*description: .*/
3012 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2    0x00000003
3013 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S))
3014 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V  0x3
3015 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S  16
3016 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3017 /*description: .*/
3018 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1    0x00000003
3019 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S))
3020 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V  0x3
3021 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S  14
3022 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3023 /*description: .*/
3024 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1    0x00000003
3025 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S))
3026 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V  0x3
3027 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S  12
3028 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3029 /*description: .*/
3030 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN    0x00000003
3031 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S))
3032 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_V  0x3
3033 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN_S  10
3034 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3035 /*description: .*/
3036 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST    0x00000003
3037 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S))
3038 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V  0x3
3039 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S  8
3040 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3041 /*description: .*/
3042 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1    0x00000003
3043 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S))
3044 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V  0x3
3045 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S  6
3046 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3047 /*description: .*/
3048 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL    0x00000003
3049 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S))
3050 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V  0x3
3051 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S  4
3052 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3053 /*description: .*/
3054 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3    0x00000003
3055 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S))
3056 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V  0x3
3057 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S  2
3058 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3059 /*description: .*/
3060 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2    0x00000003
3061 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S))
3062 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V  0x3
3063 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S  0
3064 
3065 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x1E0)
3066 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
3067 /*description: .*/
3068 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER    0x00000003
3069 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S))
3070 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V  0x3
3071 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S  30
3072 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
3073 /*description: .*/
3074 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO    0x00000003
3075 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S))
3076 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V  0x3
3077 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S  28
3078 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
3079 /*description: .*/
3080 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD    0x00000003
3081 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S))
3082 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V  0x3
3083 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S  26
3084 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
3085 /*description: .*/
3086 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG    0x00000003
3087 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S))
3088 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V  0x3
3089 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S  24
3090 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
3091 /*description: .*/
3092 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY    0x00000003
3093 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S))
3094 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V  0x3
3095 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S  22
3096 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
3097 /*description: .*/
3098 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT    0x00000003
3099 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S))
3100 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V  0x3
3101 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S  20
3102 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
3103 /*description: .*/
3104 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE    0x00000003
3105 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S))
3106 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V  0x3
3107 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S  18
3108 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3109 /*description: .*/
3110 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM    0x00000003
3111 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S))
3112 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V  0x3
3113 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S  16
3114 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3115 /*description: .*/
3116 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB    0x00000003
3117 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S))
3118 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V  0x3
3119 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S  14
3120 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3121 /*description: .*/
3122 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR    0x00000003
3123 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S))
3124 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_V  0x3
3125 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR_S  12
3126 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3127 /*description: .*/
3128 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM    0x00000003
3129 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S))
3130 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V  0x3
3131 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S  10
3132 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3133 /*description: .*/
3134 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC    0x00000003
3135 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S))
3136 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V  0x3
3137 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S  8
3138 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3139 /*description: .*/
3140 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA    0x00000003
3141 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S))
3142 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V  0x3
3143 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S  6
3144 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3145 /*description: .*/
3146 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI    0x00000003
3147 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S))
3148 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V  0x3
3149 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S  4
3150 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3151 /*description: .*/
3152 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP    0x00000003
3153 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S))
3154 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V  0x3
3155 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S  2
3156 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3157 /*description: .*/
3158 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE    0x00000003
3159 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S))
3160 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_V  0x3
3161 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE_S  0
3162 
3163 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x1E4)
3164 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
3165 /*description: .*/
3166 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1    0x00000003
3167 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S))
3168 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V  0x3
3169 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S  30
3170 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
3171 /*description: .*/
3172 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0    0x00000003
3173 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S))
3174 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V  0x3
3175 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S  28
3176 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
3177 /*description: .*/
3178 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C    0x00000003
3179 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S))
3180 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V  0x3
3181 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S  26
3182 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
3183 /*description: .*/
3184 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC    0x00000003
3185 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S))
3186 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V  0x3
3187 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S  24
3188 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
3189 /*description: .*/
3190 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF    0x00000003
3191 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S))
3192 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V  0x3
3193 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S  20
3194 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3195 /*description: .*/
3196 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX    0x00000003
3197 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S))
3198 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V  0x3
3199 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S  16
3200 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3201 /*description: .*/
3202 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC    0x00000003
3203 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S))
3204 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_V  0x3
3205 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_S  14
3206 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3207 /*description: .*/
3208 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE    0x00000003
3209 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S))
3210 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V  0x3
3211 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S  10
3212 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3213 /*description: .*/
3214 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2    0x00000003
3215 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S))
3216 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V  0x3
3217 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S  8
3218 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3219 /*description: .*/
3220 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO    0x00000003
3221 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S))
3222 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V  0x3
3223 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S  6
3224 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3225 /*description: .*/
3226 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0    0x00000003
3227 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S))
3228 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V  0x3
3229 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S  4
3230 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3231 /*description: .*/
3232 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1    0x00000003
3233 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S))
3234 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V  0x3
3235 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S  2
3236 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3237 /*description: .*/
3238 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART    0x00000003
3239 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S))
3240 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V  0x3
3241 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S  0
3242 
3243 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x1E8)
3244 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
3245 /*description: .*/
3246 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER    0x00000003
3247 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S))
3248 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V  0x3
3249 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S  30
3250 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
3251 /*description: .*/
3252 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1    0x00000003
3253 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S))
3254 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V  0x3
3255 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S  28
3256 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
3257 /*description: .*/
3258 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP    0x00000003
3259 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S))
3260 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V  0x3
3261 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S  26
3262 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
3263 /*description: .*/
3264 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0    0x00000003
3265 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S))
3266 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V  0x3
3267 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S  24
3268 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
3269 /*description: .*/
3270 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB    0x00000003
3271 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S))
3272 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V  0x3
3273 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S  22
3274 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
3275 /*description: .*/
3276 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP    0x00000003
3277 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S))
3278 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_V  0x3
3279 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BACKUP_S  18
3280 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3281 /*description: .*/
3282 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC    0x00000003
3283 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S))
3284 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V  0x3
3285 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S  16
3286 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3287 /*description: .*/
3288 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC    0x00000003
3289 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S))
3290 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V  0x3
3291 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S  14
3292 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3293 /*description: .*/
3294 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT    0x00000003
3295 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S))
3296 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V  0x3
3297 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S  12
3298 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3299 /*description: .*/
3300 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT    0x00000003
3301 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S))
3302 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V  0x3
3303 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S  10
3304 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3305 /*description: .*/
3306 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST    0x00000003
3307 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S))
3308 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V  0x3
3309 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S  8
3310 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3311 /*description: .*/
3312 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0    0x00000003
3313 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S))
3314 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V  0x3
3315 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S  6
3316 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3317 /*description: .*/
3318 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0    0x00000003
3319 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S))
3320 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V  0x3
3321 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S  4
3322 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3323 /*description: .*/
3324 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT    0x00000003
3325 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S))
3326 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V  0x3
3327 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S  0
3328 
3329 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x1EC)
3330 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
3331 /*description: .*/
3332 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR    0x00000003
3333 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S))
3334 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V  0x3
3335 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S  28
3336 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
3337 /*description: .*/
3338 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC    0x00000003
3339 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S))
3340 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V  0x3
3341 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S  26
3342 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
3343 /*description: .*/
3344 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT    0x00000003
3345 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S))
3346 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V  0x3
3347 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S  22
3348 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3349 /*description: .*/
3350 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2    0x00000003
3351 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S))
3352 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V  0x3
3353 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S  16
3354 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3355 /*description: .*/
3356 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1    0x00000003
3357 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S))
3358 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V  0x3
3359 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S  14
3360 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3361 /*description: .*/
3362 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1    0x00000003
3363 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S))
3364 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V  0x3
3365 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S  12
3366 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3367 /*description: .*/
3368 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN    0x00000003
3369 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S))
3370 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_V  0x3
3371 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CAN_S  10
3372 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3373 /*description: .*/
3374 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST    0x00000003
3375 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S))
3376 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V  0x3
3377 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S  8
3378 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3379 /*description: .*/
3380 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1    0x00000003
3381 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S))
3382 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V  0x3
3383 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S  6
3384 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3385 /*description: .*/
3386 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL    0x00000003
3387 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S))
3388 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V  0x3
3389 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S  4
3390 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3391 /*description: .*/
3392 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3    0x00000003
3393 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S))
3394 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V  0x3
3395 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S  2
3396 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3397 /*description: .*/
3398 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2    0x00000003
3399 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S))
3400 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V  0x3
3401 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S  0
3402 
3403 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x1F0)
3404 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
3405 /*description: .*/
3406 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER    0x00000003
3407 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S))
3408 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V  0x3
3409 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S  30
3410 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
3411 /*description: .*/
3412 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO    0x00000003
3413 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S))
3414 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V  0x3
3415 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S  28
3416 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
3417 /*description: .*/
3418 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD    0x00000003
3419 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S))
3420 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V  0x3
3421 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S  26
3422 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
3423 /*description: .*/
3424 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG    0x00000003
3425 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S))
3426 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V  0x3
3427 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S  24
3428 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
3429 /*description: .*/
3430 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY    0x00000003
3431 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S))
3432 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V  0x3
3433 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S  22
3434 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
3435 /*description: .*/
3436 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT    0x00000003
3437 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S))
3438 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V  0x3
3439 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S  20
3440 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
3441 /*description: .*/
3442 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE    0x00000003
3443 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S))
3444 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V  0x3
3445 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S  18
3446 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3447 /*description: .*/
3448 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM    0x00000003
3449 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S))
3450 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V  0x3
3451 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S  16
3452 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3453 /*description: .*/
3454 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB    0x00000003
3455 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S))
3456 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V  0x3
3457 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S  14
3458 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3459 /*description: .*/
3460 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR    0x00000003
3461 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S))
3462 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_V  0x3
3463 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR_S  12
3464 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3465 /*description: .*/
3466 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM    0x00000003
3467 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S))
3468 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V  0x3
3469 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S  10
3470 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3471 /*description: .*/
3472 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC    0x00000003
3473 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S))
3474 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V  0x3
3475 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S  8
3476 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3477 /*description: .*/
3478 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA    0x00000003
3479 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S))
3480 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V  0x3
3481 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S  6
3482 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3483 /*description: .*/
3484 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI    0x00000003
3485 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S))
3486 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V  0x3
3487 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S  4
3488 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3489 /*description: .*/
3490 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP    0x00000003
3491 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S))
3492 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V  0x3
3493 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S  2
3494 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3495 /*description: .*/
3496 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE    0x00000003
3497 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S))
3498 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_V  0x3
3499 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE_S  0
3500 
3501 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x1F4)
3502 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
3503 /*description: .*/
3504 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1    0x000007FF
3505 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S))
3506 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V  0x7FF
3507 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S  11
3508 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
3509 /*description: .*/
3510 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0    0x000007FF
3511 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S))
3512 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V  0x7FF
3513 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S  0
3514 
3515 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x1F8)
3516 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
3517 /*description: .*/
3518 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H    0x00000007
3519 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S))
3520 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V  0x7
3521 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S  9
3522 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
3523 /*description: .*/
3524 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L    0x00000007
3525 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S))
3526 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V  0x7
3527 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S  6
3528 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
3529 /*description: .*/
3530 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H    0x00000007
3531 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S))
3532 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V  0x7
3533 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S  3
3534 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
3535 /*description: .*/
3536 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L    0x00000007
3537 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S))
3538 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V  0x7
3539 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S  0
3540 
3541 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x1FC)
3542 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
3543 /*description: .*/
3544 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1    0x000007FF
3545 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S))
3546 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V  0x7FF
3547 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S  11
3548 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
3549 /*description: .*/
3550 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0    0x000007FF
3551 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S))
3552 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V  0x7FF
3553 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S  0
3554 
3555 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x200)
3556 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
3557 /*description: .*/
3558 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H    0x00000007
3559 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S))
3560 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V  0x7
3561 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S  9
3562 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
3563 /*description: .*/
3564 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L    0x00000007
3565 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S))
3566 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V  0x7
3567 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S  6
3568 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
3569 /*description: .*/
3570 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H    0x00000007
3571 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S))
3572 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V  0x7
3573 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S  3
3574 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
3575 /*description: .*/
3576 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L    0x00000007
3577 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S))
3578 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V  0x7
3579 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S  0
3580 
3581 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x204)
3582 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */
3583 /*description: .*/
3584 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1    0x000007FF
3585 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S))
3586 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V  0x7FF
3587 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S  11
3588 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
3589 /*description: .*/
3590 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0    0x000007FF
3591 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S))
3592 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V  0x7FF
3593 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S  0
3594 
3595 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x208)
3596 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */
3597 /*description: .*/
3598 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H    0x00000007
3599 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S))
3600 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V  0x7
3601 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S  9
3602 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */
3603 /*description: .*/
3604 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L    0x00000007
3605 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S))
3606 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V  0x7
3607 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S  6
3608 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
3609 /*description: .*/
3610 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H    0x00000007
3611 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S))
3612 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V  0x7
3613 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S  3
3614 /* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
3615 /*description: .*/
3616 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L    0x00000007
3617 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M  ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V)<<(SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S))
3618 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V  0x7
3619 #define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S  0
3620 
3621 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x20C)
3622 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
3623 /*description: .*/
3624 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK    (BIT(0))
3625 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_M  (BIT(0))
3626 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_V  0x1
3627 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_LOCK_S  0
3628 
3629 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x210)
3630 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
3631 /*description: .*/
3632 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10    0x00000003
3633 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S))
3634 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_V  0x3
3635 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_10_S  20
3636 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
3637 /*description: .*/
3638 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9    0x00000003
3639 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S))
3640 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_V  0x3
3641 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_9_S  18
3642 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3643 /*description: .*/
3644 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8    0x00000003
3645 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S))
3646 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_V  0x3
3647 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_8_S  16
3648 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3649 /*description: .*/
3650 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7    0x00000003
3651 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S))
3652 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_V  0x3
3653 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_7_S  14
3654 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3655 /*description: .*/
3656 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6    0x00000003
3657 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S))
3658 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_V  0x3
3659 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_6_S  12
3660 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3661 /*description: .*/
3662 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5    0x00000003
3663 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S))
3664 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_V  0x3
3665 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_5_S  10
3666 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3667 /*description: .*/
3668 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4    0x00000003
3669 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S))
3670 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_V  0x3
3671 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_4_S  8
3672 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3673 /*description: .*/
3674 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3    0x00000003
3675 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S))
3676 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_V  0x3
3677 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_3_S  6
3678 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3679 /*description: .*/
3680 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2    0x00000003
3681 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S))
3682 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_V  0x3
3683 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_2_S  4
3684 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3685 /*description: .*/
3686 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1    0x00000003
3687 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S))
3688 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_V  0x3
3689 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_1_S  2
3690 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3691 /*description: .*/
3692 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0    0x00000003
3693 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S))
3694 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_V  0x3
3695 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_0_AREA_0_S  0
3696 
3697 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x214)
3698 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
3699 /*description: .*/
3700 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10    0x00000003
3701 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S))
3702 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_V  0x3
3703 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_10_S  20
3704 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
3705 /*description: .*/
3706 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9    0x00000003
3707 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S))
3708 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_V  0x3
3709 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_9_S  18
3710 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
3711 /*description: .*/
3712 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8    0x00000003
3713 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S))
3714 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_V  0x3
3715 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_8_S  16
3716 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
3717 /*description: .*/
3718 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7    0x00000003
3719 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S))
3720 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_V  0x3
3721 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_7_S  14
3722 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
3723 /*description: .*/
3724 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6    0x00000003
3725 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S))
3726 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_V  0x3
3727 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_6_S  12
3728 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
3729 /*description: .*/
3730 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5    0x00000003
3731 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S))
3732 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_V  0x3
3733 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_5_S  10
3734 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
3735 /*description: .*/
3736 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4    0x00000003
3737 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S))
3738 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_V  0x3
3739 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_4_S  8
3740 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
3741 /*description: .*/
3742 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3    0x00000003
3743 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S))
3744 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_V  0x3
3745 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_3_S  6
3746 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
3747 /*description: .*/
3748 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2    0x00000003
3749 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S))
3750 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_V  0x3
3751 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_2_S  4
3752 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
3753 /*description: .*/
3754 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1    0x00000003
3755 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S))
3756 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_V  0x3
3757 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_1_S  2
3758 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
3759 /*description: .*/
3760 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0    0x00000003
3761 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S))
3762 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_V  0x3
3763 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_WORLD_1_AREA_0_S  0
3764 
3765 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x218)
3766 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3767 /*description: .*/
3768 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0    0x3FFFFFFF
3769 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S))
3770 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_V  0x3FFFFFFF
3771 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_0_S  0
3772 
3773 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x21C)
3774 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3775 /*description: .*/
3776 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1    0x3FFFFFFF
3777 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S))
3778 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_V  0x3FFFFFFF
3779 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_1_S  0
3780 
3781 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x220)
3782 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3783 /*description: .*/
3784 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2    0x3FFFFFFF
3785 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S))
3786 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_V  0x3FFFFFFF
3787 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_2_S  0
3788 
3789 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x224)
3790 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3791 /*description: .*/
3792 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3    0x3FFFFFFF
3793 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S))
3794 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_V  0x3FFFFFFF
3795 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_3_S  0
3796 
3797 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_7_REG          (DR_REG_SENSITIVE_BASE + 0x228)
3798 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3799 /*description: .*/
3800 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4    0x3FFFFFFF
3801 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S))
3802 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_V  0x3FFFFFFF
3803 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_4_S  0
3804 
3805 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_8_REG          (DR_REG_SENSITIVE_BASE + 0x22C)
3806 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3807 /*description: .*/
3808 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5    0x3FFFFFFF
3809 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S))
3810 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_V  0x3FFFFFFF
3811 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_5_S  0
3812 
3813 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_9_REG          (DR_REG_SENSITIVE_BASE + 0x230)
3814 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3815 /*description: .*/
3816 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6    0x3FFFFFFF
3817 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S))
3818 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_V  0x3FFFFFFF
3819 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_6_S  0
3820 
3821 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_10_REG          (DR_REG_SENSITIVE_BASE + 0x234)
3822 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3823 /*description: .*/
3824 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7    0x3FFFFFFF
3825 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S))
3826 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_V  0x3FFFFFFF
3827 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_7_S  0
3828 
3829 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_11_REG          (DR_REG_SENSITIVE_BASE + 0x238)
3830 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3831 /*description: .*/
3832 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8    0x3FFFFFFF
3833 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S))
3834 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_V  0x3FFFFFFF
3835 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_8_S  0
3836 
3837 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_12_REG          (DR_REG_SENSITIVE_BASE + 0x23C)
3838 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3839 /*description: .*/
3840 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9    0x3FFFFFFF
3841 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S))
3842 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_V  0x3FFFFFFF
3843 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_9_S  0
3844 
3845 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_13_REG          (DR_REG_SENSITIVE_BASE + 0x240)
3846 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3847 /*description: .*/
3848 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10    0x3FFFFFFF
3849 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S))
3850 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_V  0x3FFFFFFF
3851 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_10_S  0
3852 
3853 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_14_REG          (DR_REG_SENSITIVE_BASE + 0x244)
3854 /* SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11 : R/W ;bitpos:[29:0] ;default: 30'b0 ; */
3855 /*description: .*/
3856 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11    0x3FFFFFFF
3857 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_M  ((SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V)<<(SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S))
3858 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_V  0x3FFFFFFF
3859 #define SENSITIVE_CORE_1_REGION_PMS_CONSTRAIN_ADDR_11_S  0
3860 
3861 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x248)
3862 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
3863 /*description: .*/
3864 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK    (BIT(0))
3865 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M  (BIT(0))
3866 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V  0x1
3867 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S  0
3868 
3869 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x24C)
3870 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
3871 /*description: .*/
3872 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN    (BIT(1))
3873 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
3874 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V  0x1
3875 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S  1
3876 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
3877 /*description: .*/
3878 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
3879 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
3880 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V  0x1
3881 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S  0
3882 
3883 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x250)
3884 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */
3885 /*description: .*/
3886 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD    0x00000003
3887 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S))
3888 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V  0x3
3889 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S  6
3890 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */
3891 /*description: .*/
3892 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(5))
3893 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(5))
3894 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
3895 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  5
3896 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */
3897 /*description: .*/
3898 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
3899 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
3900 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
3901 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  2
3902 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */
3903 /*description: .*/
3904 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0    (BIT(1))
3905 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M  (BIT(1))
3906 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V  0x1
3907 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S  1
3908 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
3909 /*description: .*/
3910 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
3911 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
3912 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V  0x1
3913 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S  0
3914 
3915 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x254)
3916 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3917 /*description: .*/
3918 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR    0xFFFFFFFF
3919 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S))
3920 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
3921 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S  0
3922 
3923 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG          (DR_REG_SENSITIVE_BASE + 0x258)
3924 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
3925 /*description: .*/
3926 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN    (BIT(1))
3927 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M  (BIT(1))
3928 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V  0x1
3929 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S  1
3930 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
3931 /*description: .*/
3932 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR    (BIT(0))
3933 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M  (BIT(0))
3934 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V  0x1
3935 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S  0
3936 
3937 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG          (DR_REG_SENSITIVE_BASE + 0x25C)
3938 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */
3939 /*description: .*/
3940 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD    0x00000003
3941 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S))
3942 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V  0x3
3943 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S  3
3944 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */
3945 /*description: .*/
3946 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE    0x00000003
3947 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S))
3948 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V  0x3
3949 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S  1
3950 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
3951 /*description: .*/
3952 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR    (BIT(0))
3953 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M  (BIT(0))
3954 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V  0x1
3955 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S  0
3956 
3957 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG          (DR_REG_SENSITIVE_BASE + 0x260)
3958 /* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
3959 /*description: .*/
3960 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR    0xFFFFFFFF
3961 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M  ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V)<<(SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S))
3962 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V  0xFFFFFFFF
3963 #define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S  0
3964 
3965 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x264)
3966 /* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
3967 /*description: .*/
3968 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK    (BIT(0))
3969 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M  (BIT(0))
3970 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V  0x1
3971 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S  0
3972 
3973 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x268)
3974 /* SENSITIVE_CORE_1_VECBASE_WORLD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
3975 /*description: .*/
3976 #define SENSITIVE_CORE_1_VECBASE_WORLD_MASK    (BIT(0))
3977 #define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_M  (BIT(0))
3978 #define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_V  0x1
3979 #define SENSITIVE_CORE_1_VECBASE_WORLD_MASK_S  0
3980 
3981 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x26C)
3982 /* SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
3983 /*description: .*/
3984 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL    0x00000003
3985 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S))
3986 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V  0x3
3987 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S  22
3988 /* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
3989 /*description: .*/
3990 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE    0x003FFFFF
3991 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S))
3992 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_V  0x3FFFFF
3993 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD0_VALUE_S  0
3994 
3995 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_2_REG          (DR_REG_SENSITIVE_BASE + 0x270)
3996 /* SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
3997 /*description: .*/
3998 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE    0x003FFFFF
3999 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_M  ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V)<<(SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S))
4000 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_V  0x3FFFFF
4001 #define SENSITIVE_CORE_1_VECBASE_OVERRIDE_WORLD1_VALUE_S  0
4002 
4003 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG          (DR_REG_SENSITIVE_BASE + 0x274)
4004 /* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4005 /*description: .*/
4006 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK    (BIT(0))
4007 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M  (BIT(0))
4008 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V  0x1
4009 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S  0
4010 
4011 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG          (DR_REG_SENSITIVE_BASE + 0x278)
4012 /* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */
4013 /*description: .*/
4014 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE    (BIT(0))
4015 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M  (BIT(0))
4016 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V  0x1
4017 #define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S  0
4018 
4019 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG          (DR_REG_SENSITIVE_BASE + 0x27C)
4020 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4021 /*description: .*/
4022 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK    (BIT(0))
4023 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_M  (BIT(0))
4024 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_V  0x1
4025 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LOCK_S  0
4026 
4027 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG          (DR_REG_SENSITIVE_BASE + 0x280)
4028 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
4029 /*description: .*/
4030 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1    0x00000003
4031 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S))
4032 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_V  0x3
4033 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART1_S  30
4034 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
4035 /*description: .*/
4036 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0    0x00000003
4037 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S))
4038 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_V  0x3
4039 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S0_S  28
4040 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
4041 /*description: .*/
4042 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C    0x00000003
4043 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S))
4044 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_V  0x3
4045 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_S  26
4046 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
4047 /*description: .*/
4048 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC    0x00000003
4049 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S))
4050 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_V  0x3
4051 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_MISC_S  24
4052 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
4053 /*description: .*/
4054 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF    0x00000003
4055 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S))
4056 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_V  0x3
4057 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_HINF_S  20
4058 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
4059 /*description: .*/
4060 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX    0x00000003
4061 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S))
4062 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_V  0x3
4063 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_IO_MUX_S  16
4064 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
4065 /*description: .*/
4066 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC    0x00000003
4067 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S))
4068 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_V  0x3
4069 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTC_S  14
4070 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
4071 /*description: .*/
4072 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE    0x00000003
4073 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S))
4074 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_V  0x3
4075 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE_S  10
4076 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
4077 /*description: .*/
4078 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2    0x00000003
4079 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S))
4080 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_V  0x3
4081 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_FE2_S  8
4082 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
4083 /*description: .*/
4084 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO    0x00000003
4085 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S))
4086 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_V  0x3
4087 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_GPIO_S  6
4088 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
4089 /*description: .*/
4090 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0    0x00000003
4091 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S))
4092 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_V  0x3
4093 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0_S  4
4094 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
4095 /*description: .*/
4096 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1    0x00000003
4097 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S))
4098 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_V  0x3
4099 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1_S  2
4100 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
4101 /*description: .*/
4102 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART    0x00000003
4103 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S))
4104 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_V  0x3
4105 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART_S  0
4106 
4107 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG          (DR_REG_SENSITIVE_BASE + 0x284)
4108 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
4109 /*description: .*/
4110 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER    0x00000003
4111 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S))
4112 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_V  0x3
4113 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER_S  30
4114 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
4115 /*description: .*/
4116 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1    0x00000003
4117 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S))
4118 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_V  0x3
4119 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1_S  28
4120 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
4121 /*description: .*/
4122 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP    0x00000003
4123 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S))
4124 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_V  0x3
4125 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP_S  26
4126 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
4127 /*description: .*/
4128 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0    0x00000003
4129 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S))
4130 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_V  0x3
4131 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM0_S  24
4132 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
4133 /*description: .*/
4134 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB    0x00000003
4135 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S))
4136 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_V  0x3
4137 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BB_S  22
4138 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
4139 /*description: .*/
4140 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP    0x00000003
4141 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S))
4142 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_V  0x3
4143 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BACKUP_S  18
4144 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
4145 /*description: .*/
4146 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC    0x00000003
4147 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S))
4148 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_V  0x3
4149 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LEDC_S  16
4150 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
4151 /*description: .*/
4152 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC    0x00000003
4153 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S))
4154 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_V  0x3
4155 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLC_S  14
4156 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
4157 /*description: .*/
4158 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT    0x00000003
4159 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S))
4160 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_V  0x3
4161 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PCNT_S  12
4162 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
4163 /*description: .*/
4164 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT    0x00000003
4165 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S))
4166 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_V  0x3
4167 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RMT_S  10
4168 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
4169 /*description: .*/
4170 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST    0x00000003
4171 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S))
4172 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_V  0x3
4173 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SLCHOST_S  8
4174 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
4175 /*description: .*/
4176 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0    0x00000003
4177 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S))
4178 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_V  0x3
4179 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UHCI0_S  6
4180 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
4181 /*description: .*/
4182 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0    0x00000003
4183 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S))
4184 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_V  0x3
4185 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0_S  4
4186 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
4187 /*description: .*/
4188 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT    0x00000003
4189 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S))
4190 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_V  0x3
4191 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_S  0
4192 
4193 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG          (DR_REG_SENSITIVE_BASE + 0x288)
4194 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
4195 /*description: .*/
4196 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR    0x00000003
4197 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S))
4198 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_V  0x3
4199 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWR_S  28
4200 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
4201 /*description: .*/
4202 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC    0x00000003
4203 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S))
4204 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_V  0x3
4205 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC_S  26
4206 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
4207 /*description: .*/
4208 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT    0x00000003
4209 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S))
4210 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_V  0x3
4211 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RWBT_S  22
4212 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
4213 /*description: .*/
4214 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2    0x00000003
4215 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S))
4216 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_V  0x3
4217 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_UART2_S  16
4218 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
4219 /*description: .*/
4220 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1    0x00000003
4221 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S))
4222 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_V  0x3
4223 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2S1_S  14
4224 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
4225 /*description: .*/
4226 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1    0x00000003
4227 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S))
4228 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_V  0x3
4229 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_PWM1_S  12
4230 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
4231 /*description: .*/
4232 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN    0x00000003
4233 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S))
4234 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_V  0x3
4235 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CAN_S  10
4236 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
4237 /*description: .*/
4238 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST    0x00000003
4239 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S))
4240 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_V  0x3
4241 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SDIO_HOST_S  8
4242 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
4243 /*description: .*/
4244 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1    0x00000003
4245 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S))
4246 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_V  0x3
4247 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT1_S  6
4248 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
4249 /*description: .*/
4250 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL    0x00000003
4251 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S))
4252 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_V  0x3
4253 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL_S  4
4254 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
4255 /*description: .*/
4256 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3    0x00000003
4257 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S))
4258 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_V  0x3
4259 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_3_S  2
4260 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
4261 /*description: .*/
4262 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2    0x00000003
4263 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S))
4264 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_V  0x3
4265 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SPI_2_S  0
4266 
4267 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG          (DR_REG_SENSITIVE_BASE + 0x28C)
4268 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */
4269 /*description: .*/
4270 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER    0x00000003
4271 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S))
4272 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_V  0x3
4273 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_WORLD_CONTROLLER_S  30
4274 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */
4275 /*description: .*/
4276 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO    0x00000003
4277 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S))
4278 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_V  0x3
4279 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DIO_S  28
4280 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */
4281 /*description: .*/
4282 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD    0x00000003
4283 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S))
4284 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_V  0x3
4285 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_AD_S  26
4286 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */
4287 /*description: .*/
4288 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG    0x00000003
4289 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S))
4290 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_V  0x3
4291 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CACHE_CONFIG_S  24
4292 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */
4293 /*description: .*/
4294 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY    0x00000003
4295 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S))
4296 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_V  0x3
4297 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_DMA_COPY_S  22
4298 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */
4299 /*description: .*/
4300 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT    0x00000003
4301 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S))
4302 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_V  0x3
4303 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_INTERRUPT_S  20
4304 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */
4305 /*description: .*/
4306 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE    0x00000003
4307 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S))
4308 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_V  0x3
4309 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SENSITIVE_S  18
4310 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */
4311 /*description: .*/
4312 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM    0x00000003
4313 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S))
4314 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_V  0x3
4315 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_SYSTEM_S  16
4316 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */
4317 /*description: .*/
4318 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB    0x00000003
4319 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S))
4320 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_V  0x3
4321 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_S  14
4322 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */
4323 /*description: .*/
4324 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR    0x00000003
4325 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S))
4326 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_V  0x3
4327 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_BT_PWR_S  12
4328 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */
4329 /*description: .*/
4330 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM    0x00000003
4331 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S))
4332 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_V  0x3
4333 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_LCD_CAM_S  10
4334 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */
4335 /*description: .*/
4336 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC    0x00000003
4337 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S))
4338 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_V  0x3
4339 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_APB_ADC_S  8
4340 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */
4341 /*description: .*/
4342 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA    0x00000003
4343 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S))
4344 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_V  0x3
4345 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA_S  6
4346 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */
4347 /*description: .*/
4348 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI    0x00000003
4349 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S))
4350 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_V  0x3
4351 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI_S  4
4352 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */
4353 /*description: .*/
4354 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP    0x00000003
4355 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S))
4356 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_V  0x3
4357 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP_S  2
4358 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
4359 /*description: .*/
4360 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE    0x00000003
4361 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S))
4362 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_V  0x3
4363 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE_S  0
4364 
4365 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_5_REG          (DR_REG_SENSITIVE_BASE + 0x290)
4366 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */
4367 /*description: .*/
4368 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR    0x000007FF
4369 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S))
4370 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_V  0x7FF
4371 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_SPLTADDR_S  0
4372 
4373 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_6_REG          (DR_REG_SENSITIVE_BASE + 0x294)
4374 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */
4375 /*description: .*/
4376 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H    0x00000007
4377 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S))
4378 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_V  0x7
4379 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_H_S  3
4380 /* SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */
4381 /*description: .*/
4382 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L    0x00000007
4383 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_M  ((SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V)<<(SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S))
4384 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_V  0x7
4385 #define SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_RTCFAST_L_S  0
4386 
4387 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG          (DR_REG_SENSITIVE_BASE + 0x298)
4388 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4389 /*description: .*/
4390 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK    (BIT(0))
4391 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_M  (BIT(0))
4392 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_V  0x1
4393 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_LOCK_S  0
4394 
4395 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG          (DR_REG_SENSITIVE_BASE + 0x29C)
4396 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */
4397 /*description: .*/
4398 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN    (BIT(1))
4399 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_M  (BIT(1))
4400 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_V  0x1
4401 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_EN_S  1
4402 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */
4403 /*description: .*/
4404 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR    (BIT(0))
4405 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_M  (BIT(0))
4406 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_V  0x1
4407 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR_S  0
4408 
4409 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG          (DR_REG_SENSITIVE_BASE + 0x2A0)
4410 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[6] ;default: 1'b0 ; */
4411 /*description: .*/
4412 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE    (BIT(6))
4413 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M  (BIT(6))
4414 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V  0x1
4415 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S  6
4416 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[5:3] ;default: 3'b0 ; */
4417 /*description: .*/
4418 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE    0x00000007
4419 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S))
4420 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V  0x7
4421 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S  3
4422 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS : RO ;bitpos:[2:1] ;default: 2'b0 ; */
4423 /*description: .*/
4424 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS    0x00000003
4425 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S))
4426 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_V  0x3
4427 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS_S  1
4428 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */
4429 /*description: .*/
4430 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR    (BIT(0))
4431 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_M  (BIT(0))
4432 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_V  0x1
4433 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR_S  0
4434 
4435 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG          (DR_REG_SENSITIVE_BASE + 0x2A4)
4436 /* SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
4437 /*description: .*/
4438 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR    0xFFFFFFFF
4439 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_M  ((SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V)<<(SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S))
4440 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_V  0xFFFFFFFF
4441 #define SENSITIVE_BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR_S  0
4442 
4443 #define SENSITIVE_EDMA_BOUNDARY_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2A8)
4444 /* SENSITIVE_EDMA_BOUNDARY_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4445 /*description: .*/
4446 #define SENSITIVE_EDMA_BOUNDARY_LOCK    (BIT(0))
4447 #define SENSITIVE_EDMA_BOUNDARY_LOCK_M  (BIT(0))
4448 #define SENSITIVE_EDMA_BOUNDARY_LOCK_V  0x1
4449 #define SENSITIVE_EDMA_BOUNDARY_LOCK_S  0
4450 
4451 #define SENSITIVE_EDMA_BOUNDARY_0_REG          (DR_REG_SENSITIVE_BASE + 0x2AC)
4452 /* SENSITIVE_EDMA_BOUNDARY_0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
4453 /*description: .*/
4454 #define SENSITIVE_EDMA_BOUNDARY_0    0x00003FFF
4455 #define SENSITIVE_EDMA_BOUNDARY_0_M  ((SENSITIVE_EDMA_BOUNDARY_0_V)<<(SENSITIVE_EDMA_BOUNDARY_0_S))
4456 #define SENSITIVE_EDMA_BOUNDARY_0_V  0x3FFF
4457 #define SENSITIVE_EDMA_BOUNDARY_0_S  0
4458 
4459 #define SENSITIVE_EDMA_BOUNDARY_1_REG          (DR_REG_SENSITIVE_BASE + 0x2B0)
4460 /* SENSITIVE_EDMA_BOUNDARY_1 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */
4461 /*description: .*/
4462 #define SENSITIVE_EDMA_BOUNDARY_1    0x00003FFF
4463 #define SENSITIVE_EDMA_BOUNDARY_1_M  ((SENSITIVE_EDMA_BOUNDARY_1_V)<<(SENSITIVE_EDMA_BOUNDARY_1_S))
4464 #define SENSITIVE_EDMA_BOUNDARY_1_V  0x3FFF
4465 #define SENSITIVE_EDMA_BOUNDARY_1_S  0
4466 
4467 #define SENSITIVE_EDMA_BOUNDARY_2_REG          (DR_REG_SENSITIVE_BASE + 0x2B4)
4468 /* SENSITIVE_EDMA_BOUNDARY_2 : R/W ;bitpos:[13:0] ;default: 14'h2000 ; */
4469 /*description: .*/
4470 #define SENSITIVE_EDMA_BOUNDARY_2    0x00003FFF
4471 #define SENSITIVE_EDMA_BOUNDARY_2_M  ((SENSITIVE_EDMA_BOUNDARY_2_V)<<(SENSITIVE_EDMA_BOUNDARY_2_S))
4472 #define SENSITIVE_EDMA_BOUNDARY_2_V  0x3FFF
4473 #define SENSITIVE_EDMA_BOUNDARY_2_S  0
4474 
4475 #define SENSITIVE_EDMA_PMS_SPI2_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2B8)
4476 /* SENSITIVE_EDMA_PMS_SPI2_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4477 /*description: .*/
4478 #define SENSITIVE_EDMA_PMS_SPI2_LOCK    (BIT(0))
4479 #define SENSITIVE_EDMA_PMS_SPI2_LOCK_M  (BIT(0))
4480 #define SENSITIVE_EDMA_PMS_SPI2_LOCK_V  0x1
4481 #define SENSITIVE_EDMA_PMS_SPI2_LOCK_S  0
4482 
4483 #define SENSITIVE_EDMA_PMS_SPI2_REG          (DR_REG_SENSITIVE_BASE + 0x2BC)
4484 /* SENSITIVE_EDMA_PMS_SPI2_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4485 /*description: .*/
4486 #define SENSITIVE_EDMA_PMS_SPI2_ATTR2    0x00000003
4487 #define SENSITIVE_EDMA_PMS_SPI2_ATTR2_M  ((SENSITIVE_EDMA_PMS_SPI2_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR2_S))
4488 #define SENSITIVE_EDMA_PMS_SPI2_ATTR2_V  0x3
4489 #define SENSITIVE_EDMA_PMS_SPI2_ATTR2_S  2
4490 /* SENSITIVE_EDMA_PMS_SPI2_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4491 /*description: .*/
4492 #define SENSITIVE_EDMA_PMS_SPI2_ATTR1    0x00000003
4493 #define SENSITIVE_EDMA_PMS_SPI2_ATTR1_M  ((SENSITIVE_EDMA_PMS_SPI2_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI2_ATTR1_S))
4494 #define SENSITIVE_EDMA_PMS_SPI2_ATTR1_V  0x3
4495 #define SENSITIVE_EDMA_PMS_SPI2_ATTR1_S  0
4496 
4497 #define SENSITIVE_EDMA_PMS_SPI3_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2C0)
4498 /* SENSITIVE_EDMA_PMS_SPI3_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4499 /*description: .*/
4500 #define SENSITIVE_EDMA_PMS_SPI3_LOCK    (BIT(0))
4501 #define SENSITIVE_EDMA_PMS_SPI3_LOCK_M  (BIT(0))
4502 #define SENSITIVE_EDMA_PMS_SPI3_LOCK_V  0x1
4503 #define SENSITIVE_EDMA_PMS_SPI3_LOCK_S  0
4504 
4505 #define SENSITIVE_EDMA_PMS_SPI3_REG          (DR_REG_SENSITIVE_BASE + 0x2C4)
4506 /* SENSITIVE_EDMA_PMS_SPI3_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4507 /*description: .*/
4508 #define SENSITIVE_EDMA_PMS_SPI3_ATTR2    0x00000003
4509 #define SENSITIVE_EDMA_PMS_SPI3_ATTR2_M  ((SENSITIVE_EDMA_PMS_SPI3_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR2_S))
4510 #define SENSITIVE_EDMA_PMS_SPI3_ATTR2_V  0x3
4511 #define SENSITIVE_EDMA_PMS_SPI3_ATTR2_S  2
4512 /* SENSITIVE_EDMA_PMS_SPI3_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4513 /*description: .*/
4514 #define SENSITIVE_EDMA_PMS_SPI3_ATTR1    0x00000003
4515 #define SENSITIVE_EDMA_PMS_SPI3_ATTR1_M  ((SENSITIVE_EDMA_PMS_SPI3_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SPI3_ATTR1_S))
4516 #define SENSITIVE_EDMA_PMS_SPI3_ATTR1_V  0x3
4517 #define SENSITIVE_EDMA_PMS_SPI3_ATTR1_S  0
4518 
4519 #define SENSITIVE_EDMA_PMS_UHCI0_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2C8)
4520 /* SENSITIVE_EDMA_PMS_UHCI0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4521 /*description: .*/
4522 #define SENSITIVE_EDMA_PMS_UHCI0_LOCK    (BIT(0))
4523 #define SENSITIVE_EDMA_PMS_UHCI0_LOCK_M  (BIT(0))
4524 #define SENSITIVE_EDMA_PMS_UHCI0_LOCK_V  0x1
4525 #define SENSITIVE_EDMA_PMS_UHCI0_LOCK_S  0
4526 
4527 #define SENSITIVE_EDMA_PMS_UHCI0_REG          (DR_REG_SENSITIVE_BASE + 0x2CC)
4528 /* SENSITIVE_EDMA_PMS_UHCI0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4529 /*description: .*/
4530 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR2    0x00000003
4531 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_M  ((SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S))
4532 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_V  0x3
4533 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR2_S  2
4534 /* SENSITIVE_EDMA_PMS_UHCI0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4535 /*description: .*/
4536 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR1    0x00000003
4537 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_M  ((SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S))
4538 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_V  0x3
4539 #define SENSITIVE_EDMA_PMS_UHCI0_ATTR1_S  0
4540 
4541 #define SENSITIVE_EDMA_PMS_I2S0_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2D0)
4542 /* SENSITIVE_EDMA_PMS_I2S0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4543 /*description: .*/
4544 #define SENSITIVE_EDMA_PMS_I2S0_LOCK    (BIT(0))
4545 #define SENSITIVE_EDMA_PMS_I2S0_LOCK_M  (BIT(0))
4546 #define SENSITIVE_EDMA_PMS_I2S0_LOCK_V  0x1
4547 #define SENSITIVE_EDMA_PMS_I2S0_LOCK_S  0
4548 
4549 #define SENSITIVE_EDMA_PMS_I2S0_REG          (DR_REG_SENSITIVE_BASE + 0x2D4)
4550 /* SENSITIVE_EDMA_PMS_I2S0_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4551 /*description: .*/
4552 #define SENSITIVE_EDMA_PMS_I2S0_ATTR2    0x00000003
4553 #define SENSITIVE_EDMA_PMS_I2S0_ATTR2_M  ((SENSITIVE_EDMA_PMS_I2S0_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR2_S))
4554 #define SENSITIVE_EDMA_PMS_I2S0_ATTR2_V  0x3
4555 #define SENSITIVE_EDMA_PMS_I2S0_ATTR2_S  2
4556 /* SENSITIVE_EDMA_PMS_I2S0_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4557 /*description: .*/
4558 #define SENSITIVE_EDMA_PMS_I2S0_ATTR1    0x00000003
4559 #define SENSITIVE_EDMA_PMS_I2S0_ATTR1_M  ((SENSITIVE_EDMA_PMS_I2S0_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S0_ATTR1_S))
4560 #define SENSITIVE_EDMA_PMS_I2S0_ATTR1_V  0x3
4561 #define SENSITIVE_EDMA_PMS_I2S0_ATTR1_S  0
4562 
4563 #define SENSITIVE_EDMA_PMS_I2S1_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2D8)
4564 /* SENSITIVE_EDMA_PMS_I2S1_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4565 /*description: .*/
4566 #define SENSITIVE_EDMA_PMS_I2S1_LOCK    (BIT(0))
4567 #define SENSITIVE_EDMA_PMS_I2S1_LOCK_M  (BIT(0))
4568 #define SENSITIVE_EDMA_PMS_I2S1_LOCK_V  0x1
4569 #define SENSITIVE_EDMA_PMS_I2S1_LOCK_S  0
4570 
4571 #define SENSITIVE_EDMA_PMS_I2S1_REG          (DR_REG_SENSITIVE_BASE + 0x2DC)
4572 /* SENSITIVE_EDMA_PMS_I2S1_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4573 /*description: .*/
4574 #define SENSITIVE_EDMA_PMS_I2S1_ATTR2    0x00000003
4575 #define SENSITIVE_EDMA_PMS_I2S1_ATTR2_M  ((SENSITIVE_EDMA_PMS_I2S1_ATTR2_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR2_S))
4576 #define SENSITIVE_EDMA_PMS_I2S1_ATTR2_V  0x3
4577 #define SENSITIVE_EDMA_PMS_I2S1_ATTR2_S  2
4578 /* SENSITIVE_EDMA_PMS_I2S1_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4579 /*description: .*/
4580 #define SENSITIVE_EDMA_PMS_I2S1_ATTR1    0x00000003
4581 #define SENSITIVE_EDMA_PMS_I2S1_ATTR1_M  ((SENSITIVE_EDMA_PMS_I2S1_ATTR1_V)<<(SENSITIVE_EDMA_PMS_I2S1_ATTR1_S))
4582 #define SENSITIVE_EDMA_PMS_I2S1_ATTR1_V  0x3
4583 #define SENSITIVE_EDMA_PMS_I2S1_ATTR1_S  0
4584 
4585 #define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2E0)
4586 /* SENSITIVE_EDMA_PMS_LCD_CAM_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4587 /*description: .*/
4588 #define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK    (BIT(0))
4589 #define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_M  (BIT(0))
4590 #define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_V  0x1
4591 #define SENSITIVE_EDMA_PMS_LCD_CAM_LOCK_S  0
4592 
4593 #define SENSITIVE_EDMA_PMS_LCD_CAM_REG          (DR_REG_SENSITIVE_BASE + 0x2E4)
4594 /* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4595 /*description: .*/
4596 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2    0x00000003
4597 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_M  ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S))
4598 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_V  0x3
4599 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR2_S  2
4600 /* SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4601 /*description: .*/
4602 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1    0x00000003
4603 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_M  ((SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V)<<(SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S))
4604 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_V  0x3
4605 #define SENSITIVE_EDMA_PMS_LCD_CAM_ATTR1_S  0
4606 
4607 #define SENSITIVE_EDMA_PMS_AES_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2E8)
4608 /* SENSITIVE_EDMA_PMS_AES_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4609 /*description: .*/
4610 #define SENSITIVE_EDMA_PMS_AES_LOCK    (BIT(0))
4611 #define SENSITIVE_EDMA_PMS_AES_LOCK_M  (BIT(0))
4612 #define SENSITIVE_EDMA_PMS_AES_LOCK_V  0x1
4613 #define SENSITIVE_EDMA_PMS_AES_LOCK_S  0
4614 
4615 #define SENSITIVE_EDMA_PMS_AES_REG          (DR_REG_SENSITIVE_BASE + 0x2EC)
4616 /* SENSITIVE_EDMA_PMS_AES_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4617 /*description: .*/
4618 #define SENSITIVE_EDMA_PMS_AES_ATTR2    0x00000003
4619 #define SENSITIVE_EDMA_PMS_AES_ATTR2_M  ((SENSITIVE_EDMA_PMS_AES_ATTR2_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR2_S))
4620 #define SENSITIVE_EDMA_PMS_AES_ATTR2_V  0x3
4621 #define SENSITIVE_EDMA_PMS_AES_ATTR2_S  2
4622 /* SENSITIVE_EDMA_PMS_AES_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4623 /*description: .*/
4624 #define SENSITIVE_EDMA_PMS_AES_ATTR1    0x00000003
4625 #define SENSITIVE_EDMA_PMS_AES_ATTR1_M  ((SENSITIVE_EDMA_PMS_AES_ATTR1_V)<<(SENSITIVE_EDMA_PMS_AES_ATTR1_S))
4626 #define SENSITIVE_EDMA_PMS_AES_ATTR1_V  0x3
4627 #define SENSITIVE_EDMA_PMS_AES_ATTR1_S  0
4628 
4629 #define SENSITIVE_EDMA_PMS_SHA_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2F0)
4630 /* SENSITIVE_EDMA_PMS_SHA_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4631 /*description: .*/
4632 #define SENSITIVE_EDMA_PMS_SHA_LOCK    (BIT(0))
4633 #define SENSITIVE_EDMA_PMS_SHA_LOCK_M  (BIT(0))
4634 #define SENSITIVE_EDMA_PMS_SHA_LOCK_V  0x1
4635 #define SENSITIVE_EDMA_PMS_SHA_LOCK_S  0
4636 
4637 #define SENSITIVE_EDMA_PMS_SHA_REG          (DR_REG_SENSITIVE_BASE + 0x2F4)
4638 /* SENSITIVE_EDMA_PMS_SHA_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4639 /*description: .*/
4640 #define SENSITIVE_EDMA_PMS_SHA_ATTR2    0x00000003
4641 #define SENSITIVE_EDMA_PMS_SHA_ATTR2_M  ((SENSITIVE_EDMA_PMS_SHA_ATTR2_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR2_S))
4642 #define SENSITIVE_EDMA_PMS_SHA_ATTR2_V  0x3
4643 #define SENSITIVE_EDMA_PMS_SHA_ATTR2_S  2
4644 /* SENSITIVE_EDMA_PMS_SHA_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4645 /*description: .*/
4646 #define SENSITIVE_EDMA_PMS_SHA_ATTR1    0x00000003
4647 #define SENSITIVE_EDMA_PMS_SHA_ATTR1_M  ((SENSITIVE_EDMA_PMS_SHA_ATTR1_V)<<(SENSITIVE_EDMA_PMS_SHA_ATTR1_S))
4648 #define SENSITIVE_EDMA_PMS_SHA_ATTR1_V  0x3
4649 #define SENSITIVE_EDMA_PMS_SHA_ATTR1_S  0
4650 
4651 #define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x2F8)
4652 /* SENSITIVE_EDMA_PMS_ADC_DAC_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4653 /*description: .*/
4654 #define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK    (BIT(0))
4655 #define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_M  (BIT(0))
4656 #define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_V  0x1
4657 #define SENSITIVE_EDMA_PMS_ADC_DAC_LOCK_S  0
4658 
4659 #define SENSITIVE_EDMA_PMS_ADC_DAC_REG          (DR_REG_SENSITIVE_BASE + 0x2FC)
4660 /* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4661 /*description: .*/
4662 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2    0x00000003
4663 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_M  ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S))
4664 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_V  0x3
4665 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR2_S  2
4666 /* SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4667 /*description: .*/
4668 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1    0x00000003
4669 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_M  ((SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V)<<(SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S))
4670 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_V  0x3
4671 #define SENSITIVE_EDMA_PMS_ADC_DAC_ATTR1_S  0
4672 
4673 #define SENSITIVE_EDMA_PMS_RMT_LOCK_REG          (DR_REG_SENSITIVE_BASE + 0x300)
4674 /* SENSITIVE_EDMA_PMS_RMT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
4675 /*description: .*/
4676 #define SENSITIVE_EDMA_PMS_RMT_LOCK    (BIT(0))
4677 #define SENSITIVE_EDMA_PMS_RMT_LOCK_M  (BIT(0))
4678 #define SENSITIVE_EDMA_PMS_RMT_LOCK_V  0x1
4679 #define SENSITIVE_EDMA_PMS_RMT_LOCK_S  0
4680 
4681 #define SENSITIVE_EDMA_PMS_RMT_REG          (DR_REG_SENSITIVE_BASE + 0x304)
4682 /* SENSITIVE_EDMA_PMS_RMT_ATTR2 : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
4683 /*description: .*/
4684 #define SENSITIVE_EDMA_PMS_RMT_ATTR2    0x00000003
4685 #define SENSITIVE_EDMA_PMS_RMT_ATTR2_M  ((SENSITIVE_EDMA_PMS_RMT_ATTR2_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR2_S))
4686 #define SENSITIVE_EDMA_PMS_RMT_ATTR2_V  0x3
4687 #define SENSITIVE_EDMA_PMS_RMT_ATTR2_S  2
4688 /* SENSITIVE_EDMA_PMS_RMT_ATTR1 : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
4689 /*description: .*/
4690 #define SENSITIVE_EDMA_PMS_RMT_ATTR1    0x00000003
4691 #define SENSITIVE_EDMA_PMS_RMT_ATTR1_M  ((SENSITIVE_EDMA_PMS_RMT_ATTR1_V)<<(SENSITIVE_EDMA_PMS_RMT_ATTR1_S))
4692 #define SENSITIVE_EDMA_PMS_RMT_ATTR1_V  0x3
4693 #define SENSITIVE_EDMA_PMS_RMT_ATTR1_S  0
4694 
4695 #define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x308)
4696 /* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
4697 /*description: .*/
4698 #define SENSITIVE_CLK_EN    (BIT(0))
4699 #define SENSITIVE_CLK_EN_M  (BIT(0))
4700 #define SENSITIVE_CLK_EN_V  0x1
4701 #define SENSITIVE_CLK_EN_S  0
4702 
4703 #define SENSITIVE_RTC_PMS_REG          (DR_REG_SENSITIVE_BASE + 0x30C)
4704 /* SENSITIVE_DIS_RTC_CPU : R/W ;bitpos:[0] ;default: 1'b0 ; */
4705 /*description: .*/
4706 #define SENSITIVE_DIS_RTC_CPU    (BIT(0))
4707 #define SENSITIVE_DIS_RTC_CPU_M  (BIT(0))
4708 #define SENSITIVE_DIS_RTC_CPU_V  0x1
4709 #define SENSITIVE_DIS_RTC_CPU_S  0
4710 
4711 #define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
4712 /* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101280 ; */
4713 /*description: .*/
4714 #define SENSITIVE_DATE    0x0FFFFFFF
4715 #define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
4716 #define SENSITIVE_DATE_V  0xFFFFFFF
4717 #define SENSITIVE_DATE_S  0
4718 
4719 
4720 #ifdef __cplusplus
4721 }
4722 #endif
4723 
4724 
4725 
4726 #endif /*_SOC_SENSITIVE_REG_H_ */
4727