1 /*
2 * SPDX-FileCopyrightText: 2006 Uwe Stuehler <uwe@openbsd.org>
3 *
4 * SPDX-License-Identifier: ISC
5 *
6 * SPDX-FileContributor: 2016-2021 Espressif Systems (Shanghai) CO LTD
7 */
8 /*
9 * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
10 *
11 * Permission to use, copy, modify, and distribute this software for any
12 * purpose with or without fee is hereby granted, provided that the above
13 * copyright notice and this permission notice appear in all copies.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 */
23
24 #ifndef _SDMMC_DEFS_H_
25 #define _SDMMC_DEFS_H_
26
27 #include <stdint.h>
28 #include <limits.h>
29
30 /* MMC commands */ /* response type */
31 #define MMC_GO_IDLE_STATE 0 /* R0 */
32 #define MMC_SEND_OP_COND 1 /* R3 */
33 #define MMC_ALL_SEND_CID 2 /* R2 */
34 #define MMC_SET_RELATIVE_ADDR 3 /* R1 */
35 #define MMC_SWITCH 6 /* R1B */
36 #define MMC_SELECT_CARD 7 /* R1 */
37 #define MMC_SEND_EXT_CSD 8 /* R1 */
38 #define MMC_SEND_CSD 9 /* R2 */
39 #define MMC_SEND_CID 10 /* R1 */
40 #define MMC_READ_DAT_UNTIL_STOP 11 /* R1 */
41 #define MMC_STOP_TRANSMISSION 12 /* R1B */
42 #define MMC_SEND_STATUS 13 /* R1 */
43 #define MMC_SET_BLOCKLEN 16 /* R1 */
44 #define MMC_READ_BLOCK_SINGLE 17 /* R1 */
45 #define MMC_READ_BLOCK_MULTIPLE 18 /* R1 */
46 #define MMC_WRITE_DAT_UNTIL_STOP 20 /* R1 */
47 #define MMC_SET_BLOCK_COUNT 23 /* R1 */
48 #define MMC_WRITE_BLOCK_SINGLE 24 /* R1 */
49 #define MMC_WRITE_BLOCK_MULTIPLE 25 /* R1 */
50 #define MMC_APP_CMD 55 /* R1 */
51
52 /* SD commands */ /* response type */
53 #define SD_SEND_RELATIVE_ADDR 3 /* R6 */
54 #define SD_SEND_SWITCH_FUNC 6 /* R1 */
55 #define SD_SEND_IF_COND 8 /* R7 */
56 #define SD_READ_OCR 58 /* R3 */
57 #define SD_CRC_ON_OFF 59 /* R1 */
58
59 /* SD application commands */ /* response type */
60 #define SD_APP_SET_BUS_WIDTH 6 /* R1 */
61 #define SD_APP_SD_STATUS 13 /* R2 */
62 #define SD_APP_OP_COND 41 /* R3 */
63 #define SD_APP_SEND_SCR 51 /* R1 */
64
65 /* SD IO commands */
66 #define SD_IO_SEND_OP_COND 5 /* R4 */
67 #define SD_IO_RW_DIRECT 52 /* R5 */
68 #define SD_IO_RW_EXTENDED 53 /* R5 */
69
70
71 /* OCR bits */
72 #define MMC_OCR_MEM_READY (1<<31) /* memory power-up status bit */
73 #define MMC_OCR_ACCESS_MODE_MASK 0x60000000 /* bits 30:29 */
74 #define MMC_OCR_SECTOR_MODE (1<<30)
75 #define MMC_OCR_BYTE_MODE (1<<29)
76 #define MMC_OCR_3_5V_3_6V (1<<23)
77 #define MMC_OCR_3_4V_3_5V (1<<22)
78 #define MMC_OCR_3_3V_3_4V (1<<21)
79 #define MMC_OCR_3_2V_3_3V (1<<20)
80 #define MMC_OCR_3_1V_3_2V (1<<19)
81 #define MMC_OCR_3_0V_3_1V (1<<18)
82 #define MMC_OCR_2_9V_3_0V (1<<17)
83 #define MMC_OCR_2_8V_2_9V (1<<16)
84 #define MMC_OCR_2_7V_2_8V (1<<15)
85 #define MMC_OCR_2_6V_2_7V (1<<14)
86 #define MMC_OCR_2_5V_2_6V (1<<13)
87 #define MMC_OCR_2_4V_2_5V (1<<12)
88 #define MMC_OCR_2_3V_2_4V (1<<11)
89 #define MMC_OCR_2_2V_2_3V (1<<10)
90 #define MMC_OCR_2_1V_2_2V (1<<9)
91 #define MMC_OCR_2_0V_2_1V (1<<8)
92 #define MMC_OCR_1_65V_1_95V (1<<7)
93
94 #define SD_OCR_SDHC_CAP (1<<30)
95 #define SD_OCR_VOL_MASK 0xFF8000 /* bits 23:15 */
96
97 /* SD mode R1 response type bits */
98 #define MMC_R1_READY_FOR_DATA (1<<8) /* ready for next transfer */
99 #define MMC_R1_APP_CMD (1<<5) /* app. commands supported */
100 #define MMC_R1_SWITCH_ERROR (1<<7) /* switch command did not succeed */
101
102 /* SPI mode R1 response type bits */
103 #define SD_SPI_R1_IDLE_STATE (1<<0)
104 #define SD_SPI_R1_ERASE_RST (1<<1)
105 #define SD_SPI_R1_ILLEGAL_CMD (1<<2)
106 #define SD_SPI_R1_CMD_CRC_ERR (1<<3)
107 #define SD_SPI_R1_ERASE_SEQ_ERR (1<<4)
108 #define SD_SPI_R1_ADDR_ERR (1<<5)
109 #define SD_SPI_R1_PARAM_ERR (1<<6)
110 #define SD_SPI_R1_NO_RESPONSE (1<<7)
111
112 #define SDIO_R1_FUNC_NUM_ERR (1<<4)
113
114 /* 48-bit response decoding (32 bits w/o CRC) */
115 #define MMC_R1(resp) ((resp)[0])
116 #define MMC_R3(resp) ((resp)[0])
117 #define MMC_R4(resp) ((resp)[0])
118 #define MMC_R5(resp) ((resp)[0])
119 #define SD_R6(resp) ((resp)[0])
120 #define MMC_R1_CURRENT_STATE(resp) (((resp)[0] >> 9) & 0xf)
121
122 /* SPI mode response decoding */
123 #define SD_SPI_R1(resp) ((resp)[0] & 0xff)
124 #define SD_SPI_R2(resp) ((resp)[0] & 0xffff)
125 #define SD_SPI_R3(resp) ((resp)[0])
126 #define SD_SPI_R7(resp) ((resp)[0])
127
128 /* SPI mode data response decoding */
129 #define SD_SPI_DATA_RSP_VALID(resp_byte) (((resp_byte)&0x11)==0x1)
130 #define SD_SPI_DATA_RSP(resp_byte) (((resp_byte)>>1)&0x7)
131 #define SD_SPI_DATA_ACCEPTED 0x2
132 #define SD_SPI_DATA_CRC_ERROR 0x5
133 #define SD_SPI_DATA_WR_ERROR 0x6
134
135 /* RCA argument and response */
136 #define MMC_ARG_RCA(rca) ((rca) << 16)
137 #define SD_R6_RCA(resp) (SD_R6((resp)) >> 16)
138
139 /* bus width argument */
140 #define SD_ARG_BUS_WIDTH_1 0
141 #define SD_ARG_BUS_WIDTH_4 2
142
143 /* EXT_CSD fields */
144 #define EXT_CSD_BUS_WIDTH 183 /* WO */
145 #define EXT_CSD_HS_TIMING 185 /* R/W */
146 #define EXT_CSD_REV 192 /* RO */
147 #define EXT_CSD_STRUCTURE 194 /* RO */
148 #define EXT_CSD_CARD_TYPE 196 /* RO */
149 #define EXT_CSD_SEC_COUNT 212 /* RO */
150 #define EXT_CSD_PWR_CL_26_360 203 /* RO */
151 #define EXT_CSD_PWR_CL_52_360 202 /* RO */
152 #define EXT_CSD_PWR_CL_26_195 201 /* RO */
153 #define EXT_CSD_PWR_CL_52_195 200 /* RO */
154 #define EXT_CSD_POWER_CLASS 187 /* R/W */
155 #define EXT_CSD_CMD_SET 191 /* R/W */
156 #define EXT_CSD_S_CMD_SET 504 /* RO */
157
158 /* EXT_CSD field definitions */
159 #define EXT_CSD_CMD_SET_NORMAL (1U << 0)
160 #define EXT_CSD_CMD_SET_SECURE (1U << 1)
161 #define EXT_CSD_CMD_SET_CPSECURE (1U << 2)
162
163 /* EXT_CSD_HS_TIMING */
164 #define EXT_CSD_HS_TIMING_BC 0
165 #define EXT_CSD_HS_TIMING_HS 1
166 #define EXT_CSD_HS_TIMING_HS200 2
167 #define EXT_CSD_HS_TIMING_HS400 3
168
169 /* EXT_CSD_BUS_WIDTH */
170 #define EXT_CSD_BUS_WIDTH_1 0
171 #define EXT_CSD_BUS_WIDTH_4 1
172 #define EXT_CSD_BUS_WIDTH_8 2
173 #define EXT_CSD_BUS_WIDTH_4_DDR 5
174 #define EXT_CSD_BUS_WIDTH_8_DDR 6
175
176 /* EXT_CSD_CARD_TYPE */
177 /* The only currently valid values for this field are 0x01, 0x03, 0x07,
178 * 0x0B and 0x0F. */
179 #define EXT_CSD_CARD_TYPE_F_26M (1 << 0) /* SDR at "rated voltages */
180 #define EXT_CSD_CARD_TYPE_F_52M (1 << 1) /* SDR at "rated voltages */
181 #define EXT_CSD_CARD_TYPE_F_52M_1_8V (1 << 2) /* DDR, 1.8V or 3.3V I/O */
182 #define EXT_CSD_CARD_TYPE_F_52M_1_2V (1 << 3) /* DDR, 1.2V I/O */
183 #define EXT_CSD_CARD_TYPE_26M 0x01
184 #define EXT_CSD_CARD_TYPE_52M 0x03
185 #define EXT_CSD_CARD_TYPE_52M_V18 0x07
186 #define EXT_CSD_CARD_TYPE_52M_V12 0x0b
187 #define EXT_CSD_CARD_TYPE_52M_V12_18 0x0f
188
189 /* EXT_CSD MMC */
190 #define EXT_CSD_MMC_SIZE 512
191
192 /* MMC_SWITCH access mode */
193 #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
194 #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in value */
195 #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in value */
196 #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target to value */
197
198 /* MMC R2 response (CSD) */
199 #define MMC_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
200 #define MMC_CSD_CSDVER_1_0 1
201 #define MMC_CSD_CSDVER_2_0 2
202 #define MMC_CSD_CSDVER_EXT_CSD 3
203 #define MMC_CSD_MMCVER(resp) MMC_RSP_BITS((resp), 122, 4)
204 #define MMC_CSD_MMCVER_1_0 0 /* MMC 1.0 - 1.2 */
205 #define MMC_CSD_MMCVER_1_4 1 /* MMC 1.4 */
206 #define MMC_CSD_MMCVER_2_0 2 /* MMC 2.0 - 2.2 */
207 #define MMC_CSD_MMCVER_3_1 3 /* MMC 3.1 - 3.3 */
208 #define MMC_CSD_MMCVER_4_0 4 /* MMC 4 */
209 #define MMC_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
210 #define MMC_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
211 #define MMC_CSD_CAPACITY(resp) ((MMC_CSD_C_SIZE((resp))+1) << \
212 (MMC_CSD_C_SIZE_MULT((resp))+2))
213 #define MMC_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
214
215 /* MMC v1 R2 response (CID) */
216 #define MMC_CID_MID_V1(resp) MMC_RSP_BITS((resp), 104, 24)
217 #define MMC_CID_PNM_V1_CPY(resp, pnm) \
218 do { \
219 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
220 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
221 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
222 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
223 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
224 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
225 (pnm)[6] = MMC_RSP_BITS((resp), 48, 8); \
226 (pnm)[7] = '\0'; \
227 } while (0)
228 #define MMC_CID_REV_V1(resp) MMC_RSP_BITS((resp), 40, 8)
229 #define MMC_CID_PSN_V1(resp) MMC_RSP_BITS((resp), 16, 24)
230 #define MMC_CID_MDT_V1(resp) MMC_RSP_BITS((resp), 8, 8)
231
232 /* MMC v2 R2 response (CID) */
233 #define MMC_CID_MID_V2(resp) MMC_RSP_BITS((resp), 120, 8)
234 #define MMC_CID_OID_V2(resp) MMC_RSP_BITS((resp), 104, 16)
235 #define MMC_CID_PNM_V2_CPY(resp, pnm) \
236 do { \
237 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
238 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
239 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
240 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
241 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
242 (pnm)[5] = MMC_RSP_BITS((resp), 56, 8); \
243 (pnm)[6] = '\0'; \
244 } while (0)
245 #define MMC_CID_PSN_V2(resp) MMC_RSP_BITS((resp), 16, 32)
246
247 /* SD R2 response (CSD) */
248 #define SD_CSD_CSDVER(resp) MMC_RSP_BITS((resp), 126, 2)
249 #define SD_CSD_CSDVER_1_0 0
250 #define SD_CSD_CSDVER_2_0 1
251 #define SD_CSD_TAAC(resp) MMC_RSP_BITS((resp), 112, 8)
252 #define SD_CSD_TAAC_1_5_MSEC 0x26
253 #define SD_CSD_NSAC(resp) MMC_RSP_BITS((resp), 104, 8)
254 #define SD_CSD_SPEED(resp) MMC_RSP_BITS((resp), 96, 8)
255 #define SD_CSD_SPEED_25_MHZ 0x32
256 #define SD_CSD_SPEED_50_MHZ 0x5a
257 #define SD_CSD_CCC(resp) MMC_RSP_BITS((resp), 84, 12)
258 #define SD_CSD_CCC_BASIC (1 << 0) /* basic */
259 #define SD_CSD_CCC_BR (1 << 2) /* block read */
260 #define SD_CSD_CCC_BW (1 << 4) /* block write */
261 #define SD_CSD_CCC_ERASE (1 << 5) /* erase */
262 #define SD_CSD_CCC_WP (1 << 6) /* write protection */
263 #define SD_CSD_CCC_LC (1 << 7) /* lock card */
264 #define SD_CSD_CCC_AS (1 << 8) /*application specific*/
265 #define SD_CSD_CCC_IOM (1 << 9) /* I/O mode */
266 #define SD_CSD_CCC_SWITCH (1 << 10) /* switch */
267 #define SD_CSD_READ_BL_LEN(resp) MMC_RSP_BITS((resp), 80, 4)
268 #define SD_CSD_READ_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 79, 1)
269 #define SD_CSD_WRITE_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 78, 1)
270 #define SD_CSD_READ_BLK_MISALIGN(resp) MMC_RSP_BITS((resp), 77, 1)
271 #define SD_CSD_DSR_IMP(resp) MMC_RSP_BITS((resp), 76, 1)
272 #define SD_CSD_C_SIZE(resp) MMC_RSP_BITS((resp), 62, 12)
273 #define SD_CSD_CAPACITY(resp) ((SD_CSD_C_SIZE((resp))+1) << \
274 (SD_CSD_C_SIZE_MULT((resp))+2))
275 #define SD_CSD_V2_C_SIZE(resp) MMC_RSP_BITS((resp), 48, 22)
276 #define SD_CSD_V2_CAPACITY(resp) ((SD_CSD_V2_C_SIZE((resp))+1) << 10)
277 #define SD_CSD_V2_BL_LEN 0x9 /* 512 */
278 #define SD_CSD_VDD_R_CURR_MIN(resp) MMC_RSP_BITS((resp), 59, 3)
279 #define SD_CSD_VDD_R_CURR_MAX(resp) MMC_RSP_BITS((resp), 56, 3)
280 #define SD_CSD_VDD_W_CURR_MIN(resp) MMC_RSP_BITS((resp), 53, 3)
281 #define SD_CSD_VDD_W_CURR_MAX(resp) MMC_RSP_BITS((resp), 50, 3)
282 #define SD_CSD_VDD_RW_CURR_100mA 0x7
283 #define SD_CSD_VDD_RW_CURR_80mA 0x6
284 #define SD_CSD_C_SIZE_MULT(resp) MMC_RSP_BITS((resp), 47, 3)
285 #define SD_CSD_ERASE_BLK_EN(resp) MMC_RSP_BITS((resp), 46, 1)
286 #define SD_CSD_SECTOR_SIZE(resp) MMC_RSP_BITS((resp), 39, 7) /* +1 */
287 #define SD_CSD_WP_GRP_SIZE(resp) MMC_RSP_BITS((resp), 32, 7) /* +1 */
288 #define SD_CSD_WP_GRP_ENABLE(resp) MMC_RSP_BITS((resp), 31, 1)
289 #define SD_CSD_R2W_FACTOR(resp) MMC_RSP_BITS((resp), 26, 3)
290 #define SD_CSD_WRITE_BL_LEN(resp) MMC_RSP_BITS((resp), 22, 4)
291 #define SD_CSD_RW_BL_LEN_2G 0xa
292 #define SD_CSD_RW_BL_LEN_1G 0x9
293 #define SD_CSD_WRITE_BL_PARTIAL(resp) MMC_RSP_BITS((resp), 21, 1)
294 #define SD_CSD_FILE_FORMAT_GRP(resp) MMC_RSP_BITS((resp), 15, 1)
295 #define SD_CSD_COPY(resp) MMC_RSP_BITS((resp), 14, 1)
296 #define SD_CSD_PERM_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 13, 1)
297 #define SD_CSD_TMP_WRITE_PROTECT(resp) MMC_RSP_BITS((resp), 12, 1)
298 #define SD_CSD_FILE_FORMAT(resp) MMC_RSP_BITS((resp), 10, 2)
299
300 /* SD R2 response (CID) */
301 #define SD_CID_MID(resp) MMC_RSP_BITS((resp), 120, 8)
302 #define SD_CID_OID(resp) MMC_RSP_BITS((resp), 104, 16)
303 #define SD_CID_PNM_CPY(resp, pnm) \
304 do { \
305 (pnm)[0] = MMC_RSP_BITS((resp), 96, 8); \
306 (pnm)[1] = MMC_RSP_BITS((resp), 88, 8); \
307 (pnm)[2] = MMC_RSP_BITS((resp), 80, 8); \
308 (pnm)[3] = MMC_RSP_BITS((resp), 72, 8); \
309 (pnm)[4] = MMC_RSP_BITS((resp), 64, 8); \
310 (pnm)[5] = '\0'; \
311 } while (0)
312 #define SD_CID_REV(resp) MMC_RSP_BITS((resp), 56, 8)
313 #define SD_CID_PSN(resp) MMC_RSP_BITS((resp), 24, 32)
314 #define SD_CID_MDT(resp) MMC_RSP_BITS((resp), 8, 12)
315
316 /* SCR (SD Configuration Register) */
317 #define SCR_STRUCTURE(scr) MMC_RSP_BITS((scr), 60, 4)
318 #define SCR_STRUCTURE_VER_1_0 0 /* Version 1.0 */
319 #define SCR_SD_SPEC(scr) MMC_RSP_BITS((scr), 56, 4)
320 #define SCR_SD_SPEC_VER_1_0 0 /* Version 1.0 and 1.01 */
321 #define SCR_SD_SPEC_VER_1_10 1 /* Version 1.10 */
322 #define SCR_SD_SPEC_VER_2 2 /* Version 2.00 or Version 3.0X */
323 #define SCR_DATA_STAT_AFTER_ERASE(scr) MMC_RSP_BITS((scr), 55, 1)
324 #define SCR_SD_SECURITY(scr) MMC_RSP_BITS((scr), 52, 3)
325 #define SCR_SD_SECURITY_NONE 0 /* no security */
326 #define SCR_SD_SECURITY_1_0 1 /* security protocol 1.0 */
327 #define SCR_SD_SECURITY_1_0_2 2 /* security protocol 1.0 */
328 #define SCR_SD_BUS_WIDTHS(scr) MMC_RSP_BITS((scr), 48, 4)
329 #define SCR_SD_BUS_WIDTHS_1BIT (1 << 0) /* 1bit (DAT0) */
330 #define SCR_SD_BUS_WIDTHS_4BIT (1 << 2) /* 4bit (DAT0-3) */
331 #define SCR_SD_SPEC3(scr) MMC_RSP_BITS((scr), 47, 1)
332 #define SCR_EX_SECURITY(scr) MMC_RSP_BITS((scr), 43, 4)
333 #define SCR_SD_SPEC4(scr) MMC_RSP_BITS((scr), 42, 1)
334 #define SCR_RESERVED(scr) MMC_RSP_BITS((scr), 34, 8)
335 #define SCR_CMD_SUPPORT_CMD23(scr) MMC_RSP_BITS((scr), 33, 1)
336 #define SCR_CMD_SUPPORT_CMD20(scr) MMC_RSP_BITS((scr), 32, 1)
337 #define SCR_RESERVED2(scr) MMC_RSP_BITS((scr), 0, 32)
338
339 /* Max supply current in SWITCH_FUNC response (in mA) */
340 #define SD_SFUNC_I_MAX(status) (MMC_RSP_BITS((uint32_t *)(status), 496, 16))
341
342 /* Supported flags in SWITCH_FUNC response */
343 #define SD_SFUNC_SUPPORTED(status, group) \
344 (MMC_RSP_BITS((uint32_t *)(status), 400 + (group - 1) * 16, 16))
345
346 /* Selected function in SWITCH_FUNC response */
347 #define SD_SFUNC_SELECTED(status, group) \
348 (MMC_RSP_BITS((uint32_t *)(status), 376 + (group - 1) * 4, 4))
349
350 /* Busy flags in SWITCH_FUNC response */
351 #define SD_SFUNC_BUSY(status, group) \
352 (MMC_RSP_BITS((uint32_t *)(status), 272 + (group - 1) * 16, 16))
353
354 /* Version of SWITCH_FUNC response */
355 #define SD_SFUNC_VER(status) (MMC_RSP_BITS((uint32_t *)(status), 368, 8))
356
357 #define SD_SFUNC_GROUP_MAX 6
358 #define SD_SFUNC_FUNC_MAX 15
359
360 #define SD_ACCESS_MODE 1 /* Function group 1, Access Mode */
361
362 #define SD_ACCESS_MODE_SDR12 0 /* 25 MHz clock */
363 #define SD_ACCESS_MODE_SDR25 1 /* 50 MHz clock */
364 #define SD_ACCESS_MODE_SDR50 2 /* UHS-I, 100 MHz clock */
365 #define SD_ACCESS_MODE_SDR104 3 /* UHS-I, 208 MHz clock */
366 #define SD_ACCESS_MODE_DDR50 4 /* UHS-I, 50 MHz clock, DDR */
367
368 /**
369 * @brief Extract up to 32 sequential bits from an array of 32-bit words
370 *
371 * Bits within the word are numbered in the increasing order from LSB to MSB.
372 *
373 * As an example, consider 2 32-bit words:
374 *
375 * 0x01234567 0x89abcdef
376 *
377 * On a little-endian system, the bytes are stored in memory as follows:
378 *
379 * 67 45 23 01 ef cd ab 89
380 *
381 * MMC_RSP_BITS will extact bits as follows:
382 *
383 * start=0 len=4 -> result=0x00000007
384 * start=0 len=12 -> result=0x00000567
385 * start=28 len=8 -> result=0x000000f0
386 * start=59 len=5 -> result=0x00000011
387 *
388 * @param src array of words to extract bits from
389 * @param start index of the first bit to extract
390 * @param len number of bits to extract, 1 to 32
391 * @return 32-bit word where requested bits start from LSB
392 */
MMC_RSP_BITS(uint32_t * src,int start,int len)393 static inline uint32_t MMC_RSP_BITS(uint32_t *src, int start, int len)
394 {
395 uint32_t mask = (len % 32 == 0) ? UINT_MAX : UINT_MAX >> (32 - (len % 32));
396 size_t word = start / 32;
397 size_t shift = start % 32;
398 uint32_t right = src[word] >> shift;
399 uint32_t left = (len + shift <= 32) ? 0 : src[word + 1] << ((32 - shift) % 32);
400 return (left | right) & mask;
401 }
402
403 /* SD R4 response (IO OCR) */
404 #define SD_IO_OCR_MEM_READY (1<<31)
405 #define SD_IO_OCR_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x7)
406 #define SD_IO_OCR_MEM_PRESENT (1<<27)
407 #define SD_IO_OCR_MASK 0x00fffff0
408
409 /* CMD52 arguments */
410 #define SD_ARG_CMD52_READ (0<<31)
411 #define SD_ARG_CMD52_WRITE (1<<31)
412 #define SD_ARG_CMD52_FUNC_SHIFT 28
413 #define SD_ARG_CMD52_FUNC_MASK 0x7
414 #define SD_ARG_CMD52_EXCHANGE (1<<27)
415 #define SD_ARG_CMD52_REG_SHIFT 9
416 #define SD_ARG_CMD52_REG_MASK 0x1ffff
417 #define SD_ARG_CMD52_DATA_SHIFT 0
418 #define SD_ARG_CMD52_DATA_MASK 0xff
419 #define SD_R5_DATA(resp) ((resp)[0] & 0xff)
420
421 /* CMD53 arguments */
422 #define SD_ARG_CMD53_READ (0<<31)
423 #define SD_ARG_CMD53_WRITE (1<<31)
424 #define SD_ARG_CMD53_FUNC_SHIFT 28
425 #define SD_ARG_CMD53_FUNC_MASK 0x7
426 #define SD_ARG_CMD53_BLOCK_MODE (1<<27)
427 #define SD_ARG_CMD53_INCREMENT (1<<26)
428 #define SD_ARG_CMD53_REG_SHIFT 9
429 #define SD_ARG_CMD53_REG_MASK 0x1ffff
430 #define SD_ARG_CMD53_LENGTH_SHIFT 0
431 #define SD_ARG_CMD53_LENGTH_MASK 0x1ff
432 #define SD_ARG_CMD53_LENGTH_MAX 512
433
434 /* Card Common Control Registers (CCCR) */
435 #define SD_IO_CCCR_START 0x00000
436 #define SD_IO_CCCR_SIZE 0x100
437 #define SD_IO_CCCR_FN_ENABLE 0x02
438 #define SD_IO_CCCR_FN_READY 0x03
439 #define SD_IO_CCCR_INT_ENABLE 0x04
440 #define SD_IO_CCCR_INT_PENDING 0x05
441 #define SD_IO_CCCR_CTL 0x06
442 #define CCCR_CTL_RES (1<<3)
443 #define SD_IO_CCCR_BUS_WIDTH 0x07
444 #define CCCR_BUS_WIDTH_1 (0<<0)
445 #define CCCR_BUS_WIDTH_4 (2<<0)
446 #define CCCR_BUS_WIDTH_8 (3<<0)
447 #define CCCR_BUS_WIDTH_ECSI (1<<5)
448 #define SD_IO_CCCR_CARD_CAP 0x08
449 #define CCCR_CARD_CAP_LSC BIT(6)
450 #define CCCR_CARD_CAP_4BLS BIT(7)
451 #define SD_IO_CCCR_CISPTR 0x09
452 #define SD_IO_CCCR_BLKSIZEL 0x10
453 #define SD_IO_CCCR_BLKSIZEH 0x11
454 #define SD_IO_CCCR_HIGHSPEED 0x13
455 #define CCCR_HIGHSPEED_SUPPORT BIT(0)
456 #define CCCR_HIGHSPEED_ENABLE BIT(1)
457
458 /* Function Basic Registers (FBR) */
459 #define SD_IO_FBR_START 0x00100
460 #define SD_IO_FBR_SIZE 0x00700
461
462 /* Card Information Structure (CIS) */
463 #define SD_IO_CIS_START 0x01000
464 #define SD_IO_CIS_SIZE 0x17000
465
466 /* CIS tuple codes (based on PC Card 16) */
467 #define CISTPL_CODE_NULL 0x00
468 #define CISTPL_CODE_DEVICE 0x01
469 #define CISTPL_CODE_CHKSUM 0x10
470 #define CISTPL_CODE_VERS1 0x15
471 #define CISTPL_CODE_ALTSTR 0x16
472 #define CISTPL_CODE_CONFIG 0x1A
473 #define CISTPL_CODE_CFTABLE_ENTRY 0x1B
474 #define CISTPL_CODE_MANFID 0x20
475 #define CISTPL_CODE_FUNCID 0x21
476 #define TPLFID_FUNCTION_SDIO 0x0c
477 #define CISTPL_CODE_FUNCE 0x22
478 #define CISTPL_CODE_VENDER_BEGIN 0x80
479 #define CISTPL_CODE_VENDER_END 0x8F
480 #define CISTPL_CODE_SDIO_STD 0x91
481 #define CISTPL_CODE_SDIO_EXT 0x92
482 #define CISTPL_CODE_END 0xFF
483
484
485 /* Timing */
486 #define SDMMC_TIMING_LEGACY 0
487 #define SDMMC_TIMING_HIGHSPEED 1
488 #define SDMMC_TIMING_MMC_DDR52 2
489
490 #endif //_SDMMC_DEFS_H_
491
