1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_ll_sdmmc.h 4 * @author MCD Application Team 5 * @brief Header file of low layer SDMMC HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 10 * 11 * Redistribution and use in source and binary forms, with or without modification, 12 * are permitted provided that the following conditions are met: 13 * 1. Redistributions of source code must retain the above copyright notice, 14 * this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 ****************************************************************************** 34 */ 35 36 /* Define to prevent recursive inclusion -------------------------------------*/ 37 #ifndef STM32L4xx_LL_SDMMC_H 38 #define STM32L4xx_LL_SDMMC_H 39 40 #ifdef __cplusplus 41 extern "C" { 42 #endif 43 44 #if defined(SDMMC1) 45 46 /* Includes ------------------------------------------------------------------*/ 47 #include "stm32l4xx_hal_def.h" 48 49 /** @addtogroup STM32L4xx_Driver 50 * @{ 51 */ 52 53 /** @addtogroup SDMMC_LL 54 * @{ 55 */ 56 57 /* Exported types ------------------------------------------------------------*/ 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types 59 * @{ 60 */ 61 62 /** 63 * @brief SDMMC Configuration Structure definition 64 */ 65 typedef struct 66 { 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. 68 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ 69 70 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 71 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is 72 enabled or disabled. 73 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ 74 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 75 76 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or 77 disabled when the bus is idle. 78 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ 79 80 uint32_t BusWide; /*!< Specifies the SDMMC bus width. 81 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ 82 83 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. 84 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ 85 86 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. 87 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ 88 89 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 90 uint32_t Transceiver; /*!< Specifies whether external Transceiver is enabled or disabled. 91 This parameter can be a value of @ref SDMMC_LL_Transceiver */ 92 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 93 94 }SDMMC_InitTypeDef; 95 96 97 /** 98 * @brief SDMMC Command Control structure 99 */ 100 typedef struct 101 { 102 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent 103 to a card as part of a command message. If a command 104 contains an argument, it must be loaded into this register 105 before writing the command to the command register. */ 106 107 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and 108 Max_Data = 64 */ 109 110 uint32_t Response; /*!< Specifies the SDMMC response type. 111 This parameter can be a value of @ref SDMMC_LL_Response_Type */ 112 113 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is 114 enabled or disabled. 115 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ 116 117 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) 118 is enabled or disabled. 119 This parameter can be a value of @ref SDMMC_LL_CPSM_State */ 120 }SDMMC_CmdInitTypeDef; 121 122 123 /** 124 * @brief SDMMC Data Control structure 125 */ 126 typedef struct 127 { 128 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ 129 130 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */ 131 132 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer. 133 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */ 134 135 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer 136 is a read or write. 137 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ 138 139 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. 140 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ 141 142 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) 143 is enabled or disabled. 144 This parameter can be a value of @ref SDMMC_LL_DPSM_State */ 145 }SDMMC_DataInitTypeDef; 146 147 /** 148 * @} 149 */ 150 151 /* Exported constants --------------------------------------------------------*/ 152 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants 153 * @{ 154 */ 155 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 156 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ 157 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ 158 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ 159 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ 160 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ 161 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ 162 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ 163 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the 164 number of transferred bytes does not match the block length */ 165 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ 166 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ 167 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ 168 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock 169 command or if there was an attempt to access a locked card */ 170 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ 171 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ 172 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ 173 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ 174 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ 175 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ 176 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ 177 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ 178 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ 179 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ 180 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out 181 of erase sequence command was received */ 182 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ 183 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ 184 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ 185 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ 186 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ 187 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ 188 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ 189 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ 190 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ 191 192 /** 193 * @brief SDMMC Commands Index 194 */ 195 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ 196 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ 197 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ 198 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ 199 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ 200 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 201 operating condition register (OCR) content in the response on the CMD line. */ 202 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ 203 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ 204 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 205 and asks the card whether card supports voltage. */ 206 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ 207 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ 208 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 209 #define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ 210 #else 211 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ 212 #endif 213 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ 214 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ 215 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ 216 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ 217 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands 218 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 219 for SDHS and SDXC. */ 220 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 221 fixed 512 bytes in case of SDHC and SDXC. */ 222 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by 223 STOP_TRANSMISSION command. */ 224 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ 225 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ 226 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ 227 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 228 fixed 512 bytes in case of SDHC and SDXC. */ 229 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ 230 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ 231 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ 232 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ 233 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ 234 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ 235 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ 236 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ 237 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command 238 system set by switch function command (CMD6). */ 239 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. 240 Reserved for each command system set by switch function command (CMD6). */ 241 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ 242 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ 243 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ 244 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 245 the SET_BLOCK_LEN command. */ 246 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather 247 than a standard command. */ 248 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card 249 for general purpose/application specific commands. */ 250 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ 251 252 /** 253 * @brief Following commands are SD Card Specific commands. 254 * SDMMC_APP_CMD should be sent before sending these commands. 255 */ 256 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 257 widths are given in SCR register. */ 258 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ 259 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 260 32bit+CRC data block. */ 261 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 262 send its operating condition register (OCR) content in the response on the CMD line. */ 263 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ 264 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ 265 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ 266 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ 267 268 /** 269 * @brief Following commands are SD Card Specific security commands. 270 * SDMMC_CMD_APP_CMD should be sent before sending these commands. 271 */ 272 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) 273 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) 274 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) 275 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) 276 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) 277 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) 278 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) 279 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) 280 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) 281 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) 282 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) 283 284 /** 285 * @brief Masks for errors Card Status R1 (OCR Register) 286 */ 287 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) 288 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) 289 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) 290 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) 291 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) 292 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) 293 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) 294 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) 295 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) 296 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) 297 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) 298 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) 299 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) 300 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) 301 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) 302 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) 303 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) 304 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) 305 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) 306 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) 307 308 /** 309 * @brief Masks for R6 Response 310 */ 311 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) 312 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) 313 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) 314 315 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) 316 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) 317 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) 318 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) 319 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 320 #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) 321 #define SDMMC_SDR50_SWITCH_PATTERN ((uint32_t)0x80FF1F02U) 322 #define SDMMC_SDR25_SWITCH_PATTERN ((uint32_t)0x80FFFF01U) 323 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 324 325 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) 326 327 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) 328 329 #define SDMMC_ALLZERO ((uint32_t)0x00000000U) 330 331 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) 332 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) 333 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) 334 335 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) 336 337 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) 338 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) 339 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) 340 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) 341 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) 342 343 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) 344 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) 345 346 /** 347 * @brief Command Class supported 348 */ 349 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U) 350 351 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ 352 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ 353 #define SDMMC_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ 354 355 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge 356 * @{ 357 */ 358 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) 359 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE 360 361 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \ 362 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING)) 363 /** 364 * @} 365 */ 366 367 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 368 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass 369 * @{ 370 */ 371 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) 372 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS 373 374 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \ 375 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE)) 376 /** 377 * @} 378 */ 379 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 380 381 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving 382 * @{ 383 */ 384 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) 385 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV 386 387 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \ 388 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE)) 389 /** 390 * @} 391 */ 392 393 /** @defgroup SDMMC_LL_Bus_Wide Bus Width 394 * @{ 395 */ 396 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U) 397 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0 398 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1 399 400 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \ 401 ((WIDE) == SDMMC_BUS_WIDE_4B) || \ 402 ((WIDE) == SDMMC_BUS_WIDE_8B)) 403 /** 404 * @} 405 */ 406 407 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control 408 * @{ 409 */ 410 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) 411 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN 412 413 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \ 414 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE)) 415 /** 416 * @} 417 */ 418 419 /** @defgroup SDMMC_LL_Clock_Division Clock Division 420 * @{ 421 */ 422 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 423 /* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */ 424 #define IS_SDMMC_CLKDIV(DIV) ((DIV) < 0x400U) 425 #else 426 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFFU) 427 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 428 /** 429 * @} 430 */ 431 432 433 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 434 /** @defgroup SDMMC_LL_Transceiver Transceiver 435 * @{ 436 */ 437 #define SDMMC_TRANSCEIVER_DISABLE ((uint32_t)0x00000000U) 438 #define SDMMC_TRANSCEIVER_ENABLE ((uint32_t)0x00000001U) 439 440 #define IS_SDMMC_TRANSCEIVER(MODE) (((MODE) == SDMMC_TRANSCEIVER_DISABLE) || \ 441 ((MODE) == SDMMC_TRANSCEIVER_ENABLE)) 442 /** 443 * @} 444 */ 445 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 446 447 /** @defgroup SDMMC_LL_Command_Index Command Index 448 * @{ 449 */ 450 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40U) 451 /** 452 * @} 453 */ 454 455 /** @defgroup SDMMC_LL_Response_Type Response Type 456 * @{ 457 */ 458 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U) 459 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0 460 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP 461 462 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \ 463 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \ 464 ((RESPONSE) == SDMMC_RESPONSE_LONG)) 465 /** 466 * @} 467 */ 468 469 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt 470 * @{ 471 */ 472 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U) 473 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT 474 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND 475 476 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \ 477 ((WAIT) == SDMMC_WAIT_IT) || \ 478 ((WAIT) == SDMMC_WAIT_PEND)) 479 /** 480 * @} 481 */ 482 483 /** @defgroup SDMMC_LL_CPSM_State CPSM State 484 * @{ 485 */ 486 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U) 487 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN 488 489 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \ 490 ((CPSM) == SDMMC_CPSM_ENABLE)) 491 /** 492 * @} 493 */ 494 495 /** @defgroup SDMMC_LL_Response_Registers Response Register 496 * @{ 497 */ 498 #define SDMMC_RESP1 ((uint32_t)0x00000000U) 499 #define SDMMC_RESP2 ((uint32_t)0x00000004U) 500 #define SDMMC_RESP3 ((uint32_t)0x00000008U) 501 #define SDMMC_RESP4 ((uint32_t)0x0000000CU) 502 503 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \ 504 ((RESP) == SDMMC_RESP2) || \ 505 ((RESP) == SDMMC_RESP3) || \ 506 ((RESP) == SDMMC_RESP4)) 507 508 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 509 /** @defgroup SDMMC_Internal_DMA_Mode SDMMC Internal DMA Mode 510 * @{ 511 */ 512 #define SDMMC_DISABLE_IDMA ((uint32_t)0x00000000) 513 #define SDMMC_ENABLE_IDMA_SINGLE_BUFF (SDMMC_IDMA_IDMAEN) 514 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE) 515 #define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1 (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT) 516 517 /** 518 * @} 519 */ 520 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 521 /** 522 * @} 523 */ 524 525 /** @defgroup SDMMC_LL_Data_Length Data Lenght 526 * @{ 527 */ 528 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU) 529 /** 530 * @} 531 */ 532 533 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size 534 * @{ 535 */ 536 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) 537 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0 538 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1 539 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1) 540 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2 541 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2) 542 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 543 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2) 544 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3 545 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3) 546 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 547 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3) 548 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 549 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 550 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3) 551 552 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \ 553 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \ 554 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \ 555 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \ 556 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \ 557 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \ 558 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \ 559 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \ 560 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \ 561 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \ 562 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \ 563 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \ 564 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \ 565 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \ 566 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B)) 567 /** 568 * @} 569 */ 570 571 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction 572 * @{ 573 */ 574 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) 575 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR 576 577 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \ 578 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC)) 579 /** 580 * @} 581 */ 582 583 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type 584 * @{ 585 */ 586 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) 587 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 588 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE_1 589 #else 590 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE 591 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 592 593 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \ 594 ((MODE) == SDMMC_TRANSFER_MODE_STREAM)) 595 /** 596 * @} 597 */ 598 599 /** @defgroup SDMMC_LL_DPSM_State DPSM State 600 * @{ 601 */ 602 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U) 603 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN 604 605 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\ 606 ((DPSM) == SDMMC_DPSM_ENABLE)) 607 /** 608 * @} 609 */ 610 611 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode 612 * @{ 613 */ 614 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) 615 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD) 616 617 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \ 618 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2)) 619 /** 620 * @} 621 */ 622 623 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources 624 * @{ 625 */ 626 #define SDMMC_IT_CCRCFAIL SDMMC_MASK_CCRCFAILIE 627 #define SDMMC_IT_DCRCFAIL SDMMC_MASK_DCRCFAILIE 628 #define SDMMC_IT_CTIMEOUT SDMMC_MASK_CTIMEOUTIE 629 #define SDMMC_IT_DTIMEOUT SDMMC_MASK_DTIMEOUTIE 630 #define SDMMC_IT_TXUNDERR SDMMC_MASK_TXUNDERRIE 631 #define SDMMC_IT_RXOVERR SDMMC_MASK_RXOVERRIE 632 #define SDMMC_IT_CMDREND SDMMC_MASK_CMDRENDIE 633 #define SDMMC_IT_CMDSENT SDMMC_MASK_CMDSENTIE 634 #define SDMMC_IT_DATAEND SDMMC_MASK_DATAENDIE 635 #define SDMMC_IT_DBCKEND SDMMC_MASK_DBCKENDIE 636 #define SDMMC_IT_TXFIFOHE SDMMC_MASK_TXFIFOHEIE 637 #define SDMMC_IT_RXFIFOHF SDMMC_MASK_RXFIFOHFIE 638 #define SDMMC_IT_RXFIFOF SDMMC_MASK_RXFIFOFIE 639 #define SDMMC_IT_TXFIFOE SDMMC_MASK_TXFIFOEIE 640 #define SDMMC_IT_SDIOIT SDMMC_MASK_SDIOITIE 641 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 642 #define SDMMC_IT_DHOLD SDMMC_MASK_DHOLDIE 643 #define SDMMC_IT_DABORT SDMMC_MASK_DABORTIE 644 #define SDMMC_IT_BUSYD0END SDMMC_MASK_BUSYD0ENDIE 645 #define SDMMC_IT_ACKFAIL SDMMC_MASK_ACKFAILIE 646 #define SDMMC_IT_ACKTIMEOUT SDMMC_MASK_ACKTIMEOUTIE 647 #define SDMMC_IT_VSWEND SDMMC_MASK_VSWENDIE 648 #define SDMMC_IT_CKSTOP SDMMC_MASK_CKSTOPIE 649 #define SDMMC_IT_IDMABTC SDMMC_MASK_IDMABTCIE 650 #else 651 #define SDMMC_IT_CMDACT SDMMC_MASK_CMDACTIE 652 #define SDMMC_IT_TXACT SDMMC_MASK_TXACTIE 653 #define SDMMC_IT_RXACT SDMMC_MASK_RXACTIE 654 #define SDMMC_IT_TXFIFOF SDMMC_MASK_TXFIFOFIE 655 #define SDMMC_IT_RXFIFOE SDMMC_MASK_RXFIFOEIE 656 #define SDMMC_IT_TXDAVL SDMMC_MASK_TXDAVLIE 657 #define SDMMC_IT_RXDAVL SDMMC_MASK_RXDAVLIE 658 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 659 /** 660 * @} 661 */ 662 663 /** @defgroup SDMMC_LL_Flags Flags 664 * @{ 665 */ 666 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL 667 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL 668 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT 669 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT 670 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR 671 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR 672 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND 673 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT 674 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND 675 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND 676 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE 677 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF 678 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF 679 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF 680 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE 681 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE 682 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT 683 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 684 #define SDMMC_FLAG_DHOLD SDMMC_STA_DHOLD 685 #define SDMMC_FLAG_DABORT SDMMC_STA_DABORT 686 #define SDMMC_FLAG_DPSMACT SDMMC_STA_DPSMACT 687 #define SDMMC_FLAG_CMDACT SDMMC_STA_CPSMACT 688 #define SDMMC_FLAG_BUSYD0 SDMMC_STA_BUSYD0 689 #define SDMMC_FLAG_BUSYD0END SDMMC_STA_BUSYD0END 690 #define SDMMC_FLAG_ACKFAIL SDMMC_STA_ACKFAIL 691 #define SDMMC_FLAG_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT 692 #define SDMMC_FLAG_VSWEND SDMMC_STA_VSWEND 693 #define SDMMC_FLAG_CKSTOP SDMMC_STA_CKSTOP 694 #define SDMMC_FLAG_IDMATE SDMMC_STA_IDMATE 695 #define SDMMC_FLAG_IDMABTC SDMMC_STA_IDMABTC 696 #else 697 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT 698 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT 699 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT 700 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL 701 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL 702 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 703 704 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 705 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 706 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 707 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 708 SDMMC_FLAG_DHOLD | SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT |\ 709 SDMMC_FLAG_BUSYD0END | SDMMC_FLAG_SDIOIT | SDMMC_FLAG_ACKFAIL |\ 710 SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND | SDMMC_FLAG_CKSTOP |\ 711 SDMMC_FLAG_IDMATE | SDMMC_FLAG_IDMABTC)) 712 713 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 714 SDMMC_FLAG_CMDSENT | SDMMC_FLAG_BUSYD0END)) 715 716 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 717 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DHOLD |\ 718 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_DABORT | SDMMC_FLAG_IDMATE |\ 719 SDMMC_FLAG_IDMABTC)) 720 721 #else 722 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\ 723 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\ 724 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\ 725 SDMMC_FLAG_DBCKEND | SDMMC_FLAG_SDIOIT)) 726 727 #define SDMMC_STATIC_CMD_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT | SDMMC_FLAG_CMDREND |\ 728 SDMMC_FLAG_CMDSENT)) 729 730 #define SDMMC_STATIC_DATA_FLAGS ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\ 731 SDMMC_FLAG_RXOVERR | SDMMC_FLAG_DATAEND | SDMMC_FLAG_DBCKEND)) 732 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 733 734 /** 735 * @} 736 */ 737 738 /** 739 * @} 740 */ 741 742 /* Exported macro ------------------------------------------------------------*/ 743 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros 744 * @{ 745 */ 746 747 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions 748 * @brief SDMMC_LL registers bit address in the alias region 749 * @{ 750 */ 751 /* ---------------------- SDMMC registers bit mask --------------------------- */ 752 /* --- CLKCR Register ---*/ 753 /* CLKCR register clear mask */ 754 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 755 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 756 SDMMC_CLKCR_WIDBUS |\ 757 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 758 #else 759 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\ 760 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\ 761 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN)) 762 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 763 764 /* --- DCTRL Register ---*/ 765 /* SDMMC DCTRL Clear Mask */ 766 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\ 767 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE)) 768 769 /* --- CMD Register ---*/ 770 /* CMD Register clear mask */ 771 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 772 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 773 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 774 SDMMC_CMD_CPSMEN | SDMMC_CMD_CMDSUSPEND)) 775 #else 776 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\ 777 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\ 778 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND)) 779 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 780 781 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 782 /* SDMMC Initialization Frequency (400KHz max) */ 783 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x3C) /* 48MHz / (SDMMC_INIT_CLK_DIV * 2) < 400KHz */ 784 785 /* SDMMC Data Transfer Frequency (25MHz max) */ 786 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x1) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV * 2) < 25MHz */ 787 #else 788 /* SDMMC Initialization Frequency (400KHz max) */ 789 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ 790 791 /* SDMMC Data Transfer Frequency (25MHz max) */ 792 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0) /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */ 793 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 794 795 /** 796 * @} 797 */ 798 799 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration 800 * @brief macros to handle interrupts and specific clock configurations 801 * @{ 802 */ 803 804 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 805 /** 806 * @brief Enable the SDMMC device. 807 * @param __INSTANCE__: SDMMC Instance 808 * @retval None 809 */ 810 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) 811 812 /** 813 * @brief Disable the SDMMC device. 814 * @param __INSTANCE__: SDMMC Instance 815 * @retval None 816 */ 817 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) 818 819 /** 820 * @brief Enable the SDMMC DMA transfer. 821 * @param __INSTANCE__: SDMMC Instance 822 * @retval None 823 */ 824 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) 825 /** 826 * @brief Disable the SDMMC DMA transfer. 827 * @param __INSTANCE__: SDMMC Instance 828 * @retval None 829 */ 830 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) 831 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 832 833 /** 834 * @brief Enable the SDMMC device interrupt. 835 * @param __INSTANCE__: Pointer to SDMMC register base 836 * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. 837 * This parameter can be one or a combination of the following values: 838 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 839 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 840 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 841 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 842 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 843 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 844 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 845 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 846 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 847 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 848 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 849 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 850 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 851 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 852 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 853 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 854 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 855 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 856 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 857 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 858 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 859 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 860 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 861 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 862 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 863 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 864 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 865 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 866 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 867 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 868 * @retval None 869 */ 870 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) 871 872 /** 873 * @brief Disable the SDMMC device interrupt. 874 * @param __INSTANCE__: Pointer to SDMMC register base 875 * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. 876 * This parameter can be one or a combination of the following values: 877 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 878 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 879 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 880 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 881 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 882 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 883 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 884 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 885 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 886 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 887 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 888 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 889 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 890 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 891 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 892 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 893 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 894 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 895 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 896 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 897 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 898 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 899 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 900 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 901 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 902 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 903 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 904 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 905 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 906 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 907 * @retval None 908 */ 909 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) 910 911 /** 912 * @brief Checks whether the specified SDMMC flag is set or not. 913 * @param __INSTANCE__: Pointer to SDMMC register base 914 * @param __FLAG__: specifies the flag to check. 915 * This parameter can be one of the following values: 916 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 917 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 918 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 919 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 920 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 921 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 922 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 923 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 924 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 925 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 926 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress 927 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty 928 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full 929 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full 930 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full 931 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty 932 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty 933 * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received 934 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 935 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 936 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 937 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 938 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 939 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 940 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 941 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 942 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 943 * @arg SDMMC_FLAG_TXACT: Data transmit in progress 944 * @arg SDMMC_FLAG_RXACT: Data receive in progress 945 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO 946 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO 947 * @retval The new state of SDMMC_FLAG (SET or RESET). 948 */ 949 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) 950 951 952 /** 953 * @brief Clears the SDMMC pending flags. 954 * @param __INSTANCE__: Pointer to SDMMC register base 955 * @param __FLAG__: specifies the flag to clear. 956 * This parameter can be one or a combination of the following values: 957 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) 958 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) 959 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout 960 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout 961 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error 962 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error 963 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed) 964 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required) 965 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) 966 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed) 967 * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received 968 * @arg SDMMC_FLAG_DHOLD: Data transfer Hold 969 * @arg SDMMC_FLAG_DABORT: Data transfer aborted by CMD12 970 * @arg SDMMC_FLAG_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected 971 * @arg SDMMC_FLAG_ACKFAIL: Boot Acknowledgment received 972 * @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout 973 * @arg SDMMC_FLAG_VSWEND: Voltage switch critical timing section completion 974 * @arg SDMMC_FLAG_CKSTOP: SDMMC_CK stopped in Voltage switch procedure 975 * @arg SDMMC_FLAG_IDMATE: IDMA transfer error 976 * @arg SDMMC_FLAG_IDMABTC: IDMA buffer transfer complete 977 * @retval None 978 */ 979 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) 980 981 /** 982 * @brief Checks whether the specified SDMMC interrupt has occurred or not. 983 * @param __INSTANCE__: Pointer to SDMMC register base 984 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. 985 * This parameter can be one of the following values: 986 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 987 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 988 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 989 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 990 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 991 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 992 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 993 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 994 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt 995 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt 996 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt 997 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt 998 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt 999 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt 1000 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt 1001 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt 1002 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt 1003 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 1004 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1005 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1006 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1007 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1008 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1009 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1010 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1011 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1012 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt 1013 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt 1014 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt 1015 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt 1016 * @retval The new state of SDMMC_IT (SET or RESET). 1017 */ 1018 #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) 1019 1020 /** 1021 * @brief Clears the SDMMC's interrupt pending bits. 1022 * @param __INSTANCE__: Pointer to SDMMC register base 1023 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. 1024 * This parameter can be one or a combination of the following values: 1025 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt 1026 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt 1027 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt 1028 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt 1029 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt 1030 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt 1031 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt 1032 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt 1033 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt 1034 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt 1035 * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt 1036 * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt 1037 * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt 1038 * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt 1039 * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt 1040 * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt 1041 * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt 1042 * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt 1043 * @retval None 1044 */ 1045 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) 1046 1047 /** 1048 * @brief Enable Start the SD I/O Read Wait operation. 1049 * @param __INSTANCE__: Pointer to SDMMC register base 1050 * @retval None 1051 */ 1052 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) 1053 1054 /** 1055 * @brief Disable Start the SD I/O Read Wait operations. 1056 * @param __INSTANCE__: Pointer to SDMMC register base 1057 * @retval None 1058 */ 1059 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) 1060 1061 /** 1062 * @brief Enable Start the SD I/O Read Wait operation. 1063 * @param __INSTANCE__: Pointer to SDMMC register base 1064 * @retval None 1065 */ 1066 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) 1067 1068 /** 1069 * @brief Disable Stop the SD I/O Read Wait operations. 1070 * @param __INSTANCE__: Pointer to SDMMC register base 1071 * @retval None 1072 */ 1073 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) 1074 1075 /** 1076 * @brief Enable the SD I/O Mode Operation. 1077 * @param __INSTANCE__: Pointer to SDMMC register base 1078 * @retval None 1079 */ 1080 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) 1081 1082 /** 1083 * @brief Disable the SD I/O Mode Operation. 1084 * @param __INSTANCE__: Pointer to SDMMC register base 1085 * @retval None 1086 */ 1087 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) 1088 1089 /** 1090 * @brief Enable the SD I/O Suspend command sending. 1091 * @param __INSTANCE__: Pointer to SDMMC register base 1092 * @retval None 1093 */ 1094 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 1095 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) 1096 #else 1097 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND) 1098 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1099 1100 /** 1101 * @brief Disable the SD I/O Suspend command sending. 1102 * @param __INSTANCE__: Pointer to SDMMC register base 1103 * @retval None 1104 */ 1105 #if !defined(STM32L4R5xx) && !defined(STM32L4R7xx) && !defined(STM32L4R9xx) && !defined(STM32L4S5xx) && !defined(STM32L4S7xx) && !defined(STM32L4S9xx) 1106 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND) 1107 #else 1108 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND) 1109 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1110 1111 /** 1112 * @brief Enable the CMDTRANS mode. 1113 * @param __INSTANCE__ : Pointer to SDMMC register base 1114 * @retval None 1115 */ 1116 #define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS) 1117 1118 /** 1119 * @brief Disable the CMDTRANS mode. 1120 * @param __INSTANCE__ : Pointer to SDMMC register base 1121 * @retval None 1122 */ 1123 #define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS) 1124 /** 1125 * @} 1126 */ 1127 1128 /** 1129 * @} 1130 */ 1131 1132 /* Exported functions --------------------------------------------------------*/ 1133 /** @addtogroup SDMMC_LL_Exported_Functions 1134 * @{ 1135 */ 1136 1137 /* Initialization/de-initialization functions **********************************/ 1138 /** @addtogroup HAL_SDMMC_LL_Group1 1139 * @{ 1140 */ 1141 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init); 1142 /** 1143 * @} 1144 */ 1145 1146 /* I/O operation functions *****************************************************/ 1147 /** @addtogroup HAL_SDMMC_LL_Group2 1148 * @{ 1149 */ 1150 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx); 1151 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData); 1152 /** 1153 * @} 1154 */ 1155 1156 /* Peripheral Control functions ************************************************/ 1157 /** @addtogroup HAL_SDMMC_LL_Group3 1158 * @{ 1159 */ 1160 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx); 1161 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1162 HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx); 1163 #endif /* !STM32L4R5xx && !STM32L4R7xx && !STM32L4R9xx && !STM32L4S5xx && !STM32L4S7xx && !STM32L4S9xx */ 1164 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); 1165 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx); 1166 1167 /* Command path state machine (CPSM) management functions */ 1168 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); 1169 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx); 1170 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response); 1171 1172 /* Data path state machine (DPSM) management functions */ 1173 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data); 1174 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx); 1175 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx); 1176 1177 /* SDMMC Cards mode management functions */ 1178 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode); 1179 1180 /* SDMMC Commands management functions */ 1181 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize); 1182 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1183 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd); 1184 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1185 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd); 1186 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1187 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd); 1188 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1189 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd); 1190 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx); 1191 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx); 1192 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr); 1193 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx); 1194 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx); 1195 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1196 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1197 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth); 1198 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx); 1199 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx); 1200 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1201 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA); 1202 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1203 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx); 1204 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1205 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); 1206 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 1207 uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx); 1208 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 1209 1210 /** 1211 * @} 1212 */ 1213 1214 /** 1215 * @} 1216 */ 1217 1218 /** 1219 * @} 1220 */ 1221 1222 /** 1223 * @} 1224 */ 1225 1226 #endif /* SDMMC1 */ 1227 1228 #ifdef __cplusplus 1229 } 1230 #endif 1231 1232 #endif /* STM32L4xx_LL_SDMMC_H */ 1233 1234 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1235
