1 /**
2 ******************************************************************************
3 * @file stm32l1xx_ll_sdmmc.c
4 * @author MCD Application Team
5 * @brief SDMMC Low Layer HAL module driver.
6 *
7 * This file provides firmware functions to manage the following
8 * functionalities of the SDMMC peripheral:
9 * + Initialization/de-initialization functions
10 * + I/O operation functions
11 * + Peripheral Control functions
12 * + Peripheral State functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### SDMMC peripheral features #####
17 ==============================================================================
18 [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
19 peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
20 devices.
21
22 [..] The SDIO features include the following:
23 (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
24 for three different databus modes: 1-bit (default), 4-bit and 8-bit
25 (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
26 (+) Full compliance with SD Memory Card Specifications Version 2.0
27 (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
28 different data bus modes: 1-bit (default) and 4-bit
29 (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
30 Rev1.1)
31 (+) Data transfer up to 48 MHz for the 8 bit mode
32 (+) Data and command output enable signals to control external bidirectional drivers.
33
34
35 ##### How to use this driver #####
36 ==============================================================================
37 [..]
38 This driver is a considered as a driver of service for external devices drivers
39 that interfaces with the SDIO peripheral.
40 According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs
41 is used in the device's driver to perform SDIO operations and functionalities.
42
43 This driver is almost transparent for the final user, it is only used to implement other
44 functionalities of the external device.
45
46 [..]
47 (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from the PLL. Before start working with SDIO peripheral make sure that the
48 PLL is well configured.
49 The SDIO peripheral uses two clock signals:
50 (++) SDIO adapter clock (SDIOCLK = 48 MHz)
51 (++) APB2 bus clock (PCLK2)
52
53 -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
54 Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
55
56 (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
57 peripheral.
58
59 (+) Enable the Power ON State using the SDIO_PowerState_ON(SDIOx)
60 function and disable it using the function SDIO_PowerState_OFF(SDIOx).
61
62 (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
63
64 (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT)
65 and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode.
66
67 (+) When using the DMA mode
68 (++) Configure the DMA in the MSP layer of the external device
69 (++) Active the needed channel Request
70 (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
71 __SDIO_DMA_DISABLE().
72
73 (+) To control the CPSM (Command Path State Machine) and send
74 commands to the card use the SDIO_SendCommand(SDIOx),
75 SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
76 to fill the command structure (pointer to SDIO_CmdInitTypeDef) according
77 to the selected command to be sent.
78 The parameters that should be filled are:
79 (++) Command Argument
80 (++) Command Index
81 (++) Command Response type
82 (++) Command Wait
83 (++) CPSM Status (Enable or Disable).
84
85 -@@- To check if the command is well received, read the SDIO_CMDRESP
86 register using the SDIO_GetCommandResponse().
87 The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
88 SDIO_GetResponse() function.
89
90 (+) To control the DPSM (Data Path State Machine) and send/receive
91 data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
92 SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
93
94 *** Read Operations ***
95 =======================
96 [..]
97 (#) First, user has to fill the data structure (pointer to
98 SDIO_DataInitTypeDef) according to the selected data type to be received.
99 The parameters that should be filled are:
100 (++) Data Timeout
101 (++) Data Length
102 (++) Data Block size
103 (++) Data Transfer direction: should be from card (To SDIO)
104 (++) Data Transfer mode
105 (++) DPSM Status (Enable or Disable)
106
107 (#) Configure the SDIO resources to receive the data from the card
108 according to selected transfer mode.
109
110 (#) Send the selected Read command.
111
112 (#) Use the SDIO flags/interrupts to check the transfer status.
113
114 *** Write Operations ***
115 ========================
116 [..]
117 (#) First, user has to fill the data structure (pointer to
118 SDIO_DataInitTypeDef) according to the selected data type to be received.
119 The parameters that should be filled are:
120 (++) Data Timeout
121 (++) Data Length
122 (++) Data Block size
123 (++) Data Transfer direction: should be to card (To CARD)
124 (++) Data Transfer mode
125 (++) DPSM Status (Enable or Disable)
126
127 (#) Configure the SDIO resources to send the data to the card according to
128 selected transfer mode.
129
130 (#) Send the selected Write command.
131
132 (#) Use the SDIO flags/interrupts to check the transfer status.
133
134 @endverbatim
135 ******************************************************************************
136 * @attention
137 *
138 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
139 *
140 * Redistribution and use in source and binary forms, with or without modification,
141 * are permitted provided that the following conditions are met:
142 * 1. Redistributions of source code must retain the above copyright notice,
143 * this list of conditions and the following disclaimer.
144 * 2. Redistributions in binary form must reproduce the above copyright notice,
145 * this list of conditions and the following disclaimer in the documentation
146 * and/or other materials provided with the distribution.
147 * 3. Neither the name of STMicroelectronics nor the names of its contributors
148 * may be used to endorse or promote products derived from this software
149 * without specific prior written permission.
150 *
151 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
152 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
153 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
154 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
155 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
156 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
157 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
158 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
159 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
160 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
161 *
162 ******************************************************************************
163 */
164
165 /* Includes ------------------------------------------------------------------*/
166 #include "stm32l1xx_hal.h"
167
168 /** @addtogroup STM32L1xx_HAL_Driver
169 * @{
170 */
171
172 /** @defgroup SDMMC_LL SDMMC_LL
173 * @brief Low layer module for SD and MMC driver
174 * @{
175 */
176
177 #if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
178
179 #if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
180
181 /* Private typedef -----------------------------------------------------------*/
182 /* Private define ------------------------------------------------------------*/
183 /* Private macro -------------------------------------------------------------*/
184 /* Private variables ---------------------------------------------------------*/
185 /* Private function prototypes -----------------------------------------------*/
186 /* Private functions ---------------------------------------------------------*/
187
188 /** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
189 * @{
190 */
191
192 /** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions
193 * @brief Initialization and Configuration functions
194 *
195 @verbatim
196 ===============================================================================
197 ##### Initialization/de-initialization functions #####
198 ===============================================================================
199 [..] This section provides functions allowing to:
200
201 @endverbatim
202 * @{
203 */
204
205 /**
206 * @brief Initializes the SDIO according to the specified
207 * parameters in the SDIO_InitTypeDef and create the associated handle.
208 * @param SDIOx: Pointer to SDIO register base
209 * @param Init: SDIO initialization structure
210 * @retval HAL status
211 */
SDIO_Init(SDIO_TypeDef * SDIOx,SDIO_InitTypeDef Init)212 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
213 {
214 uint32_t tmpreg = 0;
215
216 /* Check the parameters */
217 assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
218 assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge));
219 assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
220 assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
221 assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
222 assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
223 assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
224
225 /* Set SDIO configuration parameters */
226 tmpreg |= (Init.ClockEdge |\
227 Init.ClockBypass |\
228 Init.ClockPowerSave |\
229 Init.BusWide |\
230 Init.HardwareFlowControl |\
231 Init.ClockDiv
232 );
233
234 /* Write to SDIO CLKCR */
235 MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);
236
237 return HAL_OK;
238 }
239
240 /**
241 * @}
242 */
243
244 /** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions
245 * @brief Data transfers functions
246 *
247 @verbatim
248 ===============================================================================
249 ##### I/O operation functions #####
250 ===============================================================================
251 [..]
252 This subsection provides a set of functions allowing to manage the SDIO data
253 transfers.
254
255 @endverbatim
256 * @{
257 */
258
259 /**
260 * @brief Read data (word) from Rx FIFO in blocking mode (polling)
261 * @param SDIOx: Pointer to SDIO register base
262 * @retval HAL status
263 */
SDIO_ReadFIFO(SDIO_TypeDef * SDIOx)264 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
265 {
266 /* Read data from Rx FIFO */
267 return (SDIOx->FIFO);
268 }
269
270 /**
271 * @brief Write data (word) to Tx FIFO in blocking mode (polling)
272 * @param SDIOx: Pointer to SDIO register base
273 * @param pWriteData: pointer to data to write
274 * @retval HAL status
275 */
SDIO_WriteFIFO(SDIO_TypeDef * SDIOx,uint32_t * pWriteData)276 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
277 {
278 /* Write data to FIFO */
279 SDIOx->FIFO = *pWriteData;
280
281 return HAL_OK;
282 }
283
284 /**
285 * @}
286 */
287
288 /** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions
289 * @brief management functions
290 *
291 @verbatim
292 ===============================================================================
293 ##### Peripheral Control functions #####
294 ===============================================================================
295 [..]
296 This subsection provides a set of functions allowing to control the SDIO data
297 transfers.
298
299 @endverbatim
300 * @{
301 */
302
303 /**
304 * @brief Set SDIO Power state to ON.
305 * @param SDIOx: Pointer to SDIO register base
306 * @retval HAL status
307 */
SDIO_PowerState_ON(SDIO_TypeDef * SDIOx)308 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
309 {
310 /* Set power state to ON */
311 SDIOx->POWER = SDIO_POWER_PWRCTRL;
312
313 return HAL_OK;
314 }
315
316 /**
317 * @brief Set SDIO Power state to OFF.
318 * @param SDIOx: Pointer to SDIO register base
319 * @retval HAL status
320 */
SDIO_PowerState_OFF(SDIO_TypeDef * SDIOx)321 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
322 {
323 /* Set power state to OFF */
324 SDIOx->POWER = 0x00000000U;
325
326 return HAL_OK;
327 }
328
329 /**
330 * @brief Get SDIO Power state.
331 * @param SDIOx: Pointer to SDIO register base
332 * @retval Power status of the controller. The returned value can be one of the
333 * following values:
334 * - 0x00: Power OFF
335 * - 0x02: Power UP
336 * - 0x03: Power ON
337 */
SDIO_GetPowerState(SDIO_TypeDef * SDIOx)338 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)
339 {
340 return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
341 }
342
343 /**
344 * @brief Configure the SDIO command path according to the specified parameters in
345 * SDIO_CmdInitTypeDef structure and send the command
346 * @param SDIOx: Pointer to SDIO register base
347 * @param SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains
348 * the configuration information for the SDIO command
349 * @retval HAL status
350 */
SDIO_SendCommand(SDIO_TypeDef * SDIOx,SDIO_CmdInitTypeDef * SDIO_CmdInitStruct)351 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
352 {
353 uint32_t tmpreg = 0;
354
355 /* Check the parameters */
356 assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
357 assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
358 assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
359 assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
360
361 /* Set the SDIO Argument value */
362 SDIOx->ARG = SDIO_CmdInitStruct->Argument;
363
364 /* Set SDIO command parameters */
365 tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex |\
366 SDIO_CmdInitStruct->Response |\
367 SDIO_CmdInitStruct->WaitForInterrupt |\
368 SDIO_CmdInitStruct->CPSM);
369
370 /* Write to SDIO CMD register */
371 MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg);
372
373 return HAL_OK;
374 }
375
376 /**
377 * @brief Return the command index of last command for which response received
378 * @param SDIOx: Pointer to SDIO register base
379 * @retval Command index of the last command response received
380 */
SDIO_GetCommandResponse(SDIO_TypeDef * SDIOx)381 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
382 {
383 return (uint8_t)(SDIOx->RESPCMD);
384 }
385
386
387 /**
388 * @brief Return the response received from the card for the last command
389 * @param SDIO_RESP: Specifies the SDIO response register.
390 * This parameter can be one of the following values:
391 * @arg SDIO_RESP1: Response Register 1
392 * @arg SDIO_RESP2: Response Register 2
393 * @arg SDIO_RESP3: Response Register 3
394 * @arg SDIO_RESP4: Response Register 4
395 * @retval The Corresponding response register value
396 */
SDIO_GetResponse(uint32_t SDIO_RESP)397 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
398 {
399 __IO uint32_t tmp = 0;
400
401 /* Check the parameters */
402 assert_param(IS_SDIO_RESP(SDIO_RESP));
403
404 /* Get the response */
405 tmp = SDIO_RESP_ADDR + SDIO_RESP;
406
407 return (*(__IO uint32_t *) tmp);
408 }
409
410 /**
411 * @brief Configure the SDIO data path according to the specified
412 * parameters in the SDIO_DataInitTypeDef.
413 * @param SDIOx: Pointer to SDIO register base
414 * @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure
415 * that contains the configuration information for the SDIO command.
416 * @retval HAL status
417 */
SDIO_DataConfig(SDIO_TypeDef * SDIOx,SDIO_DataInitTypeDef * SDIO_DataInitStruct)418 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
419 {
420 uint32_t tmpreg = 0;
421
422 /* Check the parameters */
423 assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
424 assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
425 assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
426 assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
427 assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
428
429 /* Set the SDIO Data Timeout value */
430 SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
431
432 /* Set the SDIO DataLength value */
433 SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
434
435 /* Set the SDIO data configuration parameters */
436 tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
437 SDIO_DataInitStruct->TransferDir |\
438 SDIO_DataInitStruct->TransferMode |\
439 SDIO_DataInitStruct->DPSM);
440
441 /* Write to SDIO DCTRL */
442 MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
443
444 return HAL_OK;
445
446 }
447
448 /**
449 * @brief Returns number of remaining data bytes to be transferred.
450 * @param SDIOx: Pointer to SDIO register base
451 * @retval Number of remaining data bytes to be transferred
452 */
SDIO_GetDataCounter(SDIO_TypeDef * SDIOx)453 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
454 {
455 return (SDIOx->DCOUNT);
456 }
457
458 /**
459 * @brief Get the FIFO data
460 * @param SDIOx: Pointer to SDIO register base
461 * @retval Data received
462 */
SDIO_GetFIFOCount(SDIO_TypeDef * SDIOx)463 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
464 {
465 return (SDIOx->FIFO);
466 }
467
468
469 /**
470 * @brief Sets one of the two options of inserting read wait interval.
471 * @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
472 * This parameter can be:
473 * @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
474 * @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
475 * @retval None
476 */
SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)477 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
478 {
479 /* Check the parameters */
480 assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
481
482 *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
483
484 return HAL_OK;
485 }
486
487 /**
488 * @}
489 */
490
491 /**
492 * @}
493 */
494
495 #endif /* STM32L151xD || STM32L152xD || STM32L162xD */
496
497 #endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
498 /**
499 * @}
500 */
501
502 /**
503 * @}
504 */
505
506 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
507
