1 /* 2 * Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its 3 * affiliates 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef SDHI_PRV_R_SDHI_PRIVATE_H 9 #define SDHI_PRV_R_SDHI_PRIVATE_H 10 11 /********************************************************************************************************************** 12 * Includes 13 **********************************************************************************************************************/ 14 #include "bsp_api.h" 15 16 /** Common macro for FSP header files. There is also a corresponding FSP_FOOTER 17 * macro at the end of this file. */ 18 FSP_HEADER 19 20 /********************************************************************************************************************** 21 * Macro definitions 22 **********************************************************************************************************************/ 23 #define SDHI_PRV_CSD_VERSION_1_0 (0U) 24 #define SDHI_PRV_CSD_VERSION_2_0 \ 25 (1U) /* value of 1 is CSD 2.0 according to SD spec. */ 26 27 #define SDHI_PRV_CMD_GO_IDLE_STATE (0U) 28 #define SDHI_PRV_CMD_SEND_OP_COND (1U) 29 #define SDHI_PRV_CMD_ALL_SEND_CID (2U) 30 #define SDHI_PRV_CMD_SEND_RELATIVE_ADDR (3U) 31 #define SDHI_PRV_CMD_SDIO (5U) 32 #define SDHI_PRV_CMD_SET_BUS_WIDTH (6U) 33 #define SDHI_PRV_CMD_SWITCH (6U) 34 #define SDHI_PRV_CMD_SEL_DES_CARD (7U) 35 #define SDHI_PRV_CMD_IF_COND (8U) 36 #define SDHI_PRV_CMD_SEND_CSD (9U) 37 #define SDHI_PRV_CMD_SET_BLOCKLEN (16U) 38 #define SDHI_PRV_CMD_READ_SINGLE_BLOCK (17U) 39 #define SDHI_PRV_CMD_READ_MULTIPLE_BLOCK (18U) 40 #define SDHI_PRV_CMD_WRITE_SINGLE_BLOCK (24U) 41 #define SDHI_PRV_CMD_WRITE_MULTIPLE_BLOCK (25U) 42 #define SDHI_PRV_CMD_ERASE_WR_BLK_START (32U) 43 #define SDHI_PRV_CMD_ERASE_WR_BLK_END (33U) 44 #define SDHI_PRV_CMD_TAG_ERASE_GROUP_START (0x423U) 45 #define SDHI_PRV_CMD_TAG_ERASE_GROUP_END (0x424U) 46 #define SDHI_PRV_CMD_ERASE (38U) 47 #define SDHI_PRV_CMD_SD_SEND_OP_COND (41U) 48 #define SDHI_PRV_CMD_IO_RW_DIRECT (52U) 49 #define SDHI_PRV_CMD_IO_READ_EXT_SINGLE_BLOCK (0x1c35U) 50 #define SDHI_PRV_CMD_IO_EXT_MULTI_BLOCK (0x6000U) 51 #define SDHI_PRV_CMD_IO_WRITE_EXT_SINGLE_BLOCK (0x0c35U) 52 53 #define SDHI_PRV_CMD_APP_CMD (55U) 54 #define SDHI_PRV_CMD_C_ACMD (1U << 6) /* APP Command */ 55 56 #define SDHI_PRV_IF_COND_VOLTAGE (1U) 57 #define SDHI_PRV_IF_COND_CHECK_PATTERN (0xAAU) 58 59 #define SDHI_PRV_OCR_CAPACITY_HC (1U << 30) 60 61 #define SDHI_PRV_OCR_VDD_2_7_V (1U << 15) 62 #define SDHI_PRV_OCR_VDD_2_8_V (1U << 16) 63 #define SDHI_PRV_OCR_VDD_2_9_V (1U << 17) 64 #define SDHI_PRV_OCR_VDD_3_0_V (1U << 18) 65 #define SDHI_PRV_OCR_VDD_3_1_V (1U << 19) 66 #define SDHI_PRV_OCR_VDD_3_2_V (1U << 20) 67 #define SDHI_PRV_OCR_VDD_3_3_V (1U << 21) 68 #define SDHI_PRV_OCR_VDD_3_4_V (1U << 22) 69 #define SDHI_PRV_OCR_VDD_3_5_V (1U << 23) 70 #define SDHI_PRV_OCR_VDD_SUPPORTED \ 71 (SDHI_PRV_OCR_VDD_2_7_V | SDHI_PRV_OCR_VDD_2_8_V | SDHI_PRV_OCR_VDD_2_9_V | \ 72 SDHI_PRV_OCR_VDD_3_0_V | SDHI_PRV_OCR_VDD_3_1_V | SDHI_PRV_OCR_VDD_3_2_V | \ 73 SDHI_PRV_OCR_VDD_3_3_V | SDHI_PRV_OCR_VDD_3_4_V | SDHI_PRV_OCR_VDD_3_5_V) 74 75 /* CMD52 Arguments */ 76 #define SDHI_PRV_SDIO_CMD52_READ (0U) 77 #define SDHI_PRV_SDIO_CMD52_WRITE (1U) 78 79 /* SWITCH command argument's bit postion */ 80 #define SDHI_PRV_SWITCH_ACCESS_SHIFT (24U) 81 #define SDHI_PRV_SWITCH_INDEX_SHIFT (16U) 82 #define SDHI_PRV_SWITCH_VALUE_SHIFT (8U) 83 84 #define SDHI_PRV_EMMC_EXT_CSD_SIZE (512U) 85 86 /* Offsets */ 87 #define SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET (185U) 88 #define SDHI_PRV_EMMC_EXT_CSD_DEVICE_TYPE_OFFSET (196U) 89 #define SDHI_PRV_EMMC_EXT_CSD_SEC_COUNT_OFFSET (212U) 90 91 /* Commands */ 92 #define SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE (3U) 93 #define SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT (2U) 94 #define SDHI_PRV_EMMC_HIGH_SPEED_MODE \ 95 (((SDHI_PRV_EMMC_SWITCH_ACCESS_WRITE_BYTE << 24U) | \ 96 (SDHI_PRV_EMMC_EXT_CSD_HS_TIMING_OFFSET << 16U)) | \ 97 (SDHI_PRV_EMMC_HIGH_SPEED_52_MHZ_BIT << 8U)) 98 99 #define SDHI_PRV_SD_SWITCH_STATUS_SIZE (64U) 100 #define SDHI_PRV_SD_SWITCH_HIGH_SPEED_RESPONSE (13U) 101 #define SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR_RESPONSE (16U) 102 #define SDHI_PRV_SD_SWITCH_HIGH_SPEED_ERROR (0x0fU) 103 #define SDHI_PRV_SD_SWITCH_HIGH_SPEED_OK (0x02U) 104 105 #define SDHI_PRV_EMMC_SEND_OP_COND (0x701U) 106 #define SDHI_PRV_EMMC_CMD_SWITCH_WBUSY \ 107 (0x506U) /* eMMC CMD6 switch command "with response busy" */ 108 #define SDHI_PRV_EMMC_CMD_SEND_EXT_CSD (0x1C08U) /* CMD 8, read data */ 109 #define SDHI_PRV_EMMC_DEFAULT_CLOCK_RATE (26000000U) /* 26 MHz */ 110 #define SDHI_PRV_EMMC_HIGH_SPEED_CLOCK_RATE (52000000U) /* 52 MHz */ 111 #define SDHI_PRV_SD_HIGH_SPEED_MODE_SWITCH (0x80FFFFF1U) /* set SD high speed \ 112 */ 113 #define SDHI_PRV_SD_DEFAULT_CLOCK_RATE (25000000U) /* 25 MHz */ 114 #define SDHI_PRV_SD_HIGH_SPEED_CLOCK_RATE (50000000U) /* 50 MHz */ 115 #define SDHI_PRV_SDIO_HIGH_SPEED_CLOCK_RATE (50000000U) /* 50 MHz */ 116 117 #define SDHI_PRV_EMMC_ERASE_ARGUMENT_TRIM (1U) 118 119 #define SDHI_PRV_CSD_CID_SERIAL_NUMBER_BITS (32) 120 #define SDHI_PRV_CSD_CID_PRODUCT_NAME_BITS (40) 121 122 /********************************************************************************************************************** 123 * Typedef definitions 124 **********************************************************************************************************************/ 125 typedef enum e_sdmmc_priv_sd_state { 126 SDMMC_PRIV_SD_STATE_IDLE, 127 SDMMC_PRIV_SD_STATE_READY, 128 SDMMC_PRIV_SD_STATE_IDENT, 129 SDMMC_PRIV_SD_STATE_STBY, 130 SDMMC_PRIV_SD_STATE_TRANSFER, 131 SDMMC_PRIV_SD_STATE_DATA, 132 SDMMC_PRIV_SD_STATE_RCV, 133 SDMMC_PRIV_SD_STATE_PROG, 134 SDMMC_PRIV_SD_STATE_DIS, 135 SDMMC_PRIV_SD_STATE_RSVD9, 136 SDMMC_PRIV_SD_STATE_RSVD10, 137 SDMMC_PRIV_SD_STATE_RSVD11, 138 SDMMC_PRIV_SD_STATE_RSVD12, 139 SDMMC_PRIV_SD_STATE_RSVD13, 140 SDMMC_PRIV_SD_STATE_RSVD14, 141 SDMMC_PRIV_SD_STATE_RSVD15 142 } sdmmc_priv_sd_state_t; 143 144 /** SDMMC card specific data */ 145 typedef struct st_sdmmc_priv_csd_reg { 146 union { 147 uint8_t array[16]; 148 149 /* All structures in this union must be packed since some bitfields span 150 * more than one 32-bit word. */ 151 #if defined(__ICCARM__) 152 __packed struct 153 #elif defined(__GNUC__) 154 struct __attribute__((__packed__)) 155 #endif 156 { 157 volatile uint32_t sdrsp10; 158 volatile uint32_t sdrsp32; 159 volatile uint32_t sdrsp54; 160 volatile uint32_t sdrsp76; 161 } reg; 162 163 /* All structures in this union must be packed since some bitfields span 164 * more than one 32-bit word. */ 165 #if defined(__ICCARM__) 166 __packed struct 167 #elif defined(__GNUC__) 168 struct __attribute__((__packed__)) 169 #endif 170 { 171 uint32_t reserved_8 : 2; ///< [9:8] 172 uint32_t file_format : 2; ///< [11:10] file format 173 uint32_t tmp_write_protect : 1; ///< [12] temporary write protection 174 uint32_t perm_write_protect : 1; ///< [13] permanent write protection 175 uint32_t copy : 1; ///< [14] copy flag 176 uint32_t file_format_grp : 1; ///< [15] file format group 177 uint32_t reserved_20 : 5; ///< [16-20] 178 uint32_t 179 write_bl_partial : 1; ///< [21] partial blocks for write allowed 180 uint32_t write_bl_len : 4; ///< [25:22] max. write data block length 181 uint32_t r2w_factor : 3; ///< [28:26] write speed factor 182 uint32_t reserved_29 : 2; ///< [30:29] 183 uint32_t wp_grp_enable : 1; ///< [31] write protect group enable 184 uint32_t wp_grp_size : 7; ///< [38:32] write protect group size 185 uint32_t sector_size : 7; ///< [45:39] erase sector size 186 uint32_t erase_blk_en : 1; ///< [46] erase single block enable 187 uint32_t c_size_mult : 3; ///< [49:47] device size multiplier*/ 188 uint32_t vdd_w_curr_max : 3; ///< [52:50] max. write current for vdd max 189 uint32_t vdd_w_curr_min : 3; ///< [55:53] max. write current for vdd min 190 uint32_t vdd_r_curr_max : 3; ///< [58:56] max. read current for vdd max 191 uint32_t vdd_r_curr_min : 3; ///< [61:59] max. read current for vdd min 192 uint32_t c_size : 12; ///< [73:62] device size 193 uint32_t reserved_74 : 2; ///< [75:74] 194 uint32_t dsr_imp : 1; ///< [76] dsr implemented 195 uint32_t read_blk_misalign : 1; ///< [77] read block misalignment 196 uint32_t write_blk_misalign : 1; ///< [78] write block misalignment 197 uint32_t read_bl_partial : 1; ///< [79] partial blocks for read allowed 198 uint32_t read_bl_len : 4; ///< [83:80] max read data block length 199 uint32_t ccc : 12; ///< [95:84] card command classes 200 uint32_t tran_speed : 8; ///< [103:96] max. data transfer rate 201 uint32_t nsac : 8; ///< [111:104] data read access-time-2 clk cycles 202 uint32_t taac : 8; ///< [119:112] data read access-time-1 203 uint32_t reserved_120 : 6; ///< [125:120] 204 uint32_t csd_structure : 2; ///< [127:126] csd structure 205 uint32_t reserved_128 : 8; ///< [135:128] 206 } csd_v1_b; 207 208 /* All structures in this union must be packed since some bitfields span 209 * more than one 32-bit word. */ 210 #if defined(__ICCARM__) 211 __packed struct 212 #elif defined(__GNUC__) 213 struct __attribute__((__packed__)) 214 #endif 215 { 216 uint32_t reserved_8 : 2; ///< [9:8] 217 uint32_t file_format : 2; ///< [11:10] file format 218 uint32_t tmp_write_protect : 1; ///< [12] temporary write protection 219 uint32_t perm_write_protect : 1; ///< [13] permanent write protection 220 uint32_t copy : 1; ///< [14] copy flag 221 uint32_t file_format_grp : 1; ///< [15] file format group 222 uint32_t reserved_20 : 5; ///< [20:16] 223 uint32_t 224 write_bl_partial : 1; ///< [21] partial blocks for write allowed 225 uint32_t write_bl_len : 4; ///< [25:22] max. write data block length 226 uint32_t r2w_factor : 3; ///< [28:26] write speed factor 227 uint32_t reserved_29 : 2; ///< [30:29] 228 uint32_t wp_grp_enable : 1; ///< [31] write protect group enable 229 uint32_t wp_grp_size : 7; ///< [38:32] write protect group size 230 uint32_t sector_size : 7; ///< [45:39] erase sector size 231 uint32_t erase_blk_en : 1; ///< [46] erase single block enable 232 uint32_t reserved_47 : 1; ///< [47] 233 uint32_t c_size : 22; ///< [69:48] device size 234 uint32_t reserved_70 : 6; ///< [75:70] 235 uint32_t dsr_imp : 1; ///< [76] dsr implemented 236 uint32_t read_blk_misalign : 1; ///< [77] read block misalignment 237 uint32_t write_blk_misalign : 1; ///< [78] write block misalignment 238 uint32_t read_bl_partial : 1; ///< [79] partial blocks for read allowed 239 uint32_t read_bl_len : 4; ///< [83:80] max read data block length 240 uint32_t ccc : 12; ///< [95:84] card command classes 241 uint32_t tran_speed : 8; ///< [103:96] max. data transfer rate 242 uint32_t nsac : 8; ///< [111:104] data read access-time-2 clk cycles 243 uint32_t taac : 8; ///< [119:112] data read access-time-1 244 uint32_t reserved_120 : 6; ///< [125:120] 245 uint32_t csd_structure : 2; ///< [127:126] csd structure 246 uint32_t reserved_128 : 8; ///< [135:128] 247 } csd_v2_b; 248 249 /* All structures in this union must be packed since some bitfields span 250 * more than one 32-bit word. */ 251 #if defined(__ICCARM__) 252 __packed struct 253 #elif defined(__GNUC__) 254 struct __attribute__((__packed__)) 255 #endif 256 { 257 uint32_t reserved_0 : 1; 258 259 uint32_t crc : 7; 260 uint32_t mfg_date : 12; 261 uint32_t reserved_23 : 4; 262 uint32_t serial_number : SDHI_PRV_CSD_CID_SERIAL_NUMBER_BITS; 263 uint32_t product_revision : 8; 264 uint64_t product_name : SDHI_PRV_CSD_CID_PRODUCT_NAME_BITS; 265 uint32_t oem_id : 16; 266 uint32_t mfg_id : 8; 267 uint32_t reserved_128 : 8; 268 } cid; 269 }; 270 } sdmmc_priv_csd_reg_t; 271 272 typedef union u_sdmmc_priv_sdio_arg_t { 273 uint32_t arg; 274 275 struct { 276 uint32_t data : 8; /* read/write data */ 277 uint32_t stuff_8 : 1; /* Stuff bit */ 278 uint32_t register_address : 17; /* Register Address */ 279 uint32_t stuff_26 : 1; /* Stuff bit should be set to 1 */ 280 uint32_t raw : 1; /* 1= Read after write. */ 281 uint32_t function_number : 3; /* function0~function7 */ 282 uint32_t rw_flag : 1; /* 0:read, 1:write */ 283 } cmd_52_arg; 284 285 struct { 286 uint32_t count : 9; /* Byte/Block Count */ 287 uint32_t register_address : 17; /* Register Address */ 288 uint32_t op_code : 1; /* 0:fixed address, 1:incrementing address */ 289 uint32_t block_mode : 1; /* 0: Byte, 1:Block */ 290 uint32_t function_number : 3; /* function0~function7 */ 291 uint32_t rw_flag : 1; /* 0:read, 1:write */ 292 } cmd_53_arg; 293 } sdmmc_priv_sdio_arg_t; 294 295 /** Common macro for FSP header files. There is also a corresponding FSP_HEADER 296 * macro at the top of this file. */ 297 FSP_FOOTER 298 299 #endif 300
