1 /* 2 * Copyright (c) 2022, ARM Limited and Contributors. All rights reserved. 3 * Copyright (c) 2022-2023, Intel Corporation. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef CDN_MMC_H 9 #define CDN_MMC_H 10 11 #include <drivers/cadence/cdns_combo_phy.h> 12 #include <drivers/mmc.h> 13 #include "socfpga_plat_def.h" 14 15 #if MMC_DEVICE_TYPE == 0 16 #define CONFIG_DMA_ADDR_T_64BIT 0 17 #endif 18 19 #define MMC_REG_BASE SOCFPGA_MMC_REG_BASE 20 #define COMBO_PHY_REG 0x0 21 #define SDHC_EXTENDED_WR_MODE_MASK 0xFFFFFFF7 22 #define SDHC_DLL_RESET_MASK 0x00000001 23 /* HRS09 */ 24 #define SDHC_PHY_SW_RESET BIT(0) 25 #define SDHC_PHY_INIT_COMPLETE BIT(1) 26 #define SDHC_EXTENDED_RD_MODE(x) ((x) << 2) 27 #define EXTENDED_WR_MODE 3 28 #define SDHC_EXTENDED_WR_MODE(x) ((x) << 3) 29 #define RDCMD_EN 15 30 #define SDHC_RDCMD_EN(x) ((x) << 15) 31 #define SDHC_RDDATA_EN(x) ((x) << 16) 32 33 /* CMD_DATA_OUTPUT */ 34 #define SDHC_CDNS_HRS16 0x40 35 36 /* This value determines the interval by which DAT line timeouts are detected */ 37 /* The interval can be computed as below: */ 38 /* • 1111b - Reserved */ 39 /* • 1110b - t_sdmclk*2(27+2) */ 40 /* • 1101b - t_sdmclk*2(26+2) */ 41 #define READ_CLK 0xa << 16 42 #define WRITE_CLK 0xe << 16 43 #define DTC_VAL 0xE 44 45 /* SRS00 */ 46 /* System Address / Argument 2 / 32-bit block count 47 * This field is used as: 48 * • 32-bit Block Count register 49 * • SDMA system memory address 50 * • Auto CMD23 Argument 51 */ 52 #define SAAR (1) 53 54 /* SRS01 */ 55 /* Transfer Block Size 56 * This field defines block size for block data transfers 57 */ 58 #define BLOCK_SIZE 0 59 60 /* SDMA Buffer Boundary 61 * System address boundary can be set for SDMA engine. 62 */ 63 #define SDMA_BUF 7 << 12 64 65 /* Block Count For Current Transfer 66 * To set the number of data blocks can be defined for next transfer 67 */ 68 #define BLK_COUNT_CT 16 69 70 /* SRS03 */ 71 #define CMD_START (U(1) << 31) 72 #define CMD_USE_HOLD_REG (1 << 29) 73 #define CMD_UPDATE_CLK_ONLY (1 << 21) 74 #define CMD_SEND_INIT (1 << 15) 75 #define CMD_STOP_ABORT_CMD (4 << 22) 76 #define CMD_RESUME_CMD (2 << 22) 77 #define CMD_SUSPEND_CMD (1 << 22) 78 #define DATA_PRESENT (1 << 21) 79 #define CMD_IDX_CHK_ENABLE (1 << 20) 80 #define CMD_WRITE (0 << 4) 81 #define CMD_READ (1 << 4) 82 #define MULTI_BLK_READ (1 << 5) 83 #define RESP_ERR (1 << 7) 84 #define CMD_CHECK_RESP_CRC (1 << 19) 85 #define RES_TYPE_SEL_48 (2 << 16) 86 #define RES_TYPE_SEL_136 (1 << 16) 87 #define RES_TYPE_SEL_48_B (3 << 16) 88 #define RES_TYPE_SEL_NO (0 << 16) 89 #define DMA_ENABLED (1 << 0) 90 #define BLK_CNT_EN (1 << 1) 91 #define AUTO_CMD_EN (2 << 2) 92 #define COM_IDX 24 93 #define ERROR_INT (1 << 15) 94 #define INT_SBE (1 << 13) 95 #define INT_HLE (1 << 12) 96 #define INT_FRUN (1 << 11) 97 #define INT_DRT (1 << 9) 98 #define INT_RTO (1 << 8) 99 #define INT_DCRC (1 << 7) 100 #define INT_RCRC (1 << 6) 101 #define INT_RXDR (1 << 5) 102 #define INT_TXDR (1 << 4) 103 #define INT_DTO (1 << 3) 104 #define INT_CMD_DONE (1 << 0) 105 #define TRAN_COMP (1 << 1) 106 107 /* SRS09 */ 108 #define STATUS_DATA_BUSY BIT(2) 109 110 /* SRS10 */ 111 /* LED Control 112 * State of this bit directly drives led port of the host 113 * in order to control the external LED diode 114 * Default value 0 << 1 115 */ 116 #define LEDC BIT(0) 117 #define LEDC_OFF 0 << 1 118 119 /* Data Transfer Width 120 * Bit used to configure DAT bus width to 1 or 4 121 * Default value 1 << 1 122 */ 123 #define DT_WIDTH BIT(1) 124 #define DTW_4BIT 1 << 1 125 126 /* Extended Data Transfer Width 127 * This bit is to enable/disable 8-bit DAT bus width mode 128 * Default value 1 << 5 129 */ 130 #define EDTW_8BIT 1 << 5 131 132 /* High Speed Enable 133 * Selects operating mode to Default Speed (HSE=0) or High Speed (HSE=1) 134 */ 135 #define HS_EN BIT(2) 136 137 /* here 0 defines the 64 Kb size */ 138 #define MAX_64KB_PAGE 0 139 #define EMMC_DESC_SIZE (1<<20) 140 141 /* SRS11 */ 142 /* Software Reset For All 143 * When set to 1, the entire slot is reset 144 * After completing the reset operation, SRFA bit is automatically cleared 145 */ 146 #define SRFA BIT(24) 147 148 /* Software Reset For CMD Line 149 * When set to 1, resets the logic related to the command generation and response checking 150 */ 151 #define SRCMD BIT(25) 152 153 /* Software Reset For DAT Line 154 * When set to 1, resets the logic related to the data path, 155 * including data buffers and the DMA logic 156 */ 157 #define SRDAT BIT(26) 158 159 /* SRS15 */ 160 /* UHS Mode Select 161 * Used to select one of UHS-I modes. 162 * • 000b - SDR12 163 * • 001b - SDR25 164 * • 010b - SDR50 165 * • 011b - SDR104 166 * • 100b - DDR50 167 */ 168 #define SDR12_MODE 0 << 16 169 #define SDR25_MODE 1 << 16 170 #define SDR50_MODE 2 << 16 171 #define SDR104_MODE 3 << 16 172 #define DDR50_MODE 4 << 16 173 /* 1.8V Signaling Enable 174 * • 0 - for Default Speed, High Speed mode 175 * • 1 - for UHS-I mode 176 */ 177 #define V18SE BIT(19) 178 179 /* CMD23 Enable 180 * In result of Card Identification process, 181 * Host Driver set this bit to 1 if Card supports CMD23 182 */ 183 #define CMD23_EN BIT(27) 184 185 /* Host Version 4.00 Enable 186 * • 0 - Version 3.00 187 * • 1 - Version 4.00 188 */ 189 #define HV4E BIT(28) 190 /* Conf depends on SRS15.HV4E */ 191 #define SDMA 0 << 3 192 #define ADMA2_32 2 << 3 193 #define ADMA2_64 3 << 3 194 195 /* Preset Value Enable 196 * Setting this bit to 1 triggers an automatically update of SRS11 197 */ 198 #define PVE BIT(31) 199 200 #define BIT_AD_32 0 << 29 201 #define BIT_AD_64 1 << 29 202 203 /* SW RESET REG*/ 204 #define SDHC_CDNS_HRS00 (0x00) 205 #define SDHC_CDNS_HRS00_SWR BIT(0) 206 207 /* PHY access port */ 208 #define SDHC_CDNS_HRS04 0x10 209 #define SDHC_CDNS_HRS04_ADDR GENMASK(5, 0) 210 211 /* PHY data access port */ 212 #define SDHC_CDNS_HRS05 0x14 213 214 /* eMMC control registers */ 215 #define SDHC_CDNS_HRS06 0x18 216 217 /* SRS */ 218 #define SDHC_CDNS_SRS_BASE 0x200 219 #define SDHC_CDNS_SRS00 0x200 220 #define SDHC_CDNS_SRS01 0x204 221 #define SDHC_CDNS_SRS02 0x208 222 #define SDHC_CDNS_SRS03 0x20c 223 #define SDHC_CDNS_SRS04 0x210 224 #define SDHC_CDNS_SRS05 0x214 225 #define SDHC_CDNS_SRS06 0x218 226 #define SDHC_CDNS_SRS07 0x21C 227 #define SDHC_CDNS_SRS08 0x220 228 #define SDHC_CDNS_SRS09 0x224 229 #define SDHC_CDNS_SRS09_CI BIT(16) 230 #define SDHC_CDNS_SRS10 0x228 231 #define SDHC_CDNS_SRS11 0x22C 232 #define SDHC_CDNS_SRS12 0x230 233 #define SDHC_CDNS_SRS13 0x234 234 #define SDHC_CDNS_SRS14 0x238 235 #define SDHC_CDNS_SRS15 0x23c 236 #define SDHC_CDNS_SRS21 0x254 237 #define SDHC_CDNS_SRS22 0x258 238 #define SDHC_CDNS_SRS23 0x25c 239 240 /* HRS07 */ 241 #define SDHC_CDNS_HRS07 0x1c 242 #define SDHC_IDELAY_VAL(x) ((x) << 0) 243 #define SDHC_RW_COMPENSATE(x) ((x) << 16) 244 245 /* PHY reset port */ 246 #define SDHC_CDNS_HRS09 0x24 247 248 /* HRS10 */ 249 /* PHY reset port */ 250 #define SDHC_CDNS_HRS10 0x28 251 252 /* HCSDCLKADJ DATA; DDR Mode */ 253 #define SDHC_HCSDCLKADJ(x) ((x) << 16) 254 255 /* Pinmux headers will reomove after ATF driver implementation */ 256 #define PINMUX_SDMMC_SEL 0x0 257 #define PIN0SEL 0x00 258 #define PIN1SEL 0x04 259 #define PIN2SEL 0x08 260 #define PIN3SEL 0x0C 261 #define PIN4SEL 0x10 262 #define PIN5SEL 0x14 263 #define PIN6SEL 0x18 264 #define PIN7SEL 0x1C 265 #define PIN8SEL 0x20 266 #define PIN9SEL 0x24 267 #define PIN10SEL 0x28 268 269 /* HRS16 */ 270 #define SDHC_WRCMD0_DLY(x) ((x) << 0) 271 #define SDHC_WRCMD1_DLY(x) ((x) << 4) 272 #define SDHC_WRDATA0_DLY(x) ((x) << 8) 273 #define SDHC_WRDATA1_DLY(x) ((x) << 12) 274 #define SDHC_WRCMD0_SDCLK_DLY(x) ((x) << 16) 275 #define SDHC_WRCMD1_SDCLK_DLY(x) ((x) << 20) 276 #define SDHC_WRDATA0_SDCLK_DLY(x) ((x) << 24) 277 #define SDHC_WRDATA1_SDCLK_DLY(x) ((x) << 28) 278 279 /* Shared Macros */ 280 #define SDMMC_CDN(_reg) (SDMMC_CDN_REG_BASE + \ 281 (SDMMC_CDN_##_reg)) 282 283 /* Refer to atf/tools/cert_create/include/debug.h */ 284 #define BIT_32(nr) (U(1) << (nr)) 285 286 /* MMC Peripheral Definition */ 287 #define SOCFPGA_MMC_BLOCK_SIZE U(8192) 288 #define SOCFPGA_MMC_BLOCK_MASK (SOCFPGA_MMC_BLOCK_SIZE - U(1)) 289 #define SOCFPGA_MMC_BOOT_CLK_RATE (400 * 1000) 290 #define MMC_RESPONSE_NONE 0 291 #define SDHC_CDNS_SRS03_VALUE 0x01020013 292 293 /* Value randomly chosen for eMMC RCA, it should be > 1 */ 294 #define MMC_FIX_RCA 6 295 #define RCA_SHIFT_OFFSET 16 296 297 #define CMD_EXTCSD_PARTITION_CONFIG 179 298 #define CMD_EXTCSD_BUS_WIDTH 183 299 #define CMD_EXTCSD_HS_TIMING 185 300 #define CMD_EXTCSD_SEC_CNT 212 301 302 #define PART_CFG_BOOT_PARTITION1_ENABLE (U(1) << 3) 303 #define PART_CFG_PARTITION1_ACCESS (U(1) << 0) 304 305 /* Values in EXT CSD register */ 306 #define MMC_BUS_WIDTH_1 U(0) 307 #define MMC_BUS_WIDTH_4 U(1) 308 #define MMC_BUS_WIDTH_8 U(2) 309 #define MMC_BUS_WIDTH_DDR_4 U(5) 310 #define MMC_BUS_WIDTH_DDR_8 U(6) 311 #define MMC_BOOT_MODE_BACKWARD (U(0) << 3) 312 #define MMC_BOOT_MODE_HS_TIMING (U(1) << 3) 313 #define MMC_BOOT_MODE_DDR (U(2) << 3) 314 315 #define EXTCSD_SET_CMD (U(0) << 24) 316 #define EXTCSD_SET_BITS (U(1) << 24) 317 #define EXTCSD_CLR_BITS (U(2) << 24) 318 #define EXTCSD_WRITE_BYTES (U(3) << 24) 319 #define EXTCSD_CMD(x) (((x) & 0xff) << 16) 320 #define EXTCSD_VALUE(x) (((x) & 0xff) << 8) 321 #define EXTCSD_CMD_SET_NORMAL U(1) 322 323 #define CSD_TRAN_SPEED_UNIT_MASK GENMASK(2, 0) 324 #define CSD_TRAN_SPEED_MULT_MASK GENMASK(6, 3) 325 #define CSD_TRAN_SPEED_MULT_SHIFT 3 326 327 #define STATUS_CURRENT_STATE(x) (((x) & 0xf) << 9) 328 #define STATUS_READY_FOR_DATA BIT(8) 329 #define STATUS_SWITCH_ERROR BIT(7) 330 #define MMC_GET_STATE(x) (((x) >> 9) & 0xf) 331 #define MMC_STATE_IDLE 0 332 #define MMC_STATE_READY 1 333 #define MMC_STATE_IDENT 2 334 #define MMC_STATE_STBY 3 335 #define MMC_STATE_TRAN 4 336 #define MMC_STATE_DATA 5 337 #define MMC_STATE_RCV 6 338 #define MMC_STATE_PRG 7 339 #define MMC_STATE_DIS 8 340 #define MMC_STATE_BTST 9 341 #define MMC_STATE_SLP 10 342 343 #define MMC_FLAG_CMD23 (U(1) << 0) 344 345 #define CMD8_CHECK_PATTERN U(0xAA) 346 #define VHS_2_7_3_6_V BIT(8) 347 348 /*ADMA table component*/ 349 #define ADMA_DESC_ATTR_VALID BIT(0) 350 #define ADMA_DESC_ATTR_END BIT(1) 351 #define ADMA_DESC_ATTR_INT BIT(2) 352 #define ADMA_DESC_ATTR_ACT1 BIT(4) 353 #define ADMA_DESC_ATTR_ACT2 BIT(5) 354 #define ADMA_DESC_TRANSFER_DATA ADMA_DESC_ATTR_ACT2 355 356 enum sd_opcode { 357 SD_GO_IDLE_STATE = 0, 358 SD_ALL_SEND_CID = 2, 359 SD_SEND_RELATIVE_ADDR = 3, 360 SDIO_SEND_OP_COND = 5, /* SDIO cards only */ 361 SD_SWITCH = 6, 362 SD_SELECT_CARD = 7, 363 SD_SEND_IF_COND = 8, 364 SD_SEND_CSD = 9, 365 SD_SEND_CID = 10, 366 SD_VOL_SWITCH = 11, 367 SD_STOP_TRANSMISSION = 12, 368 SD_SEND_STATUS = 13, 369 SD_GO_INACTIVE_STATE = 15, 370 SD_SET_BLOCK_SIZE = 16, 371 SD_READ_SINGLE_BLOCK = 17, 372 SD_READ_MULTIPLE_BLOCK = 18, 373 SD_SEND_TUNING_BLOCK = 19, 374 SD_SET_BLOCK_COUNT = 23, 375 SD_WRITE_SINGLE_BLOCK = 24, 376 SD_WRITE_MULTIPLE_BLOCK = 25, 377 SD_ERASE_BLOCK_START = 32, 378 SD_ERASE_BLOCK_END = 33, 379 SD_ERASE_BLOCK_OPERATION = 38, 380 SD_APP_CMD = 55, 381 SD_SPI_READ_OCR = 58, /* SPI mode only */ 382 SD_SPI_CRC_ON_OFF = 59, /* SPI mode only */ 383 }; 384 385 enum sd_app_cmd { 386 SD_APP_SET_BUS_WIDTH = 6, 387 SD_APP_SEND_STATUS = 13, 388 SD_APP_SEND_NUM_WRITTEN_BLK = 22, 389 SD_APP_SET_WRITE_BLK_ERASE_CNT = 23, 390 SD_APP_SEND_OP_COND = 41, 391 SD_APP_CLEAR_CARD_DETECT = 42, 392 SD_APP_SEND_SCR = 51, 393 }; 394 395 struct cdns_sdmmc_sdhc { 396 uint32_t sdhc_extended_rd_mode; 397 uint32_t sdhc_extended_wr_mode; 398 uint32_t sdhc_hcsdclkadj; 399 uint32_t sdhc_idelay_val; 400 uint32_t sdhc_rdcmd_en; 401 uint32_t sdhc_rddata_en; 402 uint32_t sdhc_rw_compensate; 403 uint32_t sdhc_sdcfsh; 404 uint32_t sdhc_sdcfsl; 405 uint32_t sdhc_wrcmd0_dly; 406 uint32_t sdhc_wrcmd0_sdclk_dly; 407 uint32_t sdhc_wrcmd1_dly; 408 uint32_t sdhc_wrcmd1_sdclk_dly; 409 uint32_t sdhc_wrdata0_dly; 410 uint32_t sdhc_wrdata0_sdclk_dly; 411 uint32_t sdhc_wrdata1_dly; 412 uint32_t sdhc_wrdata1_sdclk_dly; 413 }; 414 415 enum sdmmc_device_mode { 416 SD_DS_ID, /* Identification */ 417 SD_DS, /* Default speed */ 418 SD_HS, /* High speed */ 419 SD_UHS_SDR12, /* Ultra high speed SDR12 */ 420 SD_UHS_SDR25, /* Ultra high speed SDR25 */ 421 SD_UHS_SDR50, /* Ultra high speed SDR`50 */ 422 SD_UHS_SDR104, /* Ultra high speed SDR104 */ 423 SD_UHS_DDR50, /* Ultra high speed DDR50 */ 424 EMMC_SDR_BC, /* SDR backward compatible */ 425 EMMC_SDR, /* SDR */ 426 EMMC_DDR, /* DDR */ 427 EMMC_HS200, /* High speed 200Mhz in SDR */ 428 EMMC_HS400, /* High speed 200Mhz in DDR */ 429 EMMC_HS400es, /* High speed 200Mhz in SDR with enhanced strobe*/ 430 }; 431 432 struct cdns_sdmmc_params { 433 uintptr_t reg_base; 434 uintptr_t reg_pinmux; 435 uintptr_t reg_phy; 436 uintptr_t desc_base; 437 size_t desc_size; 438 int clk_rate; 439 int bus_width; 440 unsigned int flags; 441 enum sdmmc_device_mode cdn_sdmmc_dev_mode; 442 enum mmc_device_type cdn_sdmmc_dev_type; 443 uint32_t combophy; 444 }; 445 446 /* read and write API */ 447 size_t sdmmc_read_blocks(int lba, uintptr_t buf, size_t size); 448 size_t sdmmc_write_blocks(int lba, const uintptr_t buf, size_t size); 449 450 struct cdns_idmac_desc { 451 /*8 bit attribute*/ 452 uint8_t attr; 453 /*reserved bits in desc*/ 454 uint8_t reserved; 455 /*page length for the descriptor*/ 456 uint16_t len; 457 /*lower 32 bits for buffer (64 bit addressing)*/ 458 uint32_t addr_lo; 459 #if CONFIG_DMA_ADDR_T_64BIT == 1 460 /*higher 32 bits for buffer (64 bit addressing)*/ 461 uint32_t addr_hi; 462 } __aligned(8); 463 #else 464 } __packed; 465 #endif 466 467 468 469 /* Function Prototype */ 470 int cdns_sd_host_init(struct cdns_sdmmc_combo_phy *mmc_combo_phy_reg, 471 struct cdns_sdmmc_sdhc *mmc_sdhc_reg); 472 void cdns_set_sdmmc_var(struct cdns_sdmmc_combo_phy *combo_phy_reg, 473 struct cdns_sdmmc_sdhc *sdhc_reg); 474 #endif 475
