1 /*
2  * Copyright (c) 2021, Arm Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  *
6  */
7 
8 #ifndef __CORE_EXT_H__
9 #define __CORE_EXT_H__
10 
11 /* Coprocessor Power Control Register Definitions */
12 #define SCnSCB_CPPWR_SUS11_Pos              23U                                        /*!< CPPWR: SUS11 Position */
13 #define SCnSCB_CPPWR_SUS11_Msk              (1UL << SCnSCB_CPPWR_SUS11_Pos)            /*!< CPPWR: SUS11 Mask */
14 
15 #define SCnSCB_CPPWR_SU11_Pos               22U                                        /*!< CPPWR: SU11 Position */
16 #define SCnSCB_CPPWR_SU11_Msk               (1UL << SCnSCB_CPPWR_SU11_Pos)             /*!< CPPWR: SU11 Mask */
17 
18 #define SCnSCB_CPPWR_SUS10_Pos              21U                                        /*!< CPPWR: SUS10 Position */
19 #define SCnSCB_CPPWR_SUS10_Msk              (1UL << SCnSCB_CPPWR_SUS10_Pos)            /*!< CPPWR: SUS10 Mask */
20 
21 #define SCnSCB_CPPWR_SU10_Pos               20U                                        /*!< CPPWR: SU10 Position */
22 #define SCnSCB_CPPWR_SU10_Msk               (1UL << SCnSCB_CPPWR_SU10_Pos)             /*!< CPPWR: SU10 Mask */
23 
24 #endif /* __CORE_EXT_H__ */
25