1 /**************************************************************************//** 2 * @file sc_reg.h 3 * @version V1.00 4 * @brief SC register definition header file 5 * 6 * SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __SC_REG_H__ 10 #define __SC_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /** 17 @addtogroup REGISTER Control Register 18 @{ 19 */ 20 21 /** 22 @addtogroup SC Smart Card Host Interface Controller(SC) 23 Memory Mapped Structure for SC Controller 24 @{ */ 25 26 typedef struct 27 { 28 29 30 /** 31 * @var SC_T::DAT 32 * Offset: 0x00 SC Receive/Transmit Holding Buffer Register 33 * --------------------------------------------------------------------------------------------------- 34 * |Bits |Field |Descriptions 35 * | :----: | :----: | :---- | 36 * |[7:0] |DAT |Receive/Transmit Holding Buffer 37 * | | |Write Operation: 38 * | | |By writing data to DAT, the SC will send out an 8-bit data. 39 * | | |Note: If SCEN (SCn_CTL[0]) is not enabled, DAT cannot be programmed. 40 * | | |Read Operation: 41 * | | |By reading DAT, the SC will return an 8-bit received data. 42 * @var SC_T::CTL 43 * Offset: 0x04 SC Control Register 44 * --------------------------------------------------------------------------------------------------- 45 * |Bits |Field |Descriptions 46 * | :----: | :----: | :---- | 47 * |[0] |SCEN |SC Controller Enable Bit 48 * | | |Set this bit to 1 to enable SC operation. If this bit is cleared, 49 * | | |0 = SC will force all transition to IDLE state. 50 * | | |1 = SC controller is enabled and all function can work correctly. 51 * | | |Note1: SCEN must be set to 1 before filling in other SC registers, or smart card will not work properly. 52 * |[1] |RXOFF |RX Transition Disable Control Bit 53 * | | |This bit is used for disable Rx transition function. 54 * | | |0 = The receiver Enabled. 55 * | | |1 = The receiver Disabled. 56 * | | |Note1: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 57 * |[2] |TXOFF |TX Transition Disable Control Bit 58 * | | |This bit is used for disable Tx transition function. 59 * | | |0 = The transceiver Enabled. 60 * | | |1 = The transceiver Disabled. 61 * |[3] |AUTOCEN |Auto Convention Enable Bit 62 * | | |This bit is used for enable auto convention function. 63 * | | |0 = Auto-convention Disabled. 64 * | | |1 = Auto-convention Enabled. 65 * | | |If user enables auto convention function, the setting step must be done before Answer to Reset (ATR) 66 * | | |state and the first data must be 0x3B or 0x3F. 67 * | | |After hardware received first data and stored it at buffer, hardware will decided the convention and 68 * | | |change the CONSEL (SCn_CTL[5:4]) bits automatically when received first data is 0x3B or 0x3F. 69 * | | |If received first byte is 0x3B, TS is direct convention, CONSEL (SCn_CTL[5:4]) will be set to 00 70 * | | |automatically, otherwise the TS is inverse convention, and CONSEL (SCn_CTL[5:4]) will be set to 11. 71 * | | |If the first data is not 0x3B or 0x3F, hardware will set ACERRIF (SCn_INTSTS[10]) and generate an 72 * | | |interrupt to CPU when ACERRIEN (SCn_INTEN[10]) is enabled. 73 * |[5:4] |CONSEL |Convention Selection 74 * | | |00 = Direct convention. 75 * | | |01 = Reserved. 76 * | | |10 = Reserved. 77 * | | |11 = Inverse convention. 78 * | | |Note: If AUTOCEN (SCn_CTL[3]) is enabled, this field is ignored. 79 * |[7:6] |RXTRGLV |Rx Buffer Trigger Level 80 * | | |When the number of bytes in the receiving buffer equals the RXTRGLV, the RDAIF will be set 81 * | | |If RDAIEN (SCn_INTEN[0]) is enabled, an interrupt will be generated to CPU. 82 * | | |00 = Rx Buffer Trigger Level with 01 bytes. 83 * | | |01 = Rx Buffer Trigger Level with 02 bytes. 84 * | | |10 = Rx Buffer Trigger Level with 03 bytes. 85 * | | |11 = Reserved. 86 * |[12:8] |BGT |Block Guard Time (BGT) 87 * | | |Block guard time means the minimum interval between the leading edges of two consecutive characters 88 * | | |between different transfer directions 89 * | | |This field indicates the counter for the bit length of block guard time 90 * | | |According to ISO 7816-3, in T = 0 mode, user must fill 15 (real block guard time = 16.5) to this 91 * | | |field; in T = 1 mode, user must fill 21 (real block guard time = 22.5) to it. 92 * | | |Note: The real block guard time is BGT + 1. 93 * |[14:13] |TMRSEL |Timer Channel Selection 94 * | | |00 = All internal timer function Disabled. 95 * | | |11 = Internal 24 bit timer and two 8 bit timers Enabled 96 * | | |User can configure them by setting SCn_TMRCTL0[23:0], SCn_TMRCTL1[7:0] and SCn_TMRCTL2[7:0]. 97 * | | |Other configurations are reserved 98 * |[15] |NSB |Stop Bit Length 99 * | | |This field indicates the length of stop bit. 100 * | | |0 = The stop bit length is 2 ETU. 101 * | | |1= The stop bit length is 1 ETU. 102 * | | |Note1: The default stop bit length is 2. SC and UART adopts NSB to program the stop bit length. 103 * | | |Note2: In UART mode, RX can receive the data sequence in 1 stop bit or 2 stop bits with NSB is set to 0. 104 * |[18:16] |RXRTY |RX Error Retry Count Number 105 * | | |This field indicates the maximum number of receiver retries that are allowed when parity error has occurred. 106 * | | |Note1: The real retry number is RXRTY + 1, so 8 is the maximum retry number. 107 * | | |Note2: This field cannot be changed when RXRTYEN enabled 108 * | | |The change flow is to disable RXRTYEN first and then fill in new retry value. 109 * |[19] |RXRTYEN |RX Error Retry Enable Bit 110 * | | |This bit enables receiver retry function when parity error has occurred. 111 * | | |0 = RX error retry function Disabled. 112 * | | |1 = RX error retry function Enabled. 113 * | | |Note: User must fill in the RXRTY value before enabling this bit. 114 * |[22:20] |TXRTY |TX Error Retry Count Number 115 * | | |This field indicates the maximum number of transmitter retries that are allowed when parity 116 * | | |error has occurred. 117 * | | |Note1: The real retry number is TXRTY + 1, so 8 is the maximum retry number. 118 * | | |Note2: This field cannot be changed when TXRTYEN enabled 119 * | | |The change flow is to disable TXRTYEN first and then fill in new retry value. 120 * |[23] |TXRTYEN |TX Error Retry Enable Bit 121 * | | |This bit enables transmitter retry function when parity error has occurred. 122 * | | |0 = TX error retry function Disabled. 123 * | | |1 = TX error retry function Enabled. 124 * |[25:24] |CDDBSEL |Card Detect De-bounce Selection 125 * | | |This field indicates the card detect de-bounce selection. 126 * | | |00 = De-bounce sample card insert once per 384 (128 * 3) SC module clocks and de-bounce 127 * | | |sample card removal once per 128 SC module clocks. 128 * | | |Other configurations are reserved. 129 * |[26] |CDLV |Card Detect Level Selection 130 * | | |0 = When hardware detects the card detect pin (SCn_CD) from high to low, it indicates a card is detected. 131 * | | |1 = When hardware detects the card detect pin (SCn_CD) from low to high, it indicates a card is detected. 132 * | | |Note: User must select card detect level before Smart Card controller enabled. 133 * |[30] |SYNC |SYNC Flag Indicator (Read Only) 134 * | | |Due to synchronization, user should check this bit before writing a new value to RXRTY and TXRTY fields. 135 * | | |0 = Synchronizing is completion, user can write new data to RXRTY and TXRTY. 136 * | | |1 = Last value is synchronizing. 137 * @var SC_T::ALTCTL 138 * Offset: 0x08 SC Alternate Control Register 139 * --------------------------------------------------------------------------------------------------- 140 * |Bits |Field |Descriptions 141 * | :----: | :----: | :---- | 142 * |[0] |TXRST |TX Software Reset 143 * | | |When TXRST is set, all the bytes in the transmit buffer and TX internal state machine will be cleared. 144 * | | |0 = No effect. 145 * | | |1 = Reset the TX internal state machine and pointers. 146 * | | |Note: This bit will be auto cleared after reset is complete. 147 * |[1] |RXRST |Rx Software Reset 148 * | | |When RXRST is set, all the bytes in the receive buffer and Rx internal state machine will be cleared. 149 * | | |0 = No effect. 150 * | | |1 = Reset the Rx internal state machine and pointers. 151 * | | |Note: This bit will be auto cleared after reset is complete. 152 * |[2] |DACTEN |Deactivation Sequence Generator Enable Bit 153 * | | |This bit enables SC controller to initiate the card by deactivation sequence. 154 * | | |0 = No effect. 155 * | | |1 = Deactivation sequence generator Enabled. 156 * | | |Note1: When the deactivation sequence completed, this bit will be cleared automatically and 157 * | | |the INITIF (SCn_INTSTS[8]) will be set to 1. 158 * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) 159 * | | |Thus, do not fill in this bit DACTEN, TXRST and RXRST at the same time. 160 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 161 * |[3] |ACTEN |Activation Sequence Generator Enable Bit 162 * | | |This bit enables SC controller to initiate the card by activation sequence. 163 * | | |0 = No effect. 164 * | | |1 = Activation sequence generator Enabled. 165 * | | |Note1: When the activation sequence completed, this bit will be cleared automatically and the 166 * | | |INITIF (SCn_INTSTS[8]) will be set to 1. 167 * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) 168 * | | |Thus, do not fill in this bit ACTEN, TXRST and RXRST at the same time. 169 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 170 * | | |Note4: During the activation sequence, RX is disabled automatically and can not receive data 171 * | | |After the activation sequence completion, RXOFF (SCn_CTL[1]) keeps the state before hardware activation. 172 * |[4] |WARSTEN |Warm Reset Sequence Generator Enable Bit 173 * | | |This bit enables SC controller to initiate the card by warm reset sequence. 174 * | | |0 = No effect. 175 * | | |1 = Warm reset sequence generator Enabled. 176 * | | |Note1: When the warm reset sequence completed, this bit will be cleared automatically and the 177 * | | |INITIF (SCn_INTSTS[8]) will be set to 1. 178 * | | |Note2: This field will be cleared by TXRST (SCn_ALTCTL[0]) and RXRST (SCn_ALTCTL[1]) 179 * | | |Thus, do not fill in this bit WARSTEN, TXRST and RXRST at the same time. 180 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 181 * | | |Note4: During the warm reset sequence, RX is disabled automatically and can not receive data 182 * | | |After the warm reset sequence completion, RXOFF (SCn_CTL[1]) keeps the state before perform 183 * | | |warm reset sequence. 184 * |[5] |CNTEN0 |Internal Timer0 Start Enable Bit 185 * | | |This bit enables Timer 0 to start counting 186 * | | |User can fill 0 to stop it and set 1 to reload and count 187 * | | |The counter unit is ETU base. 188 * | | |0 = Stops counting. 189 * | | |1 = Start counting. 190 * | | |Note1: This field is used for internal 24 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only. 191 * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL0[26] = 0), this bit will 192 * | | |be auto-cleared by hardware. 193 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 194 * |[6] |CNTEN1 |Internal Timer1 Start Enable Bit 195 * | | |This bit enables Timer 1 to start counting 196 * | | |User can fill 0 to stop it and set 1 to reload and count 197 * | | |The counter unit is ETU base. 198 * | | |0 = Stops counting. 199 * | | |1 = Start counting. 200 * | | |Note1: This field is used for internal 8 bit timer when TMRSEL(SCn_CTL[14:13]) is 11 only 201 * | | |Do not fill CNTEN1 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. 202 * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL1[26] = 0), this bit will 203 * | | |be auto-cleared by hardware. 204 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 205 * |[7] |CNTEN2 |Internal Timer2 Start Enable Bit 206 * | | |This bit enables Timer 2 to start counting 207 * | | |User can fill 0 to stop it and set 1 to reload and count 208 * | | |The counter unit is ETU base. 209 * | | |0 = Stops counting. 210 * | | |1 = Start counting. 211 * | | |Note1: This field is used for internal 8 bit timer when TMRSEL (SCn_CTL[14:13]) is 11 only 212 * | | |Do not fill in CNTEN2 when TMRSEL (SCn_CTL[14:13]) is not equal to 11. 213 * | | |Note2: If the operation mode is not in auto-reload mode (SCn_TMRCTL2[26] = 0), this bit will 214 * | | |be auto-cleared by hardware. 215 * | | |Note3: If SCEN (SCn_CTL[0]) is not enabled, this filed cannot be programmed. 216 * |[9:8] |INITSEL |Initial Timing Selection 217 * | | |This fields indicates the initial timing of hardware activation, warm-reset or deactivation. 218 * | | |The unit of initial timing is SC module clock. 219 * | | |Activation: refer to SC Activation Sequence in Figure 7.17-54. 220 * | | |Warm-reset: refer to Warm-Reset Sequence in Figure 7.17-5. 221 * | | |Deactivation: refer to Deactivation Sequence in Figure 7.17-56. 222 * | | |Note: When set activation and warm reset in Timer0 operation mode 0011, it may have deviation 223 * | | |at most 128 SC module clock cycles. 224 * |[11] |ADACEN |Auto Deactivation When Card Removal 225 * | | |This bit is used for enable hardware auto deactivation when smart card is removed. 226 * | | |0 = Auto deactivation Disabled. 227 * | | |1 = Auto deactivation Enabled. 228 * | | |Note: When the card is removed, hardware will stop any process and then do deactivation sequence 229 * | | |if this bit is set 230 * | | |If auto deactivation process completes, hardware will set INITIF (SCn_INTSTS[8]) also. 231 * |[12] |RXBGTEN |Receiver Block Guard Time Function Enable Bit 232 * | | |This bit enables the receiver block guard time function. 233 * | | |0 = Receiver block guard time function Disabled. 234 * | | |1 = Receiver block guard time function Enabled. 235 * |[13] |ACTSTS0 |Internal Timer0 Active Status (Read Only) 236 * | | |This bit indicates the timer counter status of timer0. 237 * | | |0 = Timer0 is not active. 238 * | | |1 = Timer0 is active. 239 * | | |Note: Timer0 is active does not always mean timer0 is counting the CNT (SCn_TMRCTL0[23:0]). 240 * |[14] |ACTSTS1 |Internal Timer1 Active Status (Read Only) 241 * | | |This bit indicates the timer counter status of timer1. 242 * | | |0 = Timer1 is not active. 243 * | | |1 = Timer1 is active. 244 * | | |Note: Timer1 is active does not always mean timer1 is counting the CNT (SCn_TMRCTL1[7:0]). 245 * |[15] |ACTSTS2 |Internal Timer2 Active Status (Read Only) 246 * | | |This bit indicates the timer counter status of timer2. 247 * | | |0 = Timer2 is not active. 248 * | | |1 = Timer2 is active. 249 * | | |Note: Timer2 is active does not always mean timer2 is counting the CNT (SCn_TMRCTL2[7:0]). 250 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 251 * | | |Due to synchronization, user should check this bit when writing a new value to SCn_ALTCTL register. 252 * | | |0 = Synchronizing is completion, user can write new data to SCn_ALTCTL register. 253 * | | |1 = Last value is synchronizing. 254 * @var SC_T::EGT 255 * Offset: 0x0C SC Extra Guard Time Register 256 * --------------------------------------------------------------------------------------------------- 257 * |Bits |Field |Descriptions 258 * | :----: | :----: | :---- | 259 * |[7:0] |EGT |Extra Guard Time 260 * | | |This field indicates the extra guard time value. 261 * | | |Note: The extra guard time unit is ETU base. 262 * @var SC_T::RXTOUT 263 * Offset: 0x10 SC Receive Buffer Time-out Counter Register 264 * --------------------------------------------------------------------------------------------------- 265 * |Bits |Field |Descriptions 266 * | :----: | :----: | :---- | 267 * |[8:0] |RFTM |SC Receiver FIFO Time-out Counter 268 * | | |The time-out down counter resets and starts counting whenever the RX buffer received a new data 269 * | | |Once the counter decrease to 1 and no new data is received or CPU does not read data by 270 * | | |reading SCn_DAT, a receiver time-out flag RBTOIF (SCn_INTSTS[9]) will be set, and hardware will 271 * | | |generate an interrupt to CPU when RBTOIEN (SCn_INTEN[9]) is enabled. 272 * | | |Note1: The counter unit is ETU based and the interval of time-out is RFTM + 0.5. 273 * | | |Note2: Filling in all 0 to this field indicates to disable this function. 274 * @var SC_T::ETUCTL 275 * Offset: 0x14 SC Element Time Unit Control Register 276 * --------------------------------------------------------------------------------------------------- 277 * |Bits |Field |Descriptions 278 * | :----: | :----: | :---- | 279 * |[11:0] |ETURDIV |ETU Rate Divider 280 * | | |The field is used for ETU clock rate divider. 281 * | | |The real ETU is ETURDIV + 1. 282 * | | |Note: User can configure this field, but this field must be greater than 0x04. 283 * @var SC_T::INTEN 284 * Offset: 0x18 SC Interrupt Enable Control Register 285 * --------------------------------------------------------------------------------------------------- 286 * |Bits |Field |Descriptions 287 * | :----: | :----: | :---- | 288 * |[0] |RDAIEN |Receive Data Reach Interrupt Enable Bit 289 * | | |This field is used to enable received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt. 290 * | | |0 = Receive data reach trigger level interrupt Disabled. 291 * | | |1 = Receive data reach trigger level interrupt Enabled. 292 * |[1] |TBEIEN |Transmit Buffer Empty Interrupt Enable Bit 293 * | | |This field is used to enable transmit buffer empty interrupt. 294 * | | |0 = Transmit buffer empty interrupt Disabled. 295 * | | |1 = Transmit buffer empty interrupt Enabled. 296 * |[2] |TERRIEN |Transfer Error Interrupt Enable Bit 297 * | | |This field is used to enable transfer error interrupt 298 * | | |The transfer error states is at SCn_STATUS register which includes receiver break error 299 * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5]), parity error PEF (SCn_STATUS[4]), receive 300 * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), 301 * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22]) and transmitter retry over limit error 302 * | | |TXOVERR (SCn_STATUS[30]). 303 * | | |0 = Transfer error interrupt Disabled. 304 * | | |1 = Transfer error interrupt Enabled. 305 * |[3] |TMR0IEN |Timer0 Interrupt Enable Bit 306 * | | |This field is used to enable Timer0 interrupt function. 307 * | | |0 = Timer0 interrupt Disabled. 308 * | | |1 = Timer0 interrupt Enabled. 309 * |[4] |TMR1IEN |Timer1 Interrupt Enable Bit 310 * | | |This field is used to enable the Timer1 interrupt function. 311 * | | |0 = Timer1 interrupt Disabled. 312 * | | |1 = Timer1 interrupt Enabled. 313 * |[5] |TMR2IEN |Timer2 Interrupt Enable Bit 314 * | | |This field is used to enable Timer2 interrupt function. 315 * | | |0 = Timer2 interrupt Disabled. 316 * | | |1 = Timer2 interrupt Enabled. 317 * |[6] |BGTIEN |Block Guard Time Interrupt Enable Bit 318 * | | |This field is used to enable block guard time interrupt in receive direction. 319 * | | |0 = Block guard time interrupt Disabled. 320 * | | |1 = Block guard time interrupt Enabled. 321 * | | |Note: This bit is valid only for receive direction block guard time. 322 * |[7] |CDIEN |Card Detect Interrupt Enable Bit 323 * | | |This field is used to enable card detect interrupt 324 * | | |The card detect status is CDPINSTS (SCn_STATUS[13]). 325 * | | |0 = Card detect interrupt Disabled. 326 * | | |1 = Card detect interrupt Enabled. 327 * |[8] |INITIEN |Initial End Interrupt Enable Bit 328 * | | |This field is used to enable activation (ACTEN (SCn_ALTCTL[3] = 1)), deactivation 329 * | | |(DACTEN (SCn_ALTCTL[2] = 1)) and warm reset (WARSTEN (SCn_ALTCTL [4])) sequence complete interrupt. 330 * | | |0 = Initial end interrupt Disabled. 331 * | | |1 = Initial end interrupt Enabled. 332 * |[9] |RXTOIEN |Receiver Buffer Time-out Interrupt Enable Bit 333 * | | |This field is used to enable receiver buffer time-out interrupt. 334 * | | |0 = Receiver buffer time-out interrupt Disabled. 335 * | | |1 = Receiver buffer time-out interrupt Enabled. 336 * |[10] |ACERRIEN |Auto Convention Error Interrupt Enable Bit 337 * | | |This field is used to enable auto-convention error interrupt. 338 * | | |0 = Auto-convention error interrupt Disabled. 339 * | | |1 = Auto-convention error interrupt Enabled. 340 * @var SC_T::INTSTS 341 * Offset: 0x1C SC Interrupt Status Register 342 * --------------------------------------------------------------------------------------------------- 343 * |Bits |Field |Descriptions 344 * | :----: | :----: | :---- | 345 * |[0] |RDAIF |Receive Data Reach Interrupt Status Flag (Read Only) 346 * | | |This field is used for received data reaching trigger level RXTRGLV (SCn_CTL[7:6]) interrupt status flag. 347 * | | |0 = Number of receive buffer is less than RXTRGLV setting. 348 * | | |1 = Number of receive buffer data equals the RXTRGLV setting. 349 * | | |Note: This bit is read only 350 * | | |If user reads data from SCn_DAT and receiver buffer data byte number is less than RXTRGLV, 351 * | | |this bit will be cleared automatically. 352 * |[1] |TBEIF |Transmit Buffer Empty Interrupt Status Flag (Read Only) 353 * | | |This field is used for transmit buffer empty interrupt status flag. 354 * | | |0 = Transmit buffer is not empty. 355 * | | |1 = Transmit buffer is empty. 356 * | | |Note: This bit is read only 357 * | | |If user wants to clear this bit, user must write data to DAT (SCn_DAT[7:0]) and then this bit 358 * | | |will be cleared automatically. 359 * |[2] |TERRIF |Transfer Error Interrupt Status Flag 360 * | | |This field is used for transfer error interrupt status flag 361 * | | |The transfer error states is at SCn_STATUS register which includes receiver break error 362 * | | |BEF (SCn_STATUS[6]), frame error FEF (SCn_STATUS[5], parity error PEF (SCn_STATUS[4] and receive 363 * | | |buffer overflow error RXOV (SCn_STATUS[0]), transmit buffer overflow error TXOV (SCn_STATUS[8]), 364 * | | |receiver retry over limit error RXOVERR (SCn_STATUS[22] or transmitter retry over limit error 365 * | | |TXOVERR (SCn_STATUS[30]). 366 * | | |0 = Transfer error interrupt did not occur. 367 * | | |1 = Transfer error interrupt occurred. 368 * | | |Note1: This field is the status flag of BEF, FEF, PEF, RXOV, TXOV, RXOVERR or TXOVERR. 369 * | | |Note2: This bit can be cleared by writing 1 to it. 370 * |[3] |TMR0IF |Timer0 Interrupt Status Flag 371 * | | |This field is used for Timer0 interrupt status flag. 372 * | | |0 = Timer0 interrupt did not occur. 373 * | | |1 = Timer0 interrupt occurred. 374 * | | |Note: This bit can be cleared by writing 1 to it. 375 * |[4] |TMR1IF |Timer1 Interrupt Status Flag 376 * | | |This field is used for Timer1 interrupt status flag. 377 * | | |0 = Timer1 interrupt did not occur. 378 * | | |1 = Timer1 interrupt occurred. 379 * | | |Note: This bit can be cleared by writing 1 to it. 380 * |[5] |TMR2IF |Timer2 Interrupt Status Flag 381 * | | |This field is used for Timer2 interrupt status flag. 382 * | | |0 = Timer2 interrupt did not occur. 383 * | | |1 = Timer2 interrupt occurred. 384 * | | |Note: This bit can be cleared by writing 1 to it. 385 * |[6] |BGTIF |Block Guard Time Interrupt Status Flag 386 * | | |This field is used for indicate block guard time interrupt status flag in receive direction. 387 * | | |0 = Block guard time interrupt did not occur. 388 * | | |1 = Block guard time interrupt occurred. 389 * | | |Note1: This bit is valid only when RXBGTEN (SCn_ALTCTL[12]) is enabled. 390 * | | |Note2: This bit can be cleared by writing 1 to it. 391 * |[7] |CDIF |Card Detect Interrupt Status Flag (Read Only) 392 * | | |This field is used for card detect interrupt status flag 393 * | | |The card detect status is CINSERT (SCn_STATUS[12]) and CREMOVE (SCn_STATUS[11]). 394 * | | |0 = Card detect event did not occur. 395 * | | |1 = Card detect event occurred. 396 * | | |Note: This bit is read only, user must to clear CINSERT or CREMOVE status to clear it. 397 * |[8] |INITIF |Initial End Interrupt Status Flag 398 * | | |This field is used for activation (ACTEN (SCn_ALTCTL[3])), deactivation (DACTEN (SCn_ALTCTL[2])) 399 * | | |and warm reset (WARSTEN (SCn_ALTCTL[4])) sequence interrupt status flag. 400 * | | |0 = Initial sequence is not complete. 401 * | | |1 = Initial sequence is completed. 402 * | | |Note: This bit can be cleared by writing 1 to it. 403 * |[9] |RXTOIF |Receive Buffer Time-out Interrupt Status Flag (Read Only) 404 * | | |This field is used for indicate receive buffer time-out interrupt status flag. 405 * | | |0 = Receive buffer time-out interrupt did not occur. 406 * | | |1 = Receive buffer time-out interrupt occurred. 407 * | | |Note: This bit is read only, user must read all receive buffer remaining data by reading SCn_DAT 408 * | | |register to clear it. 409 * |[10] |ACERRIF |Auto Convention Error Interrupt Status Flag 410 * | | |This field indicates auto convention sequence error. 411 * | | |0 = Received TS at ATR state is 0x3B or 0x3F. 412 * | | |1 = Received TS at ATR state is neither 0x3B nor 0x3F. 413 * | | |Note: This bit can be cleared by writing 1 to it. 414 * @var SC_T::STATUS 415 * Offset: 0x20 SC Transfer Status Register 416 * --------------------------------------------------------------------------------------------------- 417 * |Bits |Field |Descriptions 418 * | :----: | :----: | :---- | 419 * |[0] |RXOV |Receive Overflow Error Status Flag 420 * | | |This bit is set when Rx buffer overflow. 421 * | | |0 = Rx buffer is not overflow. 422 * | | |1 = Rx buffer is overflow when the number of received bytes is greater than Rx buffer size (4 bytes). 423 * | | |Note: This bit can be cleared by writing 1 to it. 424 * |[1] |RXEMPTY |Receive Buffer Empty Status Flag (Read Only) 425 * | | |This bit indicates Rx buffer empty or not. 426 * | | |0 = Rx buffer is not empty. 427 * | | |1 = Rx buffer is empty, it means the last byte of Rx buffer has read from DAT (SCn_DAT[7:0]) by CPU. 428 * |[2] |RXFULL |Receive Buffer Full Status Flag (Read Only) 429 * | | |This bit indicates Rx buffer full or not. 430 * | | |0 = Rx buffer count is less than 4. 431 * | | |1 = Rx buffer count equals to 4. 432 * |[4] |PEF |Receiver Parity Error Status Flag 433 * | | |This bit is set to logic 1 whenever the received character does not have a valid parity bit. 434 * | | |0 = Receiver parity error flag did not occur. 435 * | | |1 = Receiver parity error flag occurred. 436 * | | |Note1: This bit can be cleared by writing 1 to it. 437 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not 438 * | | |set this flag. 439 * |[5] |FEF |Receiver Frame Error Status Flag 440 * | | |This bit is set to logic 1 whenever the received character does not have a valid stop bit (that is, 441 * | | |the stop bit following the last data bit or parity bit is detected as logic 0). 442 * | | |0 = Receiver frame error flag did not occur. 443 * | | |1 = Receiver frame error flag occurred. 444 * | | |Note1: This bit can be cleared by writing 1 to it. 445 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not 446 * | | |set this flag. 447 * |[6] |BEF |Receiver Break Error Status Flag 448 * | | |This bit is set to logic 1 whenever the received data input (Rx) held in the spacing state 449 * | | |(logic 0) is longer than a full word transmission time (that is, the total time of start bit + 450 * | | |data bits + parity bit + stop bit). 451 * | | |0 = Receiver break error flag did not occur. 452 * | | |1 = Receiver break error flag occurred. 453 * | | |Note1: This bit can be cleared by writing 1 to it. 454 * | | |Note2: If CPU sets receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware will not set 455 * | | |this flag. 456 * |[8] |TXOV |Transmit Overflow Error Interrupt Status Flag 457 * | | |This bit is set when Tx buffer overflow. 458 * | | |0 = Tx buffer is not overflow. 459 * | | |1 = Tx buffer is overflow when Tx buffer is full and an additional write operation to DAT (SCn_DAT[7:0]). 460 * | | |Note: This bit can be cleared by writing 1 to it. 461 * |[9] |TXEMPTY |Transmit Buffer Empty Status Flag (Read Only) 462 * | | |This bit indicates TX buffer empty or not. 463 * | | |0 = Tx buffer is not empty. 464 * | | |1 = Tx buffer is empty, it means the last byte of Tx buffer has been transferred to Transmitter 465 * | | |Shift Register. 466 * | | |Note: This bit will be cleared when writing data into DAT (SCn_DAT[7:0]). 467 * |[10] |TXFULL |Transmit Buffer Full Status Flag (Read Only) 468 * | | |This bit indicates Tx buffer full or not. 469 * | | |0 = Tx buffer count is less than 4. 470 * | | |1 = Tx buffer count equals to 4. 471 * |[11] |CREMOVE |Card Removal Status of SCn_CD Pin 472 * | | |This bit is set whenever card has been removal. 473 * | | |0 = No effect. 474 * | | |1 = Card removed. 475 * | | |Note1: This bit can be cleared by writing 1 to it. 476 * | | |Note2: Card detect function will start after SCEN (SCn_CTL[0]) set. 477 * |[12] |CINSERT |Card Insert Status of SCn_CD Pin 478 * | | |This bit is set whenever card has been inserted. 479 * | | |0 = No effect. 480 * | | |1 = Card insert. 481 * | | |Note1: This bit can be cleared by writing 1 to it. 482 * | | |Note2: The card detect function will start after SCEN (SCn_CTL[0]) set. 483 * |[13] |CDPINSTS |Card Detect Pin Status (Read Only) 484 * | | |This bit is the pin status of SCn_CD. 485 * | | |0 = The SCn_CD pin state at low. 486 * | | |1 = The SCn_CD pin state at high. 487 * |[18:16] |RXPOINT |Receive Buffer Pointer Status (Read Only) 488 * | | |This field indicates the Rx buffer pointer status 489 * | | |When SC controller receives one byte from external device, RXPOINT increases one 490 * | | |When one byte of Rx buffer is read by CPU, RXPOINT decreases one. 491 * |[21] |RXRERR |Receiver Retry Error 492 * | | |This bit is used for receiver error retry and set by hardware. 493 * | | |0 = No Rx retry transfer. 494 * | | |1 = Rx has any error and retries transfer. 495 * | | |Note1: This bit can be cleared by writing 1 to it. 496 * | | |Note2 This bit is a flag and cannot generate any interrupt to CPU. 497 * | | |Note3: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), 498 * | | |hardware will not set this flag. 499 * |[22] |RXOVERR |Receiver over Retry Error 500 * | | |This bit is used for receiver retry counts over than retry number limitation. 501 * | | |0 = Receiver retries counts is not over than RXRTY (SCn_CTL[18:16]) + 1. 502 * | | |1 = Receiver retries counts over than RXRTY (SCn_CTL[18:16]) + 1. 503 * | | |Note1: This bit can be cleared by writing 1 to it. 504 * | | |Note2: If CPU enables receiver retries function by setting RXRTYEN (SCn_CTL[19]), hardware 505 * | | |will not set this flag. 506 * |[23] |RXACT |Receiver in Active Status Flag (Read Only) 507 * | | |This bit indicates Rx transfer status. 508 * | | |0 = This bit is cleared automatically when Rx transfer is finished. 509 * | | |1 = This bit is set by hardware when Rx transfer is in active. 510 * | | |Note: This bit is read only. 511 * |[26:24] |TXPOINT |Transmit Buffer Pointer Status (Read Only) 512 * | | |This field indicates the Tx buffer pointer status 513 * | | |When CPU writes data into SCn_DAT, TXPOINT increases one 514 * | | |When one byte of Tx buffer is transferred to transmitter shift register, TXPOINT decreases one. 515 * |[29] |TXRERR |Transmitter Retry Error 516 * | | |This bit is used for indicate transmitter error retry and set by hardware. 517 * | | |0 = No Tx retry transfer. 518 * | | |1 = Tx has any error and retries transfer. 519 * | | |Note1: This bit can be cleared by writing 1 to it. 520 * | | |Note2: This bit is a flag and cannot generate any interrupt to CPU. 521 * |[30] |TXOVERR |Transmitter over Retry Error 522 * | | |This bit is used for transmitter retry counts over than retry number limitation. 523 * | | |0 = Transmitter retries counts is not over than TXRTY (SCn_CTL[22:20]) + 1. 524 * | | |1 = Transmitter retries counts over than TXRTY (SCn_CTL[22:20]) + 1. 525 * | | |Note: This bit can be cleared by writing 1 to it. 526 * |[31] |TXACT |Transmit in Active Status Flag (Read Only) 527 * | | |This bit indicates Tx transmit status. 528 * | | |0 = This bit is cleared automatically when Tx transfer is finished or the last byte transmission 529 * | | |has completed. 530 * | | |1 = Transmit is active and this bit is set by hardware when Tx transfer is in active and the STOP 531 * | | |bit of the last byte has not been transmitted. 532 * | | |Note: This bit is read only. 533 * @var SC_T::PINCTL 534 * Offset: 0x24 SC Pin Control State Register 535 * --------------------------------------------------------------------------------------------------- 536 * |Bits |Field |Descriptions 537 * | :----: | :----: | :---- | 538 * |[0] |PWREN |SCn_PWR Pin Signal 539 * | | |User can set PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]) to decide SCn_PWR pin is in high or low level. 540 * | | |Write this field to drive SCn_PWR pin 541 * | | |Refer PWRINV (SCn_PINCTL[11]) description for programming SCn_PWR pin voltage level. 542 * | | |Read this field to get SCn_PWR signal status. 543 * | | |0 = SCn_PWR signal status is low. 544 * | | |1 = SCn_PWR signal status is high. 545 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. 546 * | | |Thus, do not fill in this field when operating in these modes. 547 * |[1] |RSTEN |SCn_RST Pin Signal 548 * | | |User can set RSTEN (SCn_PINCTL[1]) to decide SCn_RST pin is in high or low level. 549 * | | |Write this field to drive SCn_RST pin. 550 * | | |0 = Drive SCn_RST pin to low. 551 * | | |1 = Drive SCn_RST pin to high. 552 * | | |Read this field to get SCn_RST signal status. 553 * | | |0 = SCn_RST signal status is low. 554 * | | |1 = SCn_RST signal status is high. 555 * | | |Note: When operating at activation, warm reset or deactivation mode, this bit will be changed automatically. 556 * | | |Thus, do not fill in this field when operating in these modes. 557 * |[6] |CLKKEEP |SC Clock Enable Bit 558 * | | |0 = SC clock generation Disabled. 559 * | | |1 = SC clock always keeps free running. 560 * | | |Note: When operating in activation, warm reset or deactivation mode, this bit will be changed automatically. 561 * | | |Thus, do not fill in this field when operating in these modes. 562 * |[9] |SCDATA |SCn_DATA Pin Signal 563 * | | |This bit is the signal status of SCn_DATA but user can drive SCn_DATA pin to high or low by setting this bit. 564 * | | |0 = Drive SCn_DATA pin to low. 565 * | | |1 = Drive SCn_DATA pin to high. 566 * | | |Read this field to get SCn_DATA signal status. 567 * | | |0 = SCn_DATA signal status is low. 568 * | | |1 = SCn_DATA signal status is high. 569 * | | |Note: When SC is at activation, warm reset or deactivation mode, this bit will be changed automatically. 570 * | | |Thus, do not fill in this field when SC is in these modes. 571 * |[11] |PWRINV |SCn_PWR Pin Inverse 572 * | | |This bit is used for inverse the SCn_PWR pin. 573 * | | |There are four kinds of combination for SCn_PWR pin setting by PWRINV (SCn_PINCTL[11]) and PWREN (SCn_PINCTL[0]). 574 * | | |PWRINV is 0 and PWREN is 0, SCn_PWR pin is 0. 575 * | | |PWRINV is 0 and PWREN is 1, SCn_PWR pin is 1. 576 * | | |PWRINV is 1 and PWREN is 0, SCn_PWR pin is 1. 577 * | | |PWRINV is 1 and PWREN is 1, SCn_PWR pin is 0. 578 * | | |Note: User must select PWRINV (SCn_PINCTL[11]) before smart card is enabled by SCEN (SCn_CTL[0]). 579 * |[16] |DATASTS |SCn_DATA Pin Status (Read Only) 580 * | | |This bit is the pin status of SCn_DATA. 581 * | | |0 = The SCn_DATA pin status is low. 582 * | | |1 = The SCn_DATA pin status is high. 583 * |[17] |PWRSTS |SCn_PWR Pin Status (Read Only) 584 * | | |This bit is the pin status of SCn_PWR. 585 * | | |0 = SCn_PWR pin to low. 586 * | | |1 = SCn_PWR pin to high. 587 * |[18] |RSTSTS |SCn_RST Pin Status (Read Only) 588 * | | |This bit is the pin status of SCn_RST. 589 * | | |0 = SCn_RST pin is low. 590 * | | |1 = SCn_RST pin is high. 591 * |[30] |SYNC |SYNC Flag Indicator (Read Only) 592 * | | |Due to synchronization, user should check this bit when writing a new value to SCn_PINCTL register. 593 * | | |0 = Synchronizing is completion, user can write new data to SCn_PINCTL register. 594 * | | |1 = Last value is synchronizing. 595 * @var SC_T::TMRCTL0 596 * Offset: 0x28 SC Internal Timer0 Control Register 597 * --------------------------------------------------------------------------------------------------- 598 * |Bits |Field |Descriptions 599 * | :----: | :----: | :---- | 600 * |[23:0] |CNT |Timer0 Counter Value 601 * | | |This field indicates the internal Timer0 counter values. 602 * | | |Note: Unit of Timer0 counter is ETU base. 603 * |[27:24] |OPMODE |Timer0 Operation Mode Selection 604 * | | |This field indicates the internal 24-bit Timer0 operation selection. 605 * | | |Refer to Table 7.17-3 for programming Timer0. 606 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 607 * | | |Due to synchronization, user should check this bit when writing a new value to the SCn_TMRCTL0 register. 608 * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL0 register. 609 * | | |1 = Last value is synchronizing. 610 * @var SC_T::TMRCTL1 611 * Offset: 0x2C SC Internal Timer1 Control Register 612 * --------------------------------------------------------------------------------------------------- 613 * |Bits |Field |Descriptions 614 * | :----: | :----: | :---- | 615 * |[7:0] |CNT |Timer 1 Counter Value 616 * | | |This field indicates the internal Timer1 counter values. 617 * | | |Note: Unit of Timer1 counter is ETU base. 618 * |[27:24] |OPMODE |Timer 1 Operation Mode Selection 619 * | | |This field indicates the internal 8-bit Timer1 operation selection. 620 * | | |Refer to Table 7.17-3 for programming Timer1. 621 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 622 * | | |Due to synchronization, software should check this bit when writing a new value to SCn_TMRCTL1 register. 623 * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL1 register. 624 * | | |1 = Last value is synchronizing. 625 * @var SC_T::TMRCTL2 626 * Offset: 0x30 SC Internal Timer2 Control Register 627 * --------------------------------------------------------------------------------------------------- 628 * |Bits |Field |Descriptions 629 * | :----: | :----: | :---- | 630 * |[7:0] |CNT |Timer 2 Counter Value 631 * | | |This field indicates the internal Timer2 counter values. 632 * | | |Note: Unit of Timer2 counter is ETU base. 633 * |[27:24] |OPMODE |Timer 2 Operation Mode Selection 634 * | | |This field indicates the internal 8-bit Timer2 operation selection 635 * | | |Refer to Table 7.17-3 for programming Timer2. 636 * |[31] |SYNC |SYNC Flag Indicator (Read Only) 637 * | | |Due to synchronization, user should check this bit when writing a new value to SCn_TMRCTL2 register. 638 * | | |0 = Synchronizing is completion, user can write new data to SCn_TMRCTL2 register. 639 * | | |1 = Last value is synchronizing. 640 * @var SC_T::UARTCTL 641 * Offset: 0x34 SC UART Mode Control Register 642 * --------------------------------------------------------------------------------------------------- 643 * |Bits |Field |Descriptions 644 * | :----: | :----: | :---- | 645 * |[0] |UARTEN |UART Mode Enable Bit 646 * | | |Sets this bit to enable UART mode function. 647 * | | |0 = Smart Card mode. 648 * | | |1 = UART mode. 649 * | | |Note1: When operating in UART mode, user must set CONSEL (SCn_CTL[5:4]) = 00 and AUTOCEN (SCn_CTL[3]) = 0. 650 * | | |Note2: When operating in Smart Card mode, user must set UARTEN (SCn_UARTCTL[0]) = 0. 651 * | | |Note3: When UART mode is enabled, hardware will generate a reset to reset FIFO and internal state machine. 652 * |[5:4] |WLS |Word Length Selection 653 * | | |This field is used for select UART data length. 654 * | | |00 = Word length is 8 bits. 655 * | | |01 = Word length is 7 bits. 656 * | | |10 = Word length is 6 bits. 657 * | | |11 = Word length is 5 bits. 658 * | | |Note: In smart card mode, this WLS must be '00'. 659 * |[6] |PBOFF |Parity Bit Disable Control 660 * | | |Sets this bit is used for disable parity check function. 661 * | | |0 = Parity bit is generated or checked between the last data word bit and stop bit of the serial data. 662 * | | |1 = Parity bit is not generated (transmitting data) or checked (receiving data) during transfer. 663 * | | |Note: In smart card mode, this field must be '0' (default setting is with parity bit). 664 * |[7] |OPE |Odd Parity Enable Bit 665 * | | |This is used for odd/even parity selection. 666 * | | |0 = Even number of logic 1's are transmitted or check the data word and parity bits in receiving mode. 667 * | | |1 = Odd number of logic 1's are transmitted or check the data word and parity bits in receiving mode. 668 * | | |Note: This bit has effect only when PBOFF bit is '0'. 669 * @var SC_T::ACTCTL 670 * Offset: 0x4C SC Activation Control Register 671 * --------------------------------------------------------------------------------------------------- 672 * |Bits |Field |Descriptions 673 * | :----: | :----: | :---- | 674 * |[4:0] |T1EXT |T1 Extend Time of Hardware Activation 675 * | | |This field provide the configurable cycles to extend the activation time T1 period. 676 * | | |The cycle scaling factor is 2048. 677 * | | |Extend cycles = (filled value * 2048) cycles. 678 * | | |Refer to SC activation sequence in Figure 7.17-4. 679 * | | |For example, 680 * | | |SCLK = 4MHz, each cycle = 0.25us,. 681 * | | |Filled 20 to this field 682 * | | |Extend time = 20 * 2048 * 0.25us = 10.24 ms. 683 * | | |Note: Setting 0 to this field conforms to the protocol ISO/IEC 7816-3 684 */ 685 __IO uint32_t DAT; /*!< [0x0000] SC Receive/Transmit Holding Buffer Register */ 686 __IO uint32_t CTL; /*!< [0x0004] SC Control Register */ 687 __IO uint32_t ALTCTL; /*!< [0x0008] SC Alternate Control Register */ 688 __IO uint32_t EGT; /*!< [0x000c] SC Extra Guard Time Register */ 689 __IO uint32_t RXTOUT; /*!< [0x0010] SC Receive Buffer Time-out Counter Register */ 690 __IO uint32_t ETUCTL; /*!< [0x0014] SC Element Time Unit Control Register */ 691 __IO uint32_t INTEN; /*!< [0x0018] SC Interrupt Enable Control Register */ 692 __IO uint32_t INTSTS; /*!< [0x001c] SC Interrupt Status Register */ 693 __IO uint32_t STATUS; /*!< [0x0020] SC Transfer Status Register */ 694 __IO uint32_t PINCTL; /*!< [0x0024] SC Pin Control State Register */ 695 __IO uint32_t TMRCTL0; /*!< [0x0028] SC Internal Timer0 Control Register */ 696 __IO uint32_t TMRCTL1; /*!< [0x002c] SC Internal Timer1 Control Register */ 697 __IO uint32_t TMRCTL2; /*!< [0x0030] SC Internal Timer2 Control Register */ 698 __IO uint32_t UARTCTL; /*!< [0x0034] SC UART Mode Control Register */ 699 /** @cond HIDDEN_SYMBOLS */ 700 __I uint32_t RESERVE0[5]; 701 /** @endcond */ 702 __IO uint32_t ACTCTL; /*!< [0x004c] SC Activation Control Register */ 703 704 } SC_T; 705 706 /** 707 @addtogroup SC_CONST SC Bit Field Definition 708 Constant Definitions for SC Controller 709 @{ */ 710 711 #define SC_DAT_DAT_Pos (0) /*!< SC_T::DAT: DAT Position */ 712 #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) /*!< SC_T::DAT: DAT Mask */ 713 714 #define SC_CTL_SCEN_Pos (0) /*!< SC_T::CTL: SCEN Position */ 715 #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) /*!< SC_T::CTL: SCEN Mask */ 716 717 #define SC_CTL_RXOFF_Pos (1) /*!< SC_T::CTL: RXOFF Position */ 718 #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) /*!< SC_T::CTL: RXOFF Mask */ 719 720 #define SC_CTL_TXOFF_Pos (2) /*!< SC_T::CTL: TXOFF Position */ 721 #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) /*!< SC_T::CTL: TXOFF Mask */ 722 723 #define SC_CTL_AUTOCEN_Pos (3) /*!< SC_T::CTL: AUTOCEN Position */ 724 #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) /*!< SC_T::CTL: AUTOCEN Mask */ 725 726 #define SC_CTL_CONSEL_Pos (4) /*!< SC_T::CTL: CONSEL Position */ 727 #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) /*!< SC_T::CTL: CONSEL Mask */ 728 729 #define SC_CTL_RXTRGLV_Pos (6) /*!< SC_T::CTL: RXTRGLV Position */ 730 #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) /*!< SC_T::CTL: RXTRGLV Mask */ 731 732 #define SC_CTL_BGT_Pos (8) /*!< SC_T::CTL: BGT Position */ 733 #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) /*!< SC_T::CTL: BGT Mask */ 734 735 #define SC_CTL_TMRSEL_Pos (13) /*!< SC_T::CTL: TMRSEL Position */ 736 #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) /*!< SC_T::CTL: TMRSEL Mask */ 737 738 #define SC_CTL_NSB_Pos (15) /*!< SC_T::CTL: NSB Position */ 739 #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) /*!< SC_T::CTL: NSB Mask */ 740 741 #define SC_CTL_RXRTY_Pos (16) /*!< SC_T::CTL: RXRTY Position */ 742 #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) /*!< SC_T::CTL: RXRTY Mask */ 743 744 #define SC_CTL_RXRTYEN_Pos (19) /*!< SC_T::CTL: RXRTYEN Position */ 745 #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) /*!< SC_T::CTL: RXRTYEN Mask */ 746 747 #define SC_CTL_TXRTY_Pos (20) /*!< SC_T::CTL: TXRTY Position */ 748 #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) /*!< SC_T::CTL: TXRTY Mask */ 749 750 #define SC_CTL_TXRTYEN_Pos (23) /*!< SC_T::CTL: TXRTYEN Position */ 751 #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) /*!< SC_T::CTL: TXRTYEN Mask */ 752 753 #define SC_CTL_CDDBSEL_Pos (24) /*!< SC_T::CTL: CDDBSEL Position */ 754 #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) /*!< SC_T::CTL: CDDBSEL Mask */ 755 756 #define SC_CTL_CDLV_Pos (26) /*!< SC_T::CTL: CDLV Position */ 757 #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) /*!< SC_T::CTL: CDLV Mask */ 758 759 #define SC_CTL_SYNC_Pos (30) /*!< SC_T::CTL: SYNC Position */ 760 #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) /*!< SC_T::CTL: SYNC Mask */ 761 762 #define SC_ALTCTL_TXRST_Pos (0) /*!< SC_T::ALTCTL: TXRST Position */ 763 #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) /*!< SC_T::ALTCTL: TXRST Mask */ 764 765 #define SC_ALTCTL_RXRST_Pos (1) /*!< SC_T::ALTCTL: RXRST Position */ 766 #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) /*!< SC_T::ALTCTL: RXRST Mask */ 767 768 #define SC_ALTCTL_DACTEN_Pos (2) /*!< SC_T::ALTCTL: DACTEN Position */ 769 #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) /*!< SC_T::ALTCTL: DACTEN Mask */ 770 771 #define SC_ALTCTL_ACTEN_Pos (3) /*!< SC_T::ALTCTL: ACTEN Position */ 772 #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) /*!< SC_T::ALTCTL: ACTEN Mask */ 773 774 #define SC_ALTCTL_WARSTEN_Pos (4) /*!< SC_T::ALTCTL: WARSTEN Position */ 775 #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) /*!< SC_T::ALTCTL: WARSTEN Mask */ 776 777 #define SC_ALTCTL_CNTEN0_Pos (5) /*!< SC_T::ALTCTL: CNTEN0 Position */ 778 #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) /*!< SC_T::ALTCTL: CNTEN0 Mask */ 779 780 #define SC_ALTCTL_CNTEN1_Pos (6) /*!< SC_T::ALTCTL: CNTEN1 Position */ 781 #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) /*!< SC_T::ALTCTL: CNTEN1 Mask */ 782 783 #define SC_ALTCTL_CNTEN2_Pos (7) /*!< SC_T::ALTCTL: CNTEN2 Position */ 784 #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) /*!< SC_T::ALTCTL: CNTEN2 Mask */ 785 786 #define SC_ALTCTL_INITSEL_Pos (8) /*!< SC_T::ALTCTL: INITSEL Position */ 787 #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) /*!< SC_T::ALTCTL: INITSEL Mask */ 788 789 #define SC_ALTCTL_ADACEN_Pos (11) /*!< SC_T::ALTCTL: ADACEN Position */ 790 #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) /*!< SC_T::ALTCTL: ADACEN Mask */ 791 792 #define SC_ALTCTL_RXBGTEN_Pos (12) /*!< SC_T::ALTCTL: RXBGTEN Position */ 793 #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) /*!< SC_T::ALTCTL: RXBGTEN Mask */ 794 795 #define SC_ALTCTL_ACTSTS0_Pos (13) /*!< SC_T::ALTCTL: ACTSTS0 Position */ 796 #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) /*!< SC_T::ALTCTL: ACTSTS0 Mask */ 797 798 #define SC_ALTCTL_ACTSTS1_Pos (14) /*!< SC_T::ALTCTL: ACTSTS1 Position */ 799 #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) /*!< SC_T::ALTCTL: ACTSTS1 Mask */ 800 801 #define SC_ALTCTL_ACTSTS2_Pos (15) /*!< SC_T::ALTCTL: ACTSTS2 Position */ 802 #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) /*!< SC_T::ALTCTL: ACTSTS2 Mask */ 803 804 #define SC_ALTCTL_SYNC_Pos (31) /*!< SC_T::ALTCTL: SYNC Position */ 805 #define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) /*!< SC_T::ALTCTL: SYNC Mask */ 806 807 #define SC_EGT_EGT_Pos (0) /*!< SC_T::EGT: EGT Position */ 808 #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) /*!< SC_T::EGT: EGT Mask */ 809 810 #define SC_RXTOUT_RFTM_Pos (0) /*!< SC_T::RXTOUT: RFTM Position */ 811 #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) /*!< SC_T::RXTOUT: RFTM Mask */ 812 813 #define SC_ETUCTL_ETURDIV_Pos (0) /*!< SC_T::ETUCTL: ETURDIV Position */ 814 #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) /*!< SC_T::ETUCTL: ETURDIV Mask */ 815 816 #define SC_INTEN_RDAIEN_Pos (0) /*!< SC_T::INTEN: RDAIEN Position */ 817 #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) /*!< SC_T::INTEN: RDAIEN Mask */ 818 819 #define SC_INTEN_TBEIEN_Pos (1) /*!< SC_T::INTEN: TBEIEN Position */ 820 #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) /*!< SC_T::INTEN: TBEIEN Mask */ 821 822 #define SC_INTEN_TERRIEN_Pos (2) /*!< SC_T::INTEN: TERRIEN Position */ 823 #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) /*!< SC_T::INTEN: TERRIEN Mask */ 824 825 #define SC_INTEN_TMR0IEN_Pos (3) /*!< SC_T::INTEN: TMR0IEN Position */ 826 #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) /*!< SC_T::INTEN: TMR0IEN Mask */ 827 828 #define SC_INTEN_TMR1IEN_Pos (4) /*!< SC_T::INTEN: TMR1IEN Position */ 829 #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) /*!< SC_T::INTEN: TMR1IEN Mask */ 830 831 #define SC_INTEN_TMR2IEN_Pos (5) /*!< SC_T::INTEN: TMR2IEN Position */ 832 #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) /*!< SC_T::INTEN: TMR2IEN Mask */ 833 834 #define SC_INTEN_BGTIEN_Pos (6) /*!< SC_T::INTEN: BGTIEN Position */ 835 #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) /*!< SC_T::INTEN: BGTIEN Mask */ 836 837 #define SC_INTEN_CDIEN_Pos (7) /*!< SC_T::INTEN: CDIEN Position */ 838 #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) /*!< SC_T::INTEN: CDIEN Mask */ 839 840 #define SC_INTEN_INITIEN_Pos (8) /*!< SC_T::INTEN: INITIEN Position */ 841 #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) /*!< SC_T::INTEN: INITIEN Mask */ 842 843 #define SC_INTEN_RXTOIEN_Pos (9) /*!< SC_T::INTEN: RXTOIEN Position */ 844 #define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) /*!< SC_T::INTEN: RXTOIEN Mask */ 845 846 #define SC_INTEN_ACERRIEN_Pos (10) /*!< SC_T::INTEN: ACERRIEN Position */ 847 #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) /*!< SC_T::INTEN: ACERRIEN Mask */ 848 849 #define SC_INTSTS_RDAIF_Pos (0) /*!< SC_T::INTSTS: RDAIF Position */ 850 #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) /*!< SC_T::INTSTS: RDAIF Mask */ 851 852 #define SC_INTSTS_TBEIF_Pos (1) /*!< SC_T::INTSTS: TBEIF Position */ 853 #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) /*!< SC_T::INTSTS: TBEIF Mask */ 854 855 #define SC_INTSTS_TERRIF_Pos (2) /*!< SC_T::INTSTS: TERRIF Position */ 856 #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) /*!< SC_T::INTSTS: TERRIF Mask */ 857 858 #define SC_INTSTS_TMR0IF_Pos (3) /*!< SC_T::INTSTS: TMR0IF Position */ 859 #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) /*!< SC_T::INTSTS: TMR0IF Mask */ 860 861 #define SC_INTSTS_TMR1IF_Pos (4) /*!< SC_T::INTSTS: TMR1IF Position */ 862 #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) /*!< SC_T::INTSTS: TMR1IF Mask */ 863 864 #define SC_INTSTS_TMR2IF_Pos (5) /*!< SC_T::INTSTS: TMR2IF Position */ 865 #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) /*!< SC_T::INTSTS: TMR2IF Mask */ 866 867 #define SC_INTSTS_BGTIF_Pos (6) /*!< SC_T::INTSTS: BGTIF Position */ 868 #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) /*!< SC_T::INTSTS: BGTIF Mask */ 869 870 #define SC_INTSTS_CDIF_Pos (7) /*!< SC_T::INTSTS: CDIF Position */ 871 #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) /*!< SC_T::INTSTS: CDIF Mask */ 872 873 #define SC_INTSTS_INITIF_Pos (8) /*!< SC_T::INTSTS: INITIF Position */ 874 #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) /*!< SC_T::INTSTS: INITIF Mask */ 875 876 #define SC_INTSTS_RXTOIF_Pos (9) /*!< SC_T::INTSTS: RXTOIF Position */ 877 #define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) /*!< SC_T::INTSTS: RXTOIF Mask */ 878 879 #define SC_INTSTS_ACERRIF_Pos (10) /*!< SC_T::INTSTS: ACERRIF Position */ 880 #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) /*!< SC_T::INTSTS: ACERRIF Mask */ 881 882 #define SC_STATUS_RXOV_Pos (0) /*!< SC_T::STATUS: RXOV Position */ 883 #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) /*!< SC_T::STATUS: RXOV Mask */ 884 885 #define SC_STATUS_RXEMPTY_Pos (1) /*!< SC_T::STATUS: RXEMPTY Position */ 886 #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) /*!< SC_T::STATUS: RXEMPTY Mask */ 887 888 #define SC_STATUS_RXFULL_Pos (2) /*!< SC_T::STATUS: RXFULL Position */ 889 #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) /*!< SC_T::STATUS: RXFULL Mask */ 890 891 #define SC_STATUS_PEF_Pos (4) /*!< SC_T::STATUS: PEF Position */ 892 #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) /*!< SC_T::STATUS: PEF Mask */ 893 894 #define SC_STATUS_FEF_Pos (5) /*!< SC_T::STATUS: FEF Position */ 895 #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) /*!< SC_T::STATUS: FEF Mask */ 896 897 #define SC_STATUS_BEF_Pos (6) /*!< SC_T::STATUS: BEF Position */ 898 #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) /*!< SC_T::STATUS: BEF Mask */ 899 900 #define SC_STATUS_TXOV_Pos (8) /*!< SC_T::STATUS: TXOV Position */ 901 #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) /*!< SC_T::STATUS: TXOV Mask */ 902 903 #define SC_STATUS_TXEMPTY_Pos (9) /*!< SC_T::STATUS: TXEMPTY Position */ 904 #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) /*!< SC_T::STATUS: TXEMPTY Mask */ 905 906 #define SC_STATUS_TXFULL_Pos (10) /*!< SC_T::STATUS: TXFULL Position */ 907 #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) /*!< SC_T::STATUS: TXFULL Mask */ 908 909 #define SC_STATUS_CREMOVE_Pos (11) /*!< SC_T::STATUS: CREMOVE Position */ 910 #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) /*!< SC_T::STATUS: CREMOVE Mask */ 911 912 #define SC_STATUS_CINSERT_Pos (12) /*!< SC_T::STATUS: CINSERT Position */ 913 #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) /*!< SC_T::STATUS: CINSERT Mask */ 914 915 #define SC_STATUS_CDPINSTS_Pos (13) /*!< SC_T::STATUS: CDPINSTS Position */ 916 #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) /*!< SC_T::STATUS: CDPINSTS Mask */ 917 918 #define SC_STATUS_RXPOINT_Pos (16) /*!< SC_T::STATUS: RXPOINT Position */ 919 #define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) /*!< SC_T::STATUS: RXPOINT Mask */ 920 921 #define SC_STATUS_RXRERR_Pos (21) /*!< SC_T::STATUS: RXRERR Position */ 922 #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) /*!< SC_T::STATUS: RXRERR Mask */ 923 924 #define SC_STATUS_RXOVERR_Pos (22) /*!< SC_T::STATUS: RXOVERR Position */ 925 #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) /*!< SC_T::STATUS: RXOVERR Mask */ 926 927 #define SC_STATUS_RXACT_Pos (23) /*!< SC_T::STATUS: RXACT Position */ 928 #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) /*!< SC_T::STATUS: RXACT Mask */ 929 930 #define SC_STATUS_TXPOINT_Pos (24) /*!< SC_T::STATUS: TXPOINT Position */ 931 #define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) /*!< SC_T::STATUS: TXPOINT Mask */ 932 933 #define SC_STATUS_TXRERR_Pos (29) /*!< SC_T::STATUS: TXRERR Position */ 934 #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) /*!< SC_T::STATUS: TXRERR Mask */ 935 936 #define SC_STATUS_TXOVERR_Pos (30) /*!< SC_T::STATUS: TXOVERR Position */ 937 #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) /*!< SC_T::STATUS: TXOVERR Mask */ 938 939 #define SC_STATUS_TXACT_Pos (31) /*!< SC_T::STATUS: TXACT Position */ 940 #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) /*!< SC_T::STATUS: TXACT Mask */ 941 942 #define SC_PINCTL_PWREN_Pos (0) /*!< SC_T::PINCTL: PWREN Position */ 943 #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) /*!< SC_T::PINCTL: PWREN Mask */ 944 945 #define SC_PINCTL_RSTEN_Pos (1) /*!< SC_T::PINCTL: RSTEN Position */ 946 #define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) /*!< SC_T::PINCTL: RSTEN Mask */ 947 948 #define SC_PINCTL_CLKKEEP_Pos (6) /*!< SC_T::PINCTL: CLKKEEP Position */ 949 #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) /*!< SC_T::PINCTL: CLKKEEP Mask */ 950 951 #define SC_PINCTL_SCDATA_Pos (9) /*!< SC_T::PINCTL: SCDATA Position */ 952 #define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) /*!< SC_T::PINCTL: SCDATA Mask */ 953 954 #define SC_PINCTL_PWRINV_Pos (11) /*!< SC_T::PINCTL: PWRINV Position */ 955 #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) /*!< SC_T::PINCTL: PWRINV Mask */ 956 957 #define SC_PINCTL_DATASTS_Pos (16) /*!< SC_T::PINCTL: DATASTS Position */ 958 #define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) /*!< SC_T::PINCTL: DATASTS Mask */ 959 960 #define SC_PINCTL_PWRSTS_Pos (17) /*!< SC_T::PINCTL: PWRSTS Position */ 961 #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) /*!< SC_T::PINCTL: PWRSTS Mask */ 962 963 #define SC_PINCTL_RSTSTS_Pos (18) /*!< SC_T::PINCTL: RSTSTS Position */ 964 #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) /*!< SC_T::PINCTL: RSTSTS Mask */ 965 966 #define SC_PINCTL_SYNC_Pos (30) /*!< SC_T::PINCTL: SYNC Position */ 967 #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) /*!< SC_T::PINCTL: SYNC Mask */ 968 969 #define SC_TMRCTL0_CNT_Pos (0) /*!< SC_T::TMRCTL0: CNT Position */ 970 #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) /*!< SC_T::TMRCTL0: CNT Mask */ 971 972 #define SC_TMRCTL0_OPMODE_Pos (24) /*!< SC_T::TMRCTL0: OPMODE Position */ 973 #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) /*!< SC_T::TMRCTL0: OPMODE Mask */ 974 975 #define SC_TMRCTL0_SYNC_Pos (31) /*!< SC_T::TMRCTL0: SYNC Position */ 976 #define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) /*!< SC_T::TMRCTL0: SYNC Mask */ 977 978 #define SC_TMRCTL1_CNT_Pos (0) /*!< SC_T::TMRCTL1: CNT Position */ 979 #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) /*!< SC_T::TMRCTL1: CNT Mask */ 980 981 #define SC_TMRCTL1_OPMODE_Pos (24) /*!< SC_T::TMRCTL1: OPMODE Position */ 982 #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) /*!< SC_T::TMRCTL1: OPMODE Mask */ 983 984 #define SC_TMRCTL1_SYNC_Pos (31) /*!< SC_T::TMRCTL1: SYNC Position */ 985 #define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) /*!< SC_T::TMRCTL1: SYNC Mask */ 986 987 #define SC_TMRCTL2_CNT_Pos (0) /*!< SC_T::TMRCTL2: CNT Position */ 988 #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) /*!< SC_T::TMRCTL2: CNT Mask */ 989 990 #define SC_TMRCTL2_OPMODE_Pos (24) /*!< SC_T::TMRCTL2: OPMODE Position */ 991 #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) /*!< SC_T::TMRCTL2: OPMODE Mask */ 992 993 #define SC_TMRCTL2_SYNC_Pos (31) /*!< SC_T::TMRCTL2: SYNC Position */ 994 #define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) /*!< SC_T::TMRCTL2: SYNC Mask */ 995 996 #define SC_UARTCTL_UARTEN_Pos (0) /*!< SC_T::UARTCTL: UARTEN Position */ 997 #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) /*!< SC_T::UARTCTL: UARTEN Mask */ 998 999 #define SC_UARTCTL_WLS_Pos (4) /*!< SC_T::UARTCTL: WLS Position */ 1000 #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) /*!< SC_T::UARTCTL: WLS Mask */ 1001 1002 #define SC_UARTCTL_PBOFF_Pos (6) /*!< SC_T::UARTCTL: PBOFF Position */ 1003 #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) /*!< SC_T::UARTCTL: PBOFF Mask */ 1004 1005 #define SC_UARTCTL_OPE_Pos (7) /*!< SC_T::UARTCTL: OPE Position */ 1006 #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) /*!< SC_T::UARTCTL: OPE Mask */ 1007 1008 #define SC_ACTCTL_T1EXT_Pos (0) /*!< SC_T::ACTCTL: T1EXT Position */ 1009 #define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) /*!< SC_T::ACTCTL: T1EXT Mask */ 1010 1011 /**@}*/ /* SC_CONST */ 1012 /**@}*/ /* end of SC register group */ 1013 /**@}*/ /* end of REGISTER group */ 1014 1015 #if defined ( __CC_ARM ) 1016 #pragma no_anon_unions 1017 #endif 1018 1019 #endif /* __SC_REG_H__ */ 1020
