| /hal_nxp-2.7.6/mcux/devices/MKL25Z4/ |
| D | MKL25Z4.h | 606 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1021/ |
| D | MIMXRT1021.h | 8716 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
24952 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
35911 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
36483 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1024/ |
| D | MIMXRT1024.h | 8698 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
24934 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
35893 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
36465 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1051/ |
| D | MIMXRT1051.h | 8542 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
22863 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
32869 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
33354 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1011/ |
| D | MIMXRT1011.h | 15609 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
24436 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
24924 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1052/ |
| D | MIMXRT1052.h | 9754 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
28517 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
41296 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
41865 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1061/ |
| D | MIMXRT1061.h | 9731 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
24466 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
35274 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
35762 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
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| /hal_nxp-2.7.6/mcux/devices/MIMXRT1015/ |
| D | MIMXRT1015.h | 18300 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
26756 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
27244 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1062/ |
| D | MIMXRT1062.h | 11092 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
30292 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
43952 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
44524 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MIMXRT1064/ |
| D | MIMXRT1064.h | 11040 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
30218 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
43878 __IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */ member
44450 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW24D5/ |
| D | MKW24D5.h | 1157 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MKW22D5/ |
| D | MKW22D5.h | 1157 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MK22F51212/ |
| D | MK22F51212.h | 868 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MKE16F16/ |
| D | MKE16F16.h | 8204 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKE18F16/ |
| D | MKE18F16.h | 8209 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKE14F16/ |
| D | MKE14F16.h | 7400 __IO uint32_t SCR; /**< Slave Control Register, offset: 0x110 */ member
|
| /hal_nxp-2.7.6/mcux/devices/MKW31Z4/ |
| D | MKW31Z4.h | 972 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
|
| /hal_nxp-2.7.6/mcux/devices/MK64F12/ |
| D | MK64F12.h | 6530 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
|
| /hal_nxp-2.7.6/mcux/devices/MKW21Z4/ |
| D | MKW21Z4.h | 901 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MKW41Z4/ |
| D | MKW41Z4.h | 972 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
|
| /hal_nxp-2.7.6/mcux/devices/MKW40Z4/ |
| D | MKW40Z4.h | 713 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MKV56F24/ |
| D | MKV56F24.h | 5928 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MKW20Z4/ |
| D | MKW20Z4.h | 713 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/mcux/devices/MKW30Z4/ |
| D | MKW30Z4.h | 713 …__IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3… member
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| /hal_nxp-2.7.6/imx/devices/MCIMX6X/ |
| D | MCIMX6X_M4.h | 33784 …__IO uint32_t SCR; /**< SPDIF Configuration Register, offset: … member
34154 __IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */ member
34403 __IO uint32_t SCR; /**< SSI Control Register, offset: 0x10 */ member
|
